JPH06151870A - EEPROM semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] The present invention is an EEP capable of improving reliability without causing a voltage drop and reducing cost.
It is to provide a ROM semiconductor memory device. A memory cell has a first select transistor used for writing and erasing, a second select transistor used in parallel with the first select transistor and used for reading, and a serial relationship with the first select transistor and the second select transistor. It is composed of a certain memory transistor. The first select transistor is an I-type or D-type N-channel transistor, the second select transistor is an E-type N-channel transistor, and the memory transistor is an I-type N-channel transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of an EEPROM semiconductor memory device.

[0002]

2. Description of the Related Art A memory cell of a conventional EEPROM semiconductor memory device will be described with reference to FIG. In terms of an equivalent circuit, it is composed of a select transistor including an E-type N-channel transistor and a memory transistor including an I-type N-channel transistor connected in series with the select transistor.
The operation is as follows. When erasing data,
The drain and source are set to 0 V, the select gate and control gate are set to V _pp potential, and the flow is set by capacitive coupling.
The potential of the floating gate is raised and electrons are injected into the floating gate. When writing data, control gauge
The source is set to 0 V, the source is set to a floating state, the select gate and the drain are set to V _pp potential, and a potential difference opposite to that at the time of erasing is generated to emit electrons from the floating gate. When reading data, drain and control gauge
The gate is set to 0 V, the select gate and the source are set to the _Vcc potential, and the data is judged by whether or not a current flows.

Here, when reading data, an E-type transistor is used as the select transistor in order to prevent a leak current in non-selected cells on the same bit line. However, when writing data, the potential at (A) required for writing causes a voltage drop due to the back gate bias effect due to the presence of the E-type select transistor. Therefore, the potential in (A) becomes smaller than the V _pp potential which is the potential of the drain. For example, V
_{When the pp} potential is about 20V, the voltage drop is about 2.5V, and the potential of (A) is about 17.5V. Therefore,
Even when the required potential at the time of writing is about 17.5V,
It is necessary to set the withstand voltage of the device around it as high as about 20V.

[0004]

As described above, the use of the E-type select transistor as the select transistor is effective in preventing malfunction of non-selected cells on the same bit line when reading data. When writing data, it is necessary to cause a voltage drop and increase the breakdown voltage of peripheral elements. Therefore, while the E-type transistor enhances reliability,
There is a problem that the cost increases as well as the number of special processes for increasing the withstand voltage.

Therefore, an object of the present invention is to provide an EEPROM semiconductor memory device capable of improving reliability without causing a voltage drop and reducing the cost.

[0006]

EEPRO according to the present invention
One memory cell of the M semiconductor memory device includes a select transistor having a first select transistor for writing and erasing and a second select transistor for reading,
It is composed of a memory transistor. The first select transistor is an I-type (intrinsic type) or D-type (depletion type) N-channel transistor, and the second select transistor is an E-type (enhancement type) N-channel transistor. The floating gate of the memory transistor is capacitively coupled to the source of the first select transistor through the tunnel oxide film.

[0007]

According to the above structure, the write and erase paths and the read path are completely separated. Therefore, since the first select transistor is used at the time of writing, no voltage drop occurs, and the V _pp potential applied at the time of writing can be used as the write potential. As a result, it is not necessary to increase the breakdown voltage of the peripheral elements due to the voltage drop. . Further, since the second select transistor is used during reading, a desired memory cell can be selected and reliability can be guaranteed.

[0008]

1 is a block diagram showing an embodiment of an EEPROM according to the present invention.
2 to FIG.

As shown in FIG. 1, the memory cell includes a first select transistor used for writing and erasing, a second select transistor used in reading for paralleling the first select transistor, the first select transistor and the first select transistor. Two select transistors and a memory transistor in series relation. The first select transistor includes a first drain 11 and a first source 12.
And an I-type or D-type N-channel transistor including a select gate 13. The second select transistor is an E-type N-channel transistor including a second drain 14, a second source 15, and a select gate 13. The memory transistor has a drain 16 electrically connected to the second source 15, a source 17, and a flow capacitively coupled to the first source 12 at a capacitive coupling portion (circled).
It is an I-type N-channel transistor including a gate 18 and a control gate 19.

The structure of the memory transistor will be described with reference to FIG. The P-type semiconductor substrate 20 is element-isolated by a field oxide film 21, and an N-type diffusion layer serving as the first source 12 of the first select transistor and the drain 16 and source 17 of the memory transistor is formed. To be done. The memory transistor has a drain 16 and a source 17.
The gate oxide film 22 is sequentially formed on the upper surface, the floating gate 18 made of polycrystalline silicon, the insulating film 23 and the control gate 19 made of polycrystalline silicon. Here, the floating 18 is the first source 12 of the first select transistor and the thin tunnel oxide film 24.
Is capacitively coupled via.

Next, the operation principle will be described. When reading data, the first drain 11, the control gate 19 and the source 17 are set to 0V, the second drain 14 and the select gate are set.
The gate 13 is set to the _Vcc potential, and the current is turned on and off depending on the charged state of the floating gate 18 of the memory transistor.
Judge by FF. Second drain 1 when writing data
4, control - Ruge - DOO 19 and source - to set the door 13 to the V _pp voltage - the scan 17 0V, the first drain 11 and Serekutoge. De - data erasing, second drain 14 and source - to set the door 19 to the V _pp voltage - scan 17, the first drain 11 0V, Serekutoge - DOO 13 and control - Ruge.

As described above, by separating the select transistor for selecting the memory cell for writing and erasing and for reading, the first select transistor for writing and erasing can be I type or D type. is there. Therefore, the voltage drop in the first select transistor can be prevented. For example, if the V _pp potential is 20 V, the voltage drop is 1 V when the first select transistor is I-type.
In the case of the D type, no voltage drop occurs.
Therefore, the potential at the point (A) (shown in FIG. 1) necessary for writing in the data writing operation can be made substantially equal to the V _pp potential.

[0013]

According to the present invention, by separating the writing and erasing paths from the reading path, it becomes possible to use I-type or D-type select transistors for writing and erasing. Therefore, the voltage drop of the V _pp potential during the write operation can be almost eliminated, and as a result, it becomes unnecessary to increase the withstand voltage of the peripheral elements due to the voltage drop, and the V _pp potential can be reduced. Furthermore, the reliability of the device is improved and the manufacturing cost is reduced.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell of an EEPROM according to the present invention.

FIG. 2 is a sectional view schematically showing a structure of a memory transistor in a memory cell of an EEPROM according to the present invention.

FIG. 3 is an equivalent circuit diagram of a memory cell of a conventional EEPROM.

[Explanation of symbols]

11 ... First drain, 12 ... First source, 13 ... Select gate 14 ... Second drain, 15 ... Second source, 16 ... Drain, 17 ... Source 18 ... Floating gate, 19 ... Controllage
20 ... Semiconductor substrate, 21 ... Field oxide film, 22 ... Gate oxide film 23 ... Insulating film, 24 ... Tunnel oxide film

Claims (2)

[Claims] 1. A semiconductor substrate having at least one selection gate, a control gate and a floating gate arranged in one storage unit area, and a first gate formed by the selection gate. A selection transistor and a second selection transistor formed by the same selection gate are provided, and at least a part of the floating source region of the first selection transistor has a thin tunnel insulating film. Through the capacitive coupling with the floating gate, and the drain of the memory transistor formed by the floating gate is electrically connected to the source of the second select transistor. A non-volatile semiconductor device characterized by being. 2. The first selection transistor is an intrinsic or depletion type N-channel transistor, the storage transistor is an intrinsic N-channel transistor, and the second selection transistor is an Harassment type N
A channel transistor is a channel transistor.
The nonvolatile semiconductor device described.