JPH0614534B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit using a thermionic emission type static induction transistor.

[Prior art and its problems]

An electrostatic induction transistor (hereinafter abbreviated as SIT) controls the current between the source region and the drain region by changing the height of a potential barrier generated by connecting a depletion layer between gate regions. It is a transistor. At this time, since the control of the potential is performed through the capacitance of the depletion layer, it is equivalent to that of the bipolar transistor which does not have the storage capacitance of the base layer, and it operates at a very high speed and low noise as compared with the FET. It has excellent characteristics.

However, in the conventional SIT, between the source region and the drain region,
In particular, since the size between the source region and the gate region has a relatively large structure, there is a problem in that the canria is scattered by the crystal lattice and the upper limit frequency is limited.

[Object of the Invention]

It is an object of the present invention to solve the conventional problems described above and to provide a semiconductor integrated circuit using a novel thermionic emission type SIT in which carriers can move at a thermionic velocity without being scattered by a crystal lattice. And

[Outline of Invention]

The present invention provides a first drain region formed of a high-concentration impurity region of the first conductivity type in a part of an intrinsic or semi-insulating substrate,
A first channel region, a first source region formed of a first-conductivity-type high-impurity-density region are formed vertically on the first drain region, and the first channel region is provided with a first source region in the peripheral portion.
The first gate region is formed of a semiconductor having a forbidden band width larger than that of the channel region, and the dimension between the first source region and the true first gate region is set to be equal to or smaller than the mean free path of carriers, and a normally-off type driving thermoelectron. A radiation type electrostatic induction transistor is formed, and the first drain region is used as a second source region in a region adjacent to the driving thermoelectron radiation type static induction transistor, and a second source region is formed on the second source region.
A channel region and a second drain region composed of a first-conductivity-type high-impurity-density region are formed vertically, and a semiconductor having a forbidden band width larger than that of the second channel region is used in the peripheral portion of the second channel region. A normally-on type load static induction transistor is formed by forming a second gate region thinner than the first gate region, and is in contact with the first gate region of the driving thermionic emission type static induction transistor. The formed electrode has a signal input terminal, the electrode formed in contact with the first source region has a ground terminal, the electrode formed in contact with the first drain region has an output terminal, and the second electrode of the load static induction transistor. It is characterized in that an integrated circuit is configured by providing power supply terminals to electrodes formed in contact with the drain region.

Example of Invention

When the size is reduced in order to increase the speed of the electrostatic induction transistor, all that exceeds the potential peak (barrier) on the front surface of the electrode formed in contact with the source region runs to the drain side, When the width of this barrier becomes close to the mean free path of the carriers, the carriers will be traveling at a very high speed almost without relying on the lattice scattering.

The current density J at this time is given by the following equation (1).

Here, q is a unit charge, k is a Boltzmann constant, T is an absolute temperature, m ^* is an effective mass of carriers, ns is an impurity density of a source region, φ _GS is a diffusion potential of a gate region and a source region,
V _G is the potential applied to the gate region.

S when the carrier injection state becomes the thermionic emission state
The cut-off frequency fc of IT is given by the following equation (2) when the width of the potential barrier is set to Wg and the input capacitance of the second stage is considered by connecting SIT in cascade.

Therefore, when GaAs is used, the width Wg of the potential barrier is 0.
The cutoff frequency fc is approximately 780 GH when 1 μm is set.
It is about z.

From the above, if the size between the source region and the true gate region is made equal to or smaller than the mean free path of the carriers and the SIT has a thermionic emission structure, the switching time becomes short, and the carriers are not scattered and the true An excellent transistor for an integrated circuit can be obtained in which gm (transconductance) is easily increased to travel over the gate region and the current driving capability is high.

Here, the true gate region is the highest point of the potential barrier generated in the vicinity of the source region in the channel during the tunnel injection type SIT operation. When the channel width (the size between the source region and the drain region in the channel region) is short, the position where the true gate region is generated can be almost near the source region without being affected by the drain voltage.

Hereinafter, an integrated circuit using this thermionic emission type SIT will be described.

FIG. 1 is a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1 is an intrinsic semiconductor or semi-insulating GaGs substrate, 2 is a drain region of a driving thermoelectron emission type SIT, 3 is a channel region, and 4 is a Ga having a larger forbidden band than GaAs forming the channel region 3. A heterojunction gate region formed using a material such as ₁ -xAlxAs or Ga ₁ -xAlxAs ₁ -yPy, 5 is a source region of a driving thermoelectron emission SIT, 8 is a gate electrode, 9 is a source electrode, and 10 is It is an output electrode.

Driving thermionic emission type SI formed on the left side of FIG.
A thermionic emission type SIT for load having the drain region 2 as a source region is formed in a region connected to T. Reference numeral 40 denotes a gate region formed of the same material as the gate region 4, but by forming the gate region 4 thinner than the gate region 4, a normally-on operation type SIT is formed to function as a load resistance. Reference numeral 45 is a drain region of the thermionic emission type SIT for load, and 91 is a drain electrode.

12 is an insulator such as Si ₃ N ₄ , SiO ₂ , and polyimide resin, 20
Is an input terminal, 21 is a ground single type provided on the source electrode,
22 is an output terminal and 23 is a power supply terminal.

The impurity density of each channel region 3 of the driving and loading thermionic emission type SIT is 10 ¹² to ¹⁸ cm ⁻³ , and the length of the channel is 0.1 to 1 μm so as to form a depletion layer during operation. Is less than the mean free path. The impurity density of the source region and the drain region is 10 ¹⁸ to ²⁰ cm.
^-3 , the composition of the heterojunction in the gate region is x = 0.3, y =
0. The electrode electrodes 9, 10 and 91 for the source electrode, the output and the power supply terminal are made of an alloy such as Au-Ge, Au-Ge-Ni, etc., and the gate electrode 8 is made of a heavy metal such as Al, Au, W, Pt, etc. To do.

FIG. 2 shows an equivalent circuit of FIG.

Reference numeral 30 denotes a thermionic emission type SIT formed on the left side of the sectional view of the semiconductor integrated circuit shown in FIG. 1, which has a normally-off characteristic, and 32 indicates a normally-on characteristic used as a load resistance formed on the right side of FIG. The equivalent circuit of SIT which it has is shown. Reference numerals 20, 21, 22, and 23 are an input terminal, a ground terminal, an output terminal, and a power supply terminal, respectively. Input terminal 2
When the input signal applied to 0 is “low”, the thermionic emission type SIT 30 is off and a “high” level is generated at the output terminal 22, and when the input signal becomes “high”, the thermionic emission type SIT 30 is
The IT 30 is turned on, a "low" level is generated at the output terminal 22, and the so-called inverter operation is performed. Where SIT
32 is made to function as a resistance equivalently by the normally-on operation.

As described above, the integrated circuit of this embodiment has the thermionic emission SI
Since T has a vertical structure, it is easy to set the channel length to 1000 Å or less, and the switching speed is the same as that of the conventional FE.
It is possible to realize an integrated circuit which is faster than T or HEMT and has lower power consumption. Further, since the wiring of the source region and the gate region formed on the upper portion is easy, the manufacturing becomes easier as compared with the integrated circuit by FET or HEMT which requires fine wiring of the source electrode, the gate electrode, and the drain electrode. Therefore, as a result of reducing the area required for the wiring portion to about 2/3, high integration can be realized.

〔The invention's effect〕

As described above, according to the present invention, the driving thermionic emission type SIT having the normally-off characteristic and the thermistor emitting type SIT for the load having the normally-on characteristic are connected in series to form an integrated circuit, so that the resistors are purposely separated. It is possible to efficiently form an integrated circuit in the same process without making it, and obtain a semiconductor integrated circuit that can be highly integrated at high speed with low power consumption.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. 1 ... Substrate, 2 ... Drain region, 3 ... Channel region, 4 ... Gate region, 5 ... Source region, 20 ... Input terminal, 21 ... Ground terminal, 22 ... Output terminal, 23 ...
… Power supply terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaoru Motoya 2-9-9 Yonegabukuro, Sendai-shi, Miyagi 406 (56) Reference JP-A-57-186374 (JP, A) Proceedings of the Federation Conference, pp. 537-540

Claims (2)

[Claims] 1. A first drain region formed of a high impurity density region of the first conductivity type is provided in a part of an intrinsic or semi-insulating substrate, and a first channel region and a first conductivity type are provided on the first drain region. A first source region formed of a high impurity density region is vertically formed, and a first gate region is formed in the peripheral portion of the first channel region with a semiconductor having a forbidden band width larger than that of the first channel region. 1 source region and true 1st
A dimension between the gate regions is equal to or less than the mean free path of carriers to form a normally-off type driving thermoelectron emission type electrostatic induction transistor, and in a region adjacent to the driving thermoelectron emission type electrostatic induction transistor, The first drain region is used as a second source region, a second channel region is formed on the second source region, a second drain region including a first-conductivity-type high impurity density region is formed vertically, and the second channel is formed. A thermionic emission type electrostatic load for electrostatic charging which is a normally-on type in which a second gate region thinner than the first gate region is formed using a semiconductor having a forbidden band width larger than that of the second channel region in the peripheral portion of the region. An induction transistor is formed, and an electrode formed in contact with the first gate region of the driving thermoelectron emission type electrostatic induction transistor is in contact with the signal input terminal and the first source region. The formed electrode is a ground terminal, the electrode formed in contact with the first drain region is an output terminal, and the electrode formed in contact with the second drain region of the thermionic emission type static induction transistor for load is a power supply terminal. A semiconductor integrated circuit characterized in that an integrated circuit is configured by providing each of them. 2. The method according to claim 1, wherein the channel region is CaAs and the gate region is Ga _{1 -x} Al _x As.
To Ga _1-x Al _x As _1-y P _y .