JPH0614437B2 - Variable speed decoding circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit which operates from low speed to high speed, and more particularly to a decoding circuit in the integrated circuit.

[Conventional technology]

As a decode circuit in a conventional integrated circuit, a static type using NAND or NOR is used in a small one.
A large-scale decoding circuit uses a dynamic type in order to reduce the number of elements used.

An example of this dynamic type is shown in FIG. 3 and will be briefly described.

FIG. 3 is a decoding circuit of 8 rows × 8 columns, CLK indicates a clock, I0 to I7 are input signals, O0 to O7 are output signals, INV is an inverter, AND0 to AND7 are 2-input AND gates, and TP0 to TP7. Is a precharge transistor, BUF0 to BUF7 are buffers, T07 and T70
And T77 are decode transistors. Also D0 to D7
Indicates a data line, and the code is determined by whether or not the decode transistors T07, T70, T77, etc. are arranged at the intersections of the outputs of the AND gates AND0 to AND7 and the data lines D0 to D7.

VDD indicates a power supply and GND indicates ground.

Next, the operation of the decoding circuit shown in FIG. 3 will be described.

First, when the clock CLK is at 0 level, the inverter INV
Output becomes 1 level and precharge transistor T
P0 to TP7 open and the power supply VDD to the data lines D0 to D7
From 1 level. At this time AND gate AND
0 to AND7 all output 0 level because the clock CLK is 0 level, and the decode transistor T07.
T70, T77, etc. are all closed. Next clock CL
When K becomes 1 level, precharge transistor TP0
-TP7 are closed, and AND gates AND0-AND7 output signals in phase with the input signals I0-I7.

Now the input signal I0 is at 1 level, and therefore the AND gate AND
If 0 outputs 1 level, the decode transistor T07 opens and the data line D7 is discharged from 1 level to 0 level. Then, the output signal 07 becomes 0 level via the buffer BUF7. Other than this AND
Outputs of gates AND0 to AND7 and data lines D0 to D7
If there is no decode transistor at the intersection of (for example, AN
The intersection of D gate AND0 and data line D0) and input signal I
When 0 to I7 are at 0 level and the decode transistors are still closed even if there is a decode transistor, the data lines D0 to D7 hold 1 level and the output signals O0 to O7 become 1 level. Third above
The decode circuit shown in the figure requires not only the precharge timing (clock CLK: 0) for precharging, but also the data lines D0 to D7 are set to a complete 1 level due to precharging, so that the data lines D0 to D0. It takes time to discharge D7 to the threshold voltage of the buffers BUF0 to BUF7, and there is a drawback that the access time from the input signals I0 to I7 to the output signals O0 to O7 is slow.

Therefore, the decoding circuit shown in FIG. 4 with the improved access time has come to be used now.

The decoding circuit of FIG. 4 will be briefly described.

In FIG. 4, I0 to I7 are input signals, O0 to O7 are output signals, INV0 to INV7 are inverters, and BUF0 to BUF0.
BUF7 is a buffer, T07, T70 and T77 are decode transistors, D0 to D7 are data lines, and GND is ground.

The operation of the decoding circuit shown in FIG.
The inputs and outputs of NV0 to INV7 are short-circuited and connected to the data lines D0 to D7 as a bias circuit. This bias value is set to a value slightly exceeding the threshold voltage of the buffers BUF0 to BUF7. Now input signal I
If 0 becomes 1 level, the decode transistor T
07 is opened, the data line D7 becomes lower than the threshold voltage of the buffer BUF7, and the output signal O7 becomes 0 level.

The input signals I0 to I7 when the force signals I0 to I7 are at 0 level
When there is no decode transistor at the intersection of the data lines D0 to D7, the data lines D0 to D7 are connected to the inverters I0 to I7.
The bias circuit causes the output signals O0 to O7 to be 1 level, which is a voltage higher than the threshold voltage of the buffers BUF0 to BUF7.

As described above, the decoding circuit of FIG. 4 does not require precharge timing as in the decoding of FIG. 3, and since the data lines D0 to D7 are voltages near the threshold voltage of the buffers BUF0 to BUF7, the switching speed is increased. Can be fast

[Problems to be Solved by the Invention] However, in the circuit of FIG. 4, since the inputs and outputs of the inverters I0 to I7 forming the bias circuit are short-circuited, current is always flowing, and the inputs of the buffers BUF0 to BUF7 are always present. However, since it is at an intermediate level, current always flows, and there is a drawback that current consumption increases. This drawback is a serious problem in that a large current flows through the decoding circuit even when the clock frequency of the integrated circuit including the decoding circuit is lowered to reduce the current consumption.

[Means for solving problems]

A decode circuit of the present invention includes a clock variable circuit and a decode circuit, the decode circuit includes a bias circuit and a precharge circuit, and the bias circuit or the precharge circuit is controlled by a signal for controlling the clock variable circuit. And a circuit for selectively switching.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a decoding circuit diagram showing an embodiment of the present invention.

In FIG. 1, φ is a clock input signal, HS is a clock speed switching signal, I0 to I7 are input signals, and O0 to O7 are output signals. DIV is a clock variable circuit, I is a power terminal of the clock variable circuit, S is a switching control input terminal of the clock variable circuit, and O is an output terminal of the clock variable circuit. Now, the clock input signal φ is input to the input terminal I of the clock variable circuit, and the clock speed switching signal HS is input to the switching control input terminal S of the clock variable circuit. CLK is a clock signal, which is an output signal of the output terminal O of the clock variable circuit DIV.

The clock variable circuit DIV has a clock speed switching signal HS.
When the clock speed switching signal HS is 0 level, it outputs to the output terminal O a signal having the same frequency as the clock input signal φ input to the input terminal I. A signal having a frequency half that of the clock input signal φ is output.

Although not shown, the clock signal CLK is also supplied to other units of the integrated circuit including the decoding circuit of FIG.

The OR is an OR gate and receives the clock signal CLK and the clock speed switching signal HS. INV8 is an inverter O
The output of the R gate OR is input. AND0 to AND7
Is an AND gate, which inputs the input signals I0 to I7 to one input and the output of the OR gate OR to the other input.

VDD supplies one level with a power supply. TP0 to TP7 are precharge transistors, and the gate is an inverter IN
The output of V8 is connected, and the power supply VDD is connected to the source.

D0 to D7 are data lines and are precharge transistors TP
The drains of 0 to TP7 are connected to each other.

INV0 to INV7 are inverters and data lines D0 to D7
Respectively as input.

TT0 to TT7 are transfer gates, the gates of which are connected to the clock speed switching signal HS, and the sources of which are connected to the inverters INV0 to INV7, respectively. The drains are connected to the data lines D0 to D7, respectively. The pair of the inverter INV0 and the transfer gate TT0 to the inverter INV7 and the transfer gate TT7 functions as a bias circuit that keeps the data lines D0 to D7 at a constant level when the clock speed switching signal HS is 1 level.

GND supplies 0 level at ground.

T07, T70, and T77 are decoding transistors, the sources of which are connected to the ground GND, and the gates of which T07 is connected to the output signal of the AND gate AND0 and T70 and T77 are connected to the output signal of the AND gate AND7. As for the drain, T70 is connected to the data line D0, and T07 and T77 are connected to the data line D7. The AND gates AND0 to AN, which are similar to those of the conventional decoding circuits of FIGS.
The decoding code is determined depending on whether or not the decoding transistor is arranged at the intersection of the output of D7 and the data lines D0 to D7.

BUF0 to BUF7 are buffers and receive data lines D0 to D7. The bias value of the bias circuit is set to a value slightly exceeding the threshold voltage of the buffers BUF0 to BUF7.

O0 to O7 are output signals and are buffers BUF0 to BUF7.
Is the signal at the output end of.

Next, the operation of the decoding circuit of FIG. 1 will be described with reference to the timing chart.

FIG. 2 is a timing chart showing the operation of the decoding circuit shown in FIG.

In FIG. 2, T1 to T8 indicate timing. HS indicates a clock speed switching signal, CLK indicates a clock signal, I0 indicates an input signal, D7S indicates a signal on the data line D7, and O7 indicates an output signal.

The clock speed switching signal HS is set to 0 level during the timings T1 to T4 and set to 1 level during the timings T5 to T8. Therefore, the clock signal CLK has timings T5 to T8.
Although not shown in the figure, the frequency is the same as that of the clock input signal φ, and is half the frequency of the clock input signal φ between the timings T1 and T4. This control is performed by the clock variable circuit DIV shown in FIG.

The input signal I0 is 1 at timing T1, T2, T5, T6.
The level becomes 0 at timing T3, T4, T7, T8.
It shall be a level.

Next, how the signal D7S of the data line D7 and the output signal O7 change at timings T1 to T8 will be sequentially examined.

At the timing T1, the clock signal CLK is at 0 level and the clock speed switching signal HS is also at 0 level, so that the output of the OR gate OR becomes 0 level and the output of the inverter INV8 becomes 1 level. Therefore, the precharge transistors TP0 to TP7 are opened and the data lines D0 to D0 are opened.
One level is supplied to D7. Also at this time AND gate A
ND0 to AND7 output 0 level, and since the decode transistors T07, T70, T77 are all closed, the data lines D0 to D7 are set to 1 level.

Now, the threshold voltage of the buffers BUF0 to BUF7 is an intermediate voltage between the 1 level and the 0 level, and when the voltage of the data line D7 becomes higher than this voltage, the output signal O7 of the buffer BUF7 becomes 1 level.

At timing T2, the clock signal CLK becomes 1 level, the precharge transistors TP0 to TP7 are closed, and the AND gate AND0 becomes 1 level because the input signal I0 is 1 level. As a result, the decode transistor T07 is opened and the 1 level of the data line D7 is discharged to 0 level. The output signal 07 of the buffer BUF7 also becomes 0 level when the data line D7 becomes lower than the threshold voltage.

Here, tALS represents the access time from the input signal I0 to the output signal O7 when the clock speed switching signal HS is at 0 level.

At the timing T3, the clock signal CLK becomes 0 level again, and the data lines D0 to D7 are precharged similarly to the timing T1.

At timing T4, since the input signal I0 is at 0 level, the AND gate AND0 remains at 0 level, the decode transistor T07 does not open, the precharge level of 1 of the data line D7 is maintained as it is, and the output signal O7 is at 1 level. Is.

At the timing T5, the clock speed switching signal HS changes to 1 level. Then, the OR gate OR becomes 1 level and the inverter INV8 becomes 0 level, and the precharge transistors TP0 to TP7 are closed. Then, the transfer gates TT0 to TT7 are opened and the data lines D0 to D7 have a voltage slightly exceeding the threshold voltage of the buffers BUF0 to BUF7.

Here, when the input signal I0 becomes 1 level, the AND gate A
The output of ND0 also becomes 1 level, the decoding transistor T07 is opened, and the data line D7 is buffered in the buffers BUF0 to BUF.
7 threshold voltage or less. Then, the output signal O7 becomes 0 level.

Here, tAHS indicates the access time from the input signal I0 to the output signal O7 when the clock speed switching signal HS is at 1 level.

After timing T5, the operation of the decoding circuit becomes independent of the clock signal CLK. That is, the output signals O0 to O7 are determined only by the input signals I0 to I7.

When the input signal I0 becomes 0 level at timing T7, AN
Since the D gate AND0 also becomes 0 level and the decode transistor T07 is closed, the data line D7 is buffered by the buffer BUF.
The threshold voltage of 0 to BUF7 is exceeded and the output signal O7 becomes 1 level.

[Embodiment 2] FIG. 5 is a decoding circuit diagram showing a second embodiment of the present invention.

In FIG. 5, a portion surrounded by a dotted line indicated by A shows a portion different from the decoding circuit of FIG. Other parts are first
Since it is exactly the same as the decoding circuit shown in the figure, its explanation is omitted.

OR1 in the difference point A is an OR gate and is a clock signal CL.
The inverted signal of K and the clock speed switching signal HS are input. NAND0 to NAND7 are NAND gates and receive the clock speed switching signal HS and the data lines D0 to D7. TT0 to TT7 are transfer gates, the output of the OR gate OR1 is connected to the gates, and the source is N
The outputs of the AND gates NAND0 to NAND7 are connected to each other, and the drains are connected to the data lines D0 to D7, respectively.

Next, the operation in the portion A which is different from the decoding circuit of FIG. 1 will be described.

NAND when the clock speed switching signal HS is 0 level
The gates NAND0 to NAND7 all output 1 level. Further, since the OR gate OR1 outputs an inverted signal of the clock signal CLK, the transfer gates TT0 to TT
7 is opened when the clock signal CLK is 0 level and NAN
It outputs 1 level which is the output of the D gates NAND0 to NAND7.

This operation is the same as the operation of the precharge transistors TP0 to TP7 of the decoding circuit of FIG.

Next, when the clock speed switching signal HS is 1 level, NAN
The D gates NAND0 to NAND7 are data lines D0 to D7.
The inverted signal of is output. Further, since the OR gate OR1 always outputs 1 level, the transfer gates TT0 to TT
7 remains open.

This operation is performed by the inverter INV0 of the decoding circuit shown in FIG.
˜INV7 and transfer gates TT0 to TT7 perform the same operation as the bias circuit.

As described above, the difference A in the decoding circuit of FIG. 5 from the decoding circuit of FIG. 1 is that the precharge transistors TP0 to TP7, the inverters INV0 to INV7 and the transfer gates TT0 to T of the decoding circuit of FIG.
Since the bias circuit constituted by T7 operates in the same manner, the entire fifth decoding circuit also operates in the same manner as the first decoding circuit.

〔The invention's effect〕

As described above, the present invention uses the clock speed switching signal HS.
Is 0 level, the precharge circuit is selected, and when the clock speed switching signal HS is 1 level, the bias circuit is selected, so that the clock signal CLK is low in speed as in timings T1 to T4. Decoding circuit,
Further, when the clock signal CLK is at high speed as at timings T5 to T8, there is an effect that a high speed and high power consumption decoding circuit can be selected to minimize the power speed product.

[Brief description of drawings]

FIG. 1 is a decoding circuit diagram of the first embodiment of the present invention, and FIG.
FIG. 4 is a timing diagram of the decoding circuit of FIG. 1, FIGS. 3 and 4 are conventional decoding circuit diagrams, and FIG. 5 is a second diagram of the present invention.
3 is a decoding circuit diagram of the embodiment of FIG. 1, FIG. 3, FIG. 4, FIG. 5, and FIG. 5, φ ... Clock input signal, HS ... Clock speed switching signal, CLK ... Clock signal, I0-I7 ... Input signal, O0-O7 ... Output signal, VDD ... Power supply, GND
...... Grounding, INV / INV0 to INV8 …… Inverter, AND0 to AND7 …… AND gate, TP0 to T
P7 ... Precharge transistor, TT0 to TT7 ...
... Transfer gate, T07 / T70 / T77 ...
Decode transistor, BUF0 to BUF7 ... Buffer, OR / OR1 ... OR gate, NAND0 to NAN
D7 ... NAND gate. In FIG. 2, T1 to T8 ... Timing, HS ... Clock speed switching signal, CLK ... Clock signal, I0 ... Input signal, D
7S ... data line D7 signal, O7 ... output signal, tA
LS ... Access time when the clock speed switching signal is 0 level, tAHS ... Access time when the clock speed switching signal is 1 level.

Claims (5)

[Claims] 1. An integrated circuit having a clock variable circuit and a decode circuit, wherein the decode circuit responds to a precharge signal when a data line and a control signal for controlling the clock variable circuit are at a first logic level. Data line control means for supplying a predetermined bias voltage to the data line regardless of the precharge signal when the data line is precharged and the control signal is at the second logic level. Variable speed decoding circuit. 2. A variable speed decoder according to claim 1.
In the data circuit, the data line control means is
Prechar connected between the line and the precharge potential point
Before the ditransistor and this precharge transistor
When the control signal is at the first logic level,
And a control signal is supplied to the second logic level.
The precharge transistor is turned off when
Precharge circuit having a gate circuit for applying an electric potential
And a bias voltage source for generating the predetermined bias voltage
And connected between the data line and the bias voltage
OFF state when the control signal is at the first logic level
Becomes the ON state at the second logic level.
And a bias circuit having an switch.
Variable speed decoding circuit. 3. The variable speed decoding circuit according to claim 2, wherein the gate circuit has a first input to which the precharge signal is supplied, a second input to which the control signal is supplied, and the precharge. An OR gate having an output connected to a gate of a transistor, the bias voltage source is an inverter having an input and an output connected, the switch is connected between the inverter and the data line, and the gate has the control signal. A variable-speed decoding circuit characterized by comprising a transistor for receiving. 4. The variable speed decoding circuit according to claim 1, wherein the data line control means includes a transistor whose one end is connected to the data line, and a gate of the transistor which receives the control signal. A first gate circuit connected to the data line and a first gate circuit that supplies the precharge signal when the logic level is 1 and a potential that makes the transistor conductive when the logic level is 1 Input, a second input for receiving the control signal, and an output connected to the other end of the transistor, and applies a precharge potential to the other end of the transistor when the control signal is at the first logic level. And a second gate circuit that performs an inversion operation on the first input at the second logic level. 5. The variable speed decoding circuit according to claim 4, wherein the first gate circuit is an OR gate, and the second gate circuit is a NAND gate. Decoding circuit.