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JPH06132439A - Plating method for ceramic package - Google Patents

Plating method for ceramic package

Info

Publication number
JPH06132439A
JPH06132439A JP28307392A JP28307392A JPH06132439A JP H06132439 A JPH06132439 A JP H06132439A JP 28307392 A JP28307392 A JP 28307392A JP 28307392 A JP28307392 A JP 28307392A JP H06132439 A JPH06132439 A JP H06132439A
Authority
JP
Japan
Prior art keywords
cavity
lead terminal
ceramic package
conductive plate
plate material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28307392A
Other languages
Japanese (ja)
Inventor
Toshiki Goto
利樹 後藤
Takaharu Kato
隆治 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Insulators Ltd
Original Assignee
NGK Insulators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Insulators Ltd filed Critical NGK Insulators Ltd
Priority to JP28307392A priority Critical patent/JPH06132439A/en
Publication of JPH06132439A publication Critical patent/JPH06132439A/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

PURPOSE:To obtain a product having a uniform plated thickness even in a pin grid array-type ceramic package provided with a chip-mounting cavity in the same direction as a lead terminal. CONSTITUTION:A bonding pad 3 which is exposed in a chip-mounting cavity 2 in a pin grid array-type ceramic package 11 provided with the cavity 2 in the same direction as a lead terminal 4 and the lead terminal 4 are electrolytically plated by using a conductive sheet material 12 as a common electrode in a state that the lead terminal 4 has been pressed to the tip. At this time, a window 13 whose size corresponds to the size of the cavity 2 is formed in the conductive sheet material 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、リード端子と同一方向
にチップ搭載用のキャビティを有するピングリッドアレ
イ型のセラミックパッケージのめっき方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of plating a pin grid array type ceramic package having a chip mounting cavity in the same direction as the lead terminals.

【0002】[0002]

【従来の技術】従来、ピングリッドアレイ型のセラミッ
クパッケージは、図3にその一例の構造を示すように、
セラミック基板21と、セラミック基板21の中央部に
形成された例えばIC、LSI等のチップ22を収容す
るキャビティ23と、セラミック基板21の上面に形成
される多数のボンディングパット24と、セラミック基
板21の下面に形成されたボンディングパット24と各
別に電気的に接続しているリード端子25とから形成さ
れている。
2. Description of the Related Art Conventionally, a pin grid array type ceramic package has a structure as shown in FIG.
The ceramic substrate 21, a cavity 23 formed in the central portion of the ceramic substrate 21 for accommodating a chip 22 such as an IC or LSI, a large number of bonding pads 24 formed on the upper surface of the ceramic substrate 21, and the ceramic substrate 21. The bonding pad 24 is formed on the lower surface and the lead terminals 25 are electrically connected to each other.

【0003】上述した構造のピングリッドアレイ型のセ
ラミックパッケージでは、導電性を良好にするとともに
酸化腐食を防止するため、ボンディングパット24のキ
ャビティ23に露出した部分およびリード端子25をニ
ッケル、金等によりめっきする必要があり、図3に示す
ようにボンディングパット24をパッケージ端面まで延
長するめっき用引き出し線26を設け、パッケージの側
面で共通電極27と接触させ、この共通電極27より給
電して電解めっき処理を実施していた。
In the pin grid array type ceramic package having the above-mentioned structure, in order to improve conductivity and prevent oxidative corrosion, the exposed portion of the bonding pad 24 in the cavity 23 and the lead terminal 25 are made of nickel, gold or the like. It is necessary to plate, and as shown in FIG. 3, a lead wire 26 for plating that extends the bonding pad 24 to the end surface of the package is provided, the side surface of the package is brought into contact with the common electrode 27, and power is supplied from the common electrode 27 for electrolytic plating. Processing was being carried out.

【0004】上述した従来のめっき方法では、めっき処
理後には不要となるめっき用引き出し線26がパッケー
ジの内部に残存するため、パッケージの信号伝達の高速
化が図れない等の種々の問題があった。この問題を解決
するため、本出願人は特願平4−64763号におい
て、めっき用引き出し線26を使用せず電解めっき処理
が可能となるよう、導電性の板材をパッケージのリード
端子先端に押し当てて、この導電性板材を共通電極とし
て電解めっきを施す方法を提供している。
In the above-described conventional plating method, the lead wire 26 for plating, which is unnecessary after the plating process, remains inside the package, and thus there are various problems such as the failure of speeding up the signal transmission of the package. . In order to solve this problem, the present applicant has proposed in Japanese Patent Application No. 4-64763 that a conductive plate material is pushed onto the tip of the lead terminal of the package so that electrolytic plating can be performed without using the lead wire 26 for plating. By applying this conductive plate material as a common electrode, electrolytic plating is provided.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た特願平4−64763号に開示しためっき方法であっ
ても、図4にその一例を示すようなリード端子25と同
一方向にチップ搭載用のキャビティ23を有する特殊形
状のピングリッドアレイ型のセラミックパッケージにこ
の方法を応用しようとすると、パッケージと導電性板材
28との隙間が小さく、導電性板材28が電解めっき時
にマスクとして作用するため、キャビティ23内のボン
ディングパット24上のメタライズ層及びリード端子2
5上にめっきが均一に付着しない問題があった。
However, even in the plating method disclosed in Japanese Patent Application No. 4-64763 mentioned above, the chip mounting method is carried out in the same direction as the lead terminal 25 as shown in FIG. If this method is applied to a specially shaped pin grid array type ceramic package having a cavity 23, the gap between the package and the conductive plate material 28 is small, and the conductive plate material 28 acts as a mask during electrolytic plating. 23 and the metallization layer on the bonding pad 24 and the lead terminal 2
There was a problem that the plating did not adhere uniformly on the No. 5 coating.

【0006】本発明の目的は上述した課題を解消して、
リード端子と同一方向にチップ搭載用キャビティを有す
るピングリッドアレイ型のセラミックパッケージでも均
一なめっき厚の製品を得ることがセラミックパッケージ
のめっき方法を提供しようとするものである。
The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a method for plating a ceramic package in which a pin grid array type ceramic package having a chip mounting cavity in the same direction as the lead terminals can obtain a product having a uniform plating thickness.

【0007】[0007]

【課題を解決するための手段】本発明のセラミックパッ
ケージのめっき方法は、リード端子と同一方向にチップ
搭載用のキャビティを有するピングリッドアレイ型のセ
ラミックパッケージの前記キャビティに露出したボンデ
ィングパットおよびリード端子を、導電性板材をリード
端子先端に押し当てた状態で導電性板材を共通電極とし
て電解めっきするにあたり、前記導電性板材に前記キャ
ビティの大きさに相当する大きさの窓部を設けたことを
特徴とするものである。
According to the method of plating a ceramic package of the present invention, a bonding pad and a lead terminal exposed in the cavity of a pin grid array type ceramic package having a cavity for mounting a chip in the same direction as the lead terminal. In electroplating the conductive plate material as a common electrode in a state where the conductive plate material is pressed against the tip of the lead terminal, the conductive plate material is provided with a window portion having a size corresponding to the size of the cavity. It is a feature.

【0008】[0008]

【作用】上述した構成において、導電性板材のキャビテ
ィに対応する部分に窓部を設けたため、導電性板材とパ
ッケージ特にキャビティとの間に電解めっき液が流れ込
み易くなる。また、電解めっき処理を行う電気めっき槽
をなす電極とめっきが付着するキャビティのボンディン
グパットとが対向するようになるため、電極とボンディ
ングパットとの間の電流分布を均等にすることができ
る。その結果、リード端子と同一方向にチップ搭載用キ
ャビティを有するピングリッドアレイのセラミックパッ
ケージでも、均一な厚さのめっきを施した製品を得るこ
とができる。
In the above structure, the window portion is provided at the portion corresponding to the cavity of the conductive plate material, so that the electrolytic plating solution easily flows between the conductive plate material and the package, especially the cavity. Further, since the electrode forming the electroplating tank for performing the electroplating process and the bonding pad of the cavity to which the plating is attached face each other, the current distribution between the electrode and the bonding pad can be made uniform. As a result, even in the case of a pin grid array ceramic package having a chip mounting cavity in the same direction as the lead terminals, a product plated with a uniform thickness can be obtained.

【0009】[0009]

【実施例】図1は本発明のセラミックパッケージのめっ
き方法を実施する際の状態を示す図であり、図1(a)
は側面図を、図1(b)は正面図をそれぞれ示してい
る。図1(a)、(b)に示す例において、セラミック
パッケージ11は、従来例と同様に、セラミック基板1
と、このセラミック基板1の中央部に設けた図示しない
ICチップ等を搭載するためのキャビティ2と、キャビ
ティ2に一部が露出するボンディングパット3と、ボン
ディングパット3と各別に電気的に接続している、セラ
ミック基板1のキャビティ2と同一面に形成したリード
端子4とから構成している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a state in which a method for plating a ceramic package according to the present invention is carried out, and FIG.
Shows a side view and FIG. 1 (b) shows a front view. In the example shown in FIGS. 1A and 1B, the ceramic package 11 has a ceramic substrate 1 similar to the conventional example.
A cavity 2 for mounting an IC chip (not shown) provided in the central portion of the ceramic substrate 1, a bonding pad 3 partially exposed in the cavity 2, and a bonding pad 3 electrically connected to each other. , And the lead terminal 4 formed on the same surface as the cavity 2 of the ceramic substrate 1.

【0010】そして、このセラミックパッケージ11の
リード端子4の先端に導電性板材12を押し当てて、こ
の導電性板材12を共通電極として、ボンディングパッ
ト3およびリード端子4に給電している。本発明の特徴
は、この導電性板材12の中央部分のキャビティ2に対
応する位置に、キャビティ2の大きさに相当する大きさ
の窓部13を設けた点である。窓部3の大きさはキャビ
ティ2と同等の大きさのため、リード端子4と導電性板
材12との接触を妨げることはない。なお、導電性板材
12としては、例えば1Ω/□以下の抵抗を有する導電
ゴム等を使用すると好ましい。
Then, the conductive plate material 12 is pressed against the tip of the lead terminal 4 of the ceramic package 11, and the bonding pad 3 and the lead terminal 4 are fed with the conductive plate material 12 as a common electrode. A feature of the present invention is that a window portion 13 having a size corresponding to the size of the cavity 2 is provided at a position corresponding to the cavity 2 in the central portion of the conductive plate material 12. Since the size of the window 3 is the same as the size of the cavity 2, the contact between the lead terminal 4 and the conductive plate 12 is not hindered. As the conductive plate member 12, it is preferable to use, for example, a conductive rubber having a resistance of 1 Ω / □ or less.

【0011】図2は図1に示す構造の導電性板材12を
設けたセラミックパッケージを実際に電解めっき用の治
具15に装着した状態で示す図である。図2に示すよう
に、丈夫なフック状の治具15の両面にそれぞれ4個ず
つセラミックパッケージ11を導電性板材12とともに
横に並べた列を複数列装着している。送電性板材12
は、それぞれがセラミックパッケージ12の外側になる
ように配置され、装着した治具15を介して電気的に給
電されるように構成されている。
FIG. 2 is a view showing a state where the ceramic package provided with the conductive plate material 12 having the structure shown in FIG. 1 is actually mounted on the jig 15 for electrolytic plating. As shown in FIG. 2, four rows of ceramic packages 11 are horizontally mounted together with the conductive plate material 12 on both sides of a durable hook-shaped jig 15. Power transmitting plate material 12
Are arranged so as to be outside the ceramic package 12, and are configured to be electrically fed through the attached jig 15.

【0012】図2に示す状態で、治具15のフック状の
部分を電解めっき装置の一方の電極に電気的に接続して
吊るし、そのまま電解めっき装置の他方の電極を兼ねる
電気めっき槽中の電解めっき液中に浸漬して、この状態
で電気めっき槽および導電性板材12に給電すれば、キ
ャビティ12に露出するボンディングパット3とリード
端子4に電解めっきを施すことが可能となる。
In the state shown in FIG. 2, the hook-shaped portion of the jig 15 is electrically connected to one of the electrodes of the electroplating apparatus and is hung, and the electroplating tank also functions as the other electrode of the electroplating apparatus. By immersing in the electrolytic plating solution and supplying electric power to the electroplating tank and the conductive plate material 12 in this state, it is possible to perform electrolytic plating on the bonding pad 3 and the lead terminal 4 exposed in the cavity 12.

【0013】本発明は上述した実施例にのみ限定される
ものではなく、幾多の変形、変更が可能である。例え
ば、上述した実施例では、窓部13の形状が対応するキ
ャビティ2の形状と同一の四角形となっているが、この
形状はこれに限定されるものではなく、円形や楕円形等
の他の形状でもキャビティの大きさに相当する大きさの
窓が開いていれば、四角形の場合と同様に本発明の効果
を達成できることは明かである。また、図2に実際の電
解めっきの状態を示したが、電解めっきの方法は例示し
た方法に限定されるものでないことも明らかである。
The present invention is not limited to the above-mentioned embodiments, but various modifications and changes can be made. For example, in the above-described embodiment, the shape of the window portion 13 is the same quadrangle as the shape of the corresponding cavity 2, but this shape is not limited to this, and other shapes such as a circle and an ellipse. It is obvious that the effect of the present invention can be achieved as in the case of a quadrangle if the window has an opening of a size corresponding to the size of the cavity. Further, although FIG. 2 shows the actual state of electrolytic plating, it is also clear that the electrolytic plating method is not limited to the exemplified method.

【0014】[0014]

【発明の効果】以上の説明から明らかなように、本発明
によれば、導電性板材のキャビティに対応する部分に窓
部を設けたため、導電性板材とパッケージ特にキャビテ
ィとの間に電解めっき液が流れ込み易くなるとともに、
電解めっき処理を行う電気めっき槽をなす電極とめっき
が付着するキャビティのボンディングパットとが対向す
るようになるため、電極とボンディングパットとの間の
電流分布を均等にすることができ、リード端子と同一方
向にチップ搭載用キャビティを有するピングリッドアレ
イのセラミックパッケージでも、均一な厚さのめっきを
施した製品を得ることができる。
As is apparent from the above description, according to the present invention, since the window portion is provided at the portion corresponding to the cavity of the conductive plate material, the electrolytic plating solution is provided between the conductive plate material and the package, especially the cavity. Becomes easy to flow in,
Since the electrode forming the electroplating tank for the electroplating process and the bonding pad of the cavity to which the plating is attached face each other, the current distribution between the electrode and the bonding pad can be made uniform, and the lead terminal and Even with a pin grid array ceramic package having chip mounting cavities in the same direction, a product plated with a uniform thickness can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のセラミックパッケージのめっき方法を
実施する際の状態を示す図である。
FIG. 1 is a diagram showing a state when a method for plating a ceramic package of the present invention is carried out.

【図2】図1に示す構造の導電性板材を設けたセラミッ
クパッケージを実際に電解めっき用の治具に装着した状
態で示す図である。
FIG. 2 is a diagram showing a ceramic package provided with a conductive plate material having the structure shown in FIG. 1 actually mounted on a jig for electrolytic plating.

【図3】従来のピングリッドアレイ型のセラミックパッ
ケージの一例の構成を示す図である。
FIG. 3 is a diagram showing a configuration of an example of a conventional pin grid array type ceramic package.

【図4】従来のセラミックパッケージのめっき方法を実
施する際の状態を示す図である。
FIG. 4 is a diagram showing a state when a conventional ceramic package plating method is carried out.

【符号の説明】[Explanation of symbols]

1 セラミック基板 2 キャビティ 3 ボンディングパット 4 リード端子 11 セラミックパッケージ 12 導電性板材 13 窓部 1 Ceramic Substrate 2 Cavity 3 Bonding Pad 4 Lead Terminal 11 Ceramic Package 12 Conductive Plate 13 Window

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 23/12

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 リード端子と同一方向にチップ搭載用の
キャビティを有するピングリッドアレイ型のセラミック
パッケージの前記キャビティに露出したボンディングパ
ットおよびリード端子を、導電性板材をリード端子先端
に押し当てた状態で導電性板材を共通電極として電解め
っきするにあたり、前記導電性板材に前記キャビティの
大きさに相当する大きさの窓部を設けたことを特徴とす
るセラミックパッケージのめっき方法。
1. A state in which a bonding pad and a lead terminal exposed in the cavity of a pin grid array type ceramic package having a cavity for mounting a chip in the same direction as that of the lead terminal are pressed against a tip of the lead terminal with a conductive plate material. In the electroplating using the conductive plate material as a common electrode, the conductive plate material is provided with a window portion having a size corresponding to the size of the cavity.
JP28307392A 1992-10-21 1992-10-21 Plating method for ceramic package Pending JPH06132439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28307392A JPH06132439A (en) 1992-10-21 1992-10-21 Plating method for ceramic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28307392A JPH06132439A (en) 1992-10-21 1992-10-21 Plating method for ceramic package

Publications (1)

Publication Number Publication Date
JPH06132439A true JPH06132439A (en) 1994-05-13

Family

ID=17660860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28307392A Pending JPH06132439A (en) 1992-10-21 1992-10-21 Plating method for ceramic package

Country Status (1)

Country Link
JP (1) JPH06132439A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989591B1 (en) * 2000-07-18 2006-01-24 Atmel Grenoble S.A. Method for making an integrated circuit of the surface-mount type and resulting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989591B1 (en) * 2000-07-18 2006-01-24 Atmel Grenoble S.A. Method for making an integrated circuit of the surface-mount type and resulting circuit

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