JPH06132404A - Multi-layer wiring method for semiconductors - Google Patents

Abstract

(57) [Abstract] [Purpose] A method of manufacturing a semiconductor device including formation of an electrical connection between a lower wiring layer and an upper wiring layer, and removal of a natural oxide film formed on the surface of the lower wiring layer at the bottom of a connection hole. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which is capable of preventing the secondary deposition of insulating properties and improving the electrical connection between the upper and lower wirings. A process of forming a conductive etching mask on an interlayer insulating film formed on a lower wiring layer, and dry etching using the etching mask to penetrate the interlayer insulating film to expose the lower wiring layer The method is characterized by including a step of forming an opening and a step of forming a conductive coating covering the exposed lower wiring layer while leaving the etching mask, following the step of forming the opening.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including forming an electrical connection between a lower wiring layer and an upper wiring layer.

In recent years, with the increase in scale of integrated circuits, the development of three-dimensional wiring technology for increasing the degree of integration, that is, semiconductor multilayer wiring technology has become more and more important. High integration requires not only circuit elements but also miniaturization of wiring dimensions. Therefore, low resistance wiring technology with high reproducibility and reliability is required.

[0003]

2. Description of the Prior Art Multilayer wiring materials for integrated circuits include highly reliable and stable Al alloys, polycrystalline silicon, refractory metals,
A refractory metal silicide or the like is used, and photolithography, etching, coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), heat treatment, or the like is used as a wiring element technology.

FIG. 5 shows a typical multilayer wiring process in which the first and second metal wiring layers are made of Al alloy. As shown in FIG. 5A, the S having the integrated circuit element formed thereon is formed.
An SiO ₂ layer 2 for element isolation and substrate-wiring isolation is formed on an i-substrate 1 and Al is used as a lower wiring layer on the SiO ₂ layer 2.
The alloy wiring layer 3 is formed. When the substrate is taken out into the atmosphere, a natural oxide film 4 is formed on the Al alloy layer 3.

As shown in FIG. 5B, PS is formed as an interlayer insulating film 50 on the Al alloy layer 3 having the natural oxide film 4.
A sandwich structure of the G layer 5, the SOG layer 6 and the PSG layer 7 is formed. The total thickness is preferably about the same as or smaller than the opening diameter of the connection hole to be formed. The PSG layers 5 and 7 are deposited by low pressure CVD or the like, and the SOG layer 6 is spin-coated. The spin-coated SOG layer 6 flattens the unevenness of the underlying surface.

SOG (spin-on-glass) is excellent in flattening, but has a high hygroscopic property, so that SOG is not absorbed during vacuum processing in the subsequent process.
Degassing of water or the like from G may occur and adversely affect the wiring. Therefore, both surfaces of the SOG layer 6 are covered with phosphorus glass (PSG) layers 5 and 7 having excellent waterproofness to protect the upper and lower wiring layers.

A photoresist film 10 is applied on the interlayer insulating film 50. The photoresist film 10 is subjected to patterning for connection holes by the usual photolithography technique. Using this photoresist film mask, reactive ion etching (RIE) is performed to open the connection hole 11 in the interlayer insulating film 50.

Next, as shown in FIG. 5C, the photoresist film 10 is ashed and removed by oxygen plasma, the substrate to be processed is transferred into the sputtering apparatus, and the native oxide film 4 of Al alloy is first formed. Remove.

In the pretreatment chamber of the PVD apparatus, a natural oxide film (Al ₂
Etch O _x ) 4. This is because if the upper layer wiring is formed on the natural oxide film 4 without removing it, the connection will be defective.

As shown in FIG. 5 (D), subsequently, the substrate to be processed is moved to the sputtering chamber in the same apparatus, and the Al alloy of the upper layer metal wiring material is sputtered to form the Al alloy layer 13.
Is formed in contact with the Al alloy layer 3 which is the lower metal wiring layer.

When the substrate is taken out into the atmosphere, the Al oxide natural oxide film 14 is formed on the surface of the Al alloy layer 13 of the upper metal wiring.
Is formed. Finally, as shown in FIG. 5E, the Al alloy layer 13 of the upper metal wiring is patterned into a predetermined shape. In this way, the two-layer wiring is completed. The natural oxide film 1 is also formed on the side surface of the patterned Al alloy layer 13.
4'is formed.

Since the wiring width becomes finer as the scale of the integrated circuit becomes larger, the diameter of the connection hole 11 also becomes finer. It is difficult to sufficiently reduce the contact resistance unless the natural oxide film of the lower metal wiring layer at the bottom of the contact hole is removed.

However, it is not appropriate to remove the natural oxide film by wet etching. In wet etching,
The natural oxide film 4 of the Al alloy layer 3 cannot be completely removed.

Further, there is a risk that the interlayer insulating film 50 is side-etched and the opening diameter is unintentionally increased. In that sense, dry etching such as Ar plasma etching as described with reference to FIG. 5C is preferable.

A technique has also been proposed in which the surface of the lower wiring layer is receded by overetching when the connection hole is opened (for example, Japanese Patent Laid-Open Nos. 61-289648 and 4-1).
20757). In these cases, after the lower layer wiring is over-etched, the substrate is once taken out into the outside air, and then the upper layer wiring is buried and deposited. Therefore, it is difficult to sufficiently reduce the contact resistance between the upper and lower wiring layers.

[0016]

Although the Ar plasma etching in the step of FIG. 5C is effective for removing the natural oxide film at the bottom of the fine connection hole, it is poor in selectivity and therefore exposed. The surface of the existing interlayer insulating film 50 is also etched. Therefore, the natural oxide film 4 at the bottom of the connection hole 11
Is etched off, and the interlayer insulating film 50 is etched. The PSG layers 5 and 7 of the interlayer insulating film 50 and the SOG layer 6
Is formed of a low melting point glass which is an insulator.

When the glass component secondarily etched reaches the surface of the activated Al alloy layer 3, a non-uniform deposit 29 is formed. This deposit 29 is of course an insulating composition. When the Al alloy layer 13 of the upper metal wiring is deposited on this, the contact resistance between the upper and lower wiring layers increases.

When the upper wiring layer is sputtered,
The substrate is typically heated to improve step coverage. When heated in a vacuum, the interlayer insulating film 50, especially S
Degassing or the like occurs in the OG layer 6 and adheres to the surface of the lower wiring layer to change its surface state or generate a deposit. When an upper wiring layer is formed on this, contact resistance increases.

The object of the present invention is to remove the natural oxide film formed on the surface of the lower wiring layer at the bottom of the connection hole, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing the secondary deposition of insulating properties and improving the electrical connection between upper and lower wirings.

[0020]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a conductive etching mask on an interlayer insulating film formed on a lower wiring layer, and a dry process using the etching mask. A step of forming an opening that exposes the lower wiring layer through the interlayer insulating film by etching, and a conductive coating that covers the exposed lower wiring layer while leaving the etching mask, following the step of forming the opening And a process.

[0021]

A conductive etching mask is formed on the interlayer insulating film, and the interlayer insulating film can be dry-etched by using this conductive etching mask.

Even if dry etching is used when the natural oxide film of the lower wiring layer below the interlayer insulating film is removed after forming the connection hole in the interlayer insulating film, the secondary etching is conductive etching. Mostly for masks, it is conductive even if deposition occurs. Therefore, it is possible to prevent the conductive surface area of the lower wiring layer from decreasing.

At this time, the dry etching product can be deposited also on the side wall of the connection hole to prevent the outgassing from the interlayer insulating film 50, especially from the SOG 6. Further, by retracting the surface of the connection hole portion of the lower wiring layer, the surface area of the connection hole portion is increased,
This makes it possible to further improve the degassing prevention effect.

By forming a conductive coating for the upper wiring layer on the connection hole, the contact resistance between the upper and lower wiring layers can be kept low. Hereinafter, the present invention will be described in more detail based on examples.

[0025]

1 shows the main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1A, an integrated circuit element is formed, element isolation and wiring-S are performed.
An Al alloy layer 3 is formed as a lower metal wiring on the Si substrate 1 on which the SiO ₂ layer 2 for separating the i substrates is formed.

When the substrate is taken out into the atmosphere, the Al alloy layer 3
A natural oxide film 4 is formed on the surface of the. On the Al alloy layer 3 provided with the natural oxide film 4, the PSG layer 5, the SOG layer 6,
An interlayer insulating film 50 made of the PSG layer 7 is formed.

The interlayer insulating film 50 is formed by depositing the PSG layer 6 having a thickness of 100 nm by the low pressure CVD method, then applying the SOG layer 7 having a thickness of 200 nm thereon by the spin coating method, and again by the low pressure CVD method. Then, a PSG layer 8 having a thickness of 200 nm is deposited to form a triple structure.

An Al alloy layer 8 having a thickness of about 100 nm is formed as a metal mask material on the interlayer insulating film 50 by sputtering. When the substrate is taken out into the air, the Al alloy layer 8
A natural oxide film 9 is formed on the surface of the. A photoresist film 10 is applied on the Al alloy layer 8 having the natural oxide film 9.

As shown in FIG. 1B, a contact hole pattern 11 for connecting upper and lower wiring layers is formed in the photoresist film 10 by using photolithography. Using the photoresist pattern as a mask, the natural oxide film 9 and the Al alloy layer 8 are selectively etched by reactive ion etching (RIE) to form a connection hole 11.

That is, the sample is introduced into the dry etching apparatus, and the Al alloy layer 8 having a thickness of 100 nm and the natural oxide film 9 thereon are etched by RIE using a mixed gas of BCl ₃ and Cl ₂ . At this time, the PSG layer 7 acts as an etching stopper.

As shown in FIG. 1C, the interlayer insulating film 50 is formed.
Before the connection hole is opened, the photoresist film 10 is first ashed and removed in oxygen plasma. Next, the atmosphere is changed, and RIE is performed with a mixed gas of CHF ₃ and CF ₄ of about 1: 1.
Then, the interlayer insulating film 50 is perforated by using the Al alloy layer 8 and the natural oxide film 9 as a mask.

Etching can be stopped by the natural oxide film 4 on the surface of the Al alloy layer 3 of the lower wiring layer, that is, Al ₂ O _x . In this way, the connection hole 11 is formed in the interlayer insulating film 50.

Next, as shown in FIG. 1D, Ar sputter etching is performed without taking out the substrate into the atmosphere. First, the natural oxide films 4 and 9 on the surfaces of the Al alloy layers 3 and 8 are etched and disappeared by Ar sputtering. Subsequently, the Al alloy layers 3 and 8 are sputter-etched to
The 1-alloy layer 3 is etched to a depth of about 200 nm.
The Al alloy film 8 of the metal mask is also sputter etched.

A part of the Al alloy that has jumped out of the sputter-etched Al alloy layers 3 and 8 is reattached to the side wall surface of the connection hole 11 to form the Al alloy coating film 12. The exposed surface of the interlayer insulating film 50 including the SOG layer 6 is formed by the Al alloy coating 1
Covered by 2.

As shown in FIG. 1 (E), the substrate is then heated to about 500 ° C. without being taken out into the air, and the Al alloy layer 13 is sputtered to fill the connection hole 11.
The upper metal wiring 13 is formed by depositing to a thickness of about 1 μm. Even if the substrate is heated, the surface of the interlayer insulating film 50 including the SOG layer 6 is covered with the Al alloy film 12, so that degassing and the like are controlled.

When the substrate is taken out into the atmosphere, the Al alloy layer 1
A natural oxide film 14 is formed on the surface of the metal. Although not shown in the figure after this, if the second layer metal wiring 13 is patterned, the upper layer wiring is completed. Patterned Al
A natural oxide film is also formed on the surface of the alloy layer 13.

In this embodiment, the Al alloy is used as the metal mask material, but Cu alloy or Mg alloy may be used instead. The SOG layer 6 may be made of an organic silicon type, a polyimide type, or any other known composition.

Since the steps from FIG. 1C to the formation of the Al alloy layer 13 can be performed without breaking the vacuum, formation of a new natural oxide film can be prevented. A non-oxidizing atmosphere may be used instead of the vacuum.

FIG. 2 shows the main steps of a semiconductor device manufacturing method according to the second embodiment of the present invention. In this embodiment, as in the previous embodiment, an Al alloy is used as the material for the upper and lower wiring layers and the material for the metal mask. After forming the contact hole, the native oxide film is removed by RIE instead of Ar sputtering.

FIG. 2A shows a SiO ₂ layer 2, a lower Al alloy layer 3, an interlayer insulating film 50, and an upper Al layer on a Si substrate 1.
A step of forming the alloy layer 8, forming a photoresist mask 10 on the alloy layer 8, and selectively etching the upper Al alloy layer 8 will be described. This step is the same as the embodiment shown in FIG.

FIG. 2B shows a step of ashing the photoresist mask 10 and a selective etching process of the interlayer insulating film 50 using the natural oxide film 9 and the Al alloy layer 8 as a mask. This step is also similar to that of the embodiment shown in FIG.

Next, as shown in FIG. 2C, the natural oxide film 4 on the Al alloy layer 3 of the lower wiring, that is, the surface of the Al alloy oxide film and the Al alloy layer 3 thereunder in the same vacuum. R
Dry etching is performed by IE. This process uses BCl
RIE is performed in a mixed gas of ₃ and Cl ₂ to etch the Al alloy layer 3 to a depth of about 100 nm, and the process is completed.

Since this step has stronger chemical reactivity than Ar sputter etching, the etching rate is high.
Further, the Al alloy layer 8 of the mask and the natural oxide film 9 thereon are etched as well as the Al alloy layer 3 and the natural oxide film 4 thereon. Further, since the etched Al component has a shape of Al chloride, the vapor pressure is high, and therefore, unlike the case of the previous embodiment, the side surface of the interlayer insulating film 50 is not covered.

On the surfaces of the Al alloy layers 3 and 8 etched with a gas containing Cl, Al chloride (AlCl _x )
Layer 15 is formed. As shown in FIG. 2 (D), the substrate was exposed to 120 Torr in a Cl ₂ gas atmosphere of 10 Torr in the same apparatus.
The Al chloride layer 15 is removed by heating to ° C. Al chloride slightly left on the outermost surface is removed by heating to 200 ° C. while irradiating with ultraviolet rays in an atmosphere of hydrogen. Instead of ultraviolet rays, heating at about 500 ° C., light hydrogen plasma, light Ar sputtering, etc. may be used. You may perform cleaning combining these.

As shown in FIG. 2E, an Al alloy is first sputtered in the same vacuum at room temperature to a thickness of about 60 nm.
The room temperature deposited Al alloy film 13-a is formed. Since this step is performed at room temperature, the exposed side surface of the interlayer insulating film 50 can be covered while controlling degassing from the SOG layer 6.

Subsequently, the substrate is heated to 500 ° C. to sputter an Al alloy to form a heat-deposited Al alloy film 13-b having a thickness of 1 μm and good step coverage in a good migration state. These Al alloy layers 13-
a and 13-b form the upper wiring layer.

After that, when the substrate is taken out into the atmosphere, a natural oxide film 14 is formed on the surface of the upper wiring layer. Next, patterning is performed on the upper wiring layer. In FIG. 3, the lower wiring layer is made of tungsten polycide (WSi ₂ / polycrystalline S).
i), an example in which the upper wiring layer and the metal mask material are tungsten is shown. As shown in FIG.
An SiO ₂ layer 2 is formed on a Si substrate 1, and a polycrystalline Si layer 16 and a WSi ₂ layer 17 which are lower wiring layers are formed on the SiO ₂ layer 2. When the substrate is taken out into the atmosphere, a natural oxide film 18 is formed on the surface of the WSi ₂ layer 17.

The polycrystalline Si layer 16 is formed by the CVD method.
For example, it is formed to have a thickness of 150 nm. The WSi ₂ layer 17 is formed by the CVD method to have a thickness of 250 nm, for example. After these layers are deposited, they are patterned into the desired shape.

As shown in FIG. 3B, the natural oxide film 18 is formed.
With WSi₂A layer having a thickness of 60 is formed on the layer 17 by the low pressure CVD method.
Deposit a 0 nm PSG layer 5. Polycrystalline Si layer 16, W
Si ₂Since the layer 17 has high heat resistance, the substrate is heated and PS
The surface is flattened by the reflow of the G layer 5.

Next, a W layer 19 which is a metal mask material is formed on the PSG layer 5 to have a thickness of 200 nm by sputtering. When the substrate is taken out into the atmosphere, the WO _x layer 20 is formed on the surface. A photoresist film 10 is applied on the WO _x layer 20.

As shown in FIG. 3C, the photoresist film 10 is patterned using photolithography, and then the pattern of the contact hole 11 is transferred to the WO _x layer 20 and the W layer 19 by dry etching.

As shown in FIG. 3D, next, the photoresist film 10 is ashed and removed in oxygen plasma, the substrate is introduced into a dry etching apparatus, and the WO _x layer 20 and the W layer 1 are introduced.
9 as a mask, PSG layers 5 and W which are interlayer insulating films
The native oxide film 18 of the Si ₂ layer 17 is selectively RIEed in a mixed gas of CHF ₃ and CF ₄ . In this way WSi
_The connection hole 11 exposing the _second layer 17 is formed. At this time, the WO _x layer 20 on the surface of the W layer 19 is also removed.

As shown in FIG. 3 (E), the substrate is transferred without breaking the vacuum and heated to about 300.degree.
A W layer 21 of 00 nm is deposited on the entire surface by a CVD method to fill the connection hole 11.

When the substrate is taken out into the atmosphere, a WO _x layer 22 of a natural oxide film is formed on the surface of the W layer 21. By patterning the W layer 21 using photolithography, the upper layer wiring is formed.

Upper wiring layer and mask used in this embodiment
Material W and its natural oxide film WO _xIs the natural acid of Al
Film AlO_XCompared with
Have. Si or WSi as the lower wiring layer₂High melting point gold
If a metal silicide or refractory metal is used, PSG, etc.
Flattening by reflow is possible, without using SOG
May be.

FIG. 4 shows steps of a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. In this embodiment, similar to the first and second embodiments, Al alloy is used for the upper and lower wiring layers and the metal mask material. However, the process is simplified as compared with the first embodiment.

As shown in FIG. 4A, the SiO ₂ layer 2, the Al alloy layer 3, the natural oxide film 4, the PSG layer 5, the SOG layer 6, the PSG layer 7, the Al alloy film 8 are formed on the Si substrate 1. The natural oxide film 9 and the photoresist film 10 in this order are shown in FIG.
It is formed in the same manner as the step of.

As shown in FIG. 4B, a photoresist film
10 is patterned using photolithography, and the substrate
Is introduced into the dry etching apparatus. First BCl₃When
Cl ₂Al alloy layer 8 by RIE with mixed gas of
By selectively etching the natural oxide film 9 and the Al alloy film 8 of
To form a metal mask.

Then, CHF ₃ and C were added to the gas in the same apparatus.
By switching to the mixed gas of F ₄ and performing RIE, P
The SG layer 7, the SOG layer 6 and the PSG layer 5 are continuously selectively etched to form the connection hole 11.

As shown in FIG. 4C, the substrate is once taken out into the atmosphere and the photoresist film 10 is stripped with a resist stripping solution. A natural oxide film 9a is formed on the side surface of the Al alloy layer 8 in the atmosphere. Next, the substrate is introduced into the sputtering device.

As shown in FIG. 4D, Ar sputtering is performed in the sputtering apparatus to etch the native oxide film 4 at the bottom of the contact hole 11 and the Al alloy layer 3 thereunder to a depth of 200 nm. In this process, the natural oxide film 9 and Al alloy layer 8 functioning as a mask are also sputtered. A
The Al alloy coating 12 is redeposited on the side wall surface of the connection hole 11 by sputtering the 1-alloy layers 3 and 8 as in the first embodiment.

As shown in FIG. 4E, the Al alloy layer 13 is successively deposited by sputtering in the same vacuum. That is, the Al alloy layer 13 is deposited by sputtering to a thickness of about 1 μm on a substrate heated to about 500 ° C.

Once the substrate is taken out into the atmosphere, a natural oxide film 14 is formed on the surface of the Al alloy layer 13. Further, by patterning the Al alloy layer 13, the upper wiring is completed.

The contact resistance between the upper layer wiring and the lower layer wiring obtained in this example was evaluated as a function of the diameter of the cylindrical connection hole opening 11 and compared with the case of the conventional example shown in FIG. As shown in FIG. Wiring metal in upper and lower layers contains 1% Cu A
1 alloy. Conventional contact resistances were obtained from published literature.

In the submicron diameter of the contact hole, the contact resistance of Example 4 is lower than that of the conventional example as the diameter decreases. In the case of a connection hole having a diameter of 0.5 μm, the contact resistance of the conventional example is about 3.5Ω, whereas the contact resistance of the fourth example is about 1.7Ω.

Although the case of the two-layer wiring has been described as an example, wiring of three or more layers can be connected in the same process. The interlayer insulating film and the wiring layer may be formed of other materials. The shape of the connection hole is arbitrary.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0068]

As described above, according to the present invention,
Even if the diameter of the connection hole is small, the contact resistance between the upper and lower wiring layers can be kept low.

Further, the contact resistance between the upper and lower wiring layers is low,
A highly reliable semiconductor device can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part of a multilayer wiring process of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a main part of a multilayer wiring process in a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a main part of a multilayer wiring process in a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a main part of a multilayer wiring process in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a main part of a multilayer wiring process of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 6 is a graph showing a comparison of contact resistance between upper and lower wiring layers according to an example and a conventional example.

[Explanation of symbols]

1 Si Substrate 2 SiO ₂ Layer 3 Al Alloy Layer 4 Natural Oxide Film 5 PSG Layer 6 SOG Layer 7 PSG Layer 8 Al Alloy Layer 9 Natural Oxide Film 10 Photoresist Film 11 Connection Hole 12 (Reattached) Al Alloy Film 13 Al Alloy Layer 14 Natural oxide film 13-a (deposition at room temperature) Al alloy film 13-b (deposition by heating) Al alloy film 15 Al chloride layer 16 Polycrystalline Si layer 17 WSi ₂ layer 18 (of WSi ₂ ) natural oxide film 19 W layer 20 WO _x film 21 W layer 22 WO _x layer 29 Deposit 50 Interlayer insulating film

Claims (6)

[Claims] 1. A step of forming a conductive etching mask (8, 19) on an interlayer insulating film (50, 5) formed on a lower wiring layer (3, 16, 17), and the etching mask ( 8, 19) to form an opening (11) penetrating the interlayer insulating film (50, 5) to expose the lower wiring layer (3, 17) by dry etching, and following the opening forming step, And a step of forming a conductive coating (13, 21) covering the exposed lower wiring layer (3, 17) while leaving the etching mask, the method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the opening forming step includes dry etching the natural oxide film (4, 18) on the lower wiring layer (3, 17). 3. The step of forming an opening further comprises retreating the surface of the lower wiring layer (3, 17) by dry etching, and covering the side surface of the interlayer insulating film exposed by the opening with a dry etch product (12). The method for manufacturing a semiconductor device according to claim 2, further comprising: 4. The contaminated layer on the surface of the lower wiring layer by further retracting the surface of the lower wiring layer (3) in the step of forming the opening, and subsequently by dry cleaning using at least one of ultraviolet rays, plasma and heat. The method of manufacturing a semiconductor device according to claim 2, further comprising removing (15). 5. The lower wiring layer (3) at least a surface portion of which is formed of an aluminum alloy, and the main component of the etching mask (8) is any one of aluminum, copper and magnesium. A method of manufacturing a semiconductor device according to claim 1. 6. The lower wiring layer (17), at least a surface portion of which is formed of silicide, and the etching mask (19) and the conductive coating (21) are mainly composed of tungsten. A method of manufacturing a semiconductor device according to item 1.