JPH06138973A - Clock synchronizing system - Google Patents

Abstract

(57) [Summary] [Object] Regarding clock synchronization control in a system having a plurality of processing devices, clock synchronization is performed even when multiple τ times are required to transmit a signal between the devices. The purpose is to provide a guaranteed clock synchronization scheme. A register 104 for storing a time required to transmit a signal for synchronous control generated by a specific clock control device 10 to another clock control device 20 is provided, and the clock control device 20 further comprises: It is configured by providing a means for creating a clock based on the value of the register 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to clock synchronous control in a system having a plurality of processing devices which operate at the same timing and perform parallel processing.

In computer systems in recent years, it has been required to further improve the processing capacity due to an increase in processing data. However, since the processing capacity of a single processing unit is approaching its limit, the processing capacity of the system is improved by having a plurality of processing units in the system and performing parallel processing.

[0003]

2. Description of the Related Art In a system having a plurality of processing devices for performing parallel processing, the distance between the devices increases as the number of processing devices increases. In this case, since a common signal cannot be transmitted between the processing devices within a time width of 1τ, it becomes a problem how to supply a common clock to each processing device.

In order to solve this problem, a method of dividing the processing devices into a plurality of groups has been implemented. This method enables 1τ transmission within a group, and also allows 1τ transmission between devices connecting between groups.
Then, the clocks of all processors are synchronized by sending clock control signals between the devices that connect the groups.

A conventional example will be briefly described with reference to FIGS. FIG. 5 is a schematic diagram of the system. This system is composed of two subsystems 50 to 54 and 60 to 64. Here, the devices 54 and 64 having the built-in clock oscillator send the clock signal to the clock control device 5.
It is sent to 0,60. Note that a larger system can be configured by adding the same subsystem.

The clock control devices 50 and 60 are devices for controlling the synchronization of the clocks used in the subsystems 50 to 54 and 60 to 64, respectively.
A common clock is supplied to 53 to 61 and 63 to 63. In addition, the clock control devices 50 and 60 transmit signals for controlling synchronization to each other, and each subsystem 50 to 5
4, 60 to 64 are synchronized.

FIG. 6 is a diagram showing the configuration of a conventional clock control device. In FIG. 6, a clock controller 50
Is a counter 501 and registers 503 to 505, 50.
7, a clock generation circuit 502, and a selection circuit 506. Clock control device 6 of other subsystem
0 is also composed of similar circuits 601 to 607.

5 and 6, when the power is turned on,
Each subsystem starts up as an independent system. At this time, one of the subsystems is operated by the clock of the device 54 containing the clock oscillator,
The other subsystem operates on the clock of the device 64 which contains the clock oscillator.

A conventional method for synchronizing the clocks in the entire system when one of the subsystems is designated as the master and the other subsystem is designated as the slave from this state will be described.

The clock control of the subsystem designated as the master is used as it is, and the counter information output from the counter 501 is shifted to the register 507 via the registers 503 and 504.

Then, the counter 501 temporarily outputs "0",
When it counts up to "1", ..., "7", it becomes "0" again.
If the counter information value is, for example, “0” or “4”, the clock generation circuit 502 generates a clock of 4τ cycle and supplies it to the processing devices 50 to 53.

On the other hand, in the subsystem designated as the slave, from the clock of the device 64 incorporating the clock oscillator in the subsystem designated as the slave to the clock of the device 54 incorporating the clock oscillator in the subsystem designated as the master. The clock is switched to.

When the clock is switched, the counter information signal 508 sent from the master subsystem.
Are set in the register 605. This value is the selection circuit 6
When selected in 06 and set in the register 607, the clock creating circuit 602 creates a clock of 4τ cycle.

FIG. 7 shows a timing chart when the clock is generated as described above. As shown in the figure, the count value of the counter 501 is delayed by 1τ, and
03, and 1 τ later and appearing in the register 504 and the register 605 on the clock controller 60 side.

The value of the register 504 appears in the register 507 because it is selected by the selection circuit 506 at the next timing. Further, at the same timing, the value of the register 605 is selected by the selection circuit 606 and therefore appears in the register 607. Therefore, the counter 50
The count value of 1 is the register 507, after the time of 3τ has elapsed.
It is set to 607.

The clock generation circuits 502 and 602 of the clock control devices 50 and 60 output pulses when the values of the registers 507 and 607 become "0" or "4". Therefore, the clock generation circuits 502 and 602 have four
The same clock is supplied every τ cycle.

[0017]

In the system described above, the number of subsystems increases as the number of devices increases, so that the clock control devices connecting the subsystems can be connected within 1τ time. Therefore, it becomes difficult to transmit a signal for synchronization control.

As described above, the number of subsystems increases, and a plurality of τ's are required to transmit a signal between the clock control devices.
If time is required, it will be necessary to perform air transmission. However, it is very difficult to realize this synchronization control because the transmission τ number changes depending on the clock cycle. Therefore, the conventional method has a problem in that it is impossible to increase the number of devices in order to improve the performance.

The present invention has been made in view of the above-mentioned conventional problems, and even if a plurality of τ times are required to transmit a signal between devices, each of the system is The purpose of the present invention is to provide a clock synchronization system that guarantees the synchronization of clocks supplied to devices, and as a result, it is possible to increase the number of devices on a large scale.

[0020]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, the invention of claim 1 comprises a plurality of devices that operate at the same timing, a device that incorporates a clock oscillator, and a clock control device that supplies the same clock to the plurality of devices. By having a plurality of subsystems and the clock control devices of the plurality of subsystems creating clocks synchronized with each other, all the devices of the plurality of subsystems can be operated at the same timing. In the system configured as described above, a register for storing the time required to transmit a signal for synchronization control generated by a specific clock control device to another clock control device is provided, and the other clock control device is provided with Based on the value of this register, the count value of the counter is counted by the specific clock control device. A clock synchronization method of providing a means for setting the count value same value as the data.

According to the invention of claim 2, a delay is provided in the means for transmitting the signal for the synchronous control from a specific clock control device to another clock control device, and
This is a clock synchronization system in which there is provided transmission means for returning the signal for the synchronization control to the specific clock control device, the transmission means being set to the same delay as the transmission means.

Further, the invention of claim 3 is a clock synchronization system, which is provided with a means for detecting a timing at which the signal returned by the return transmission means can be correctly latched, and a means for transmitting the timing to another clock control device. Is.

[0024]

1 is a diagram showing an embodiment of the present invention. In FIG. 1, the clock control device 10 is a master, and the clock control device 20 is a slave that creates a clock synchronized with the clock of the master. Counter 10
3, 203 are clock control devices 10, 20 respectively.
At, the count operation is performed and the count value that is the basis of the clock is output.

In the clock controller 10, the counter 1
When the value counted by 03 reaches a certain value, the counter 103 outputs the trigger signal for 1τ time. This trigger signal is sent to the synchronization circuit 210 of another clock control device 20 by the cable 107, and then the cable 10
6, the synchronization circuit 1 of its own clock control device 10
Passed to 10.

The clock control device 10, when the trigger signal is transmitted back to its own clock control device 10,
The count value of the counter 103 is set in the register 104.
In addition, the trigger signal synchronization circuit 110 is connected to the cable 10
The trigger signal returned by 6 is input, the timing at which this trigger signal can be correctly latched is detected, and the timing is output as the path selection signal 109.

FIG. 2 is a timing chart for explaining the operation described above. In FIG. 2, the counter 103 starts counting from "0" after counting "0", "1", ..., "7". During this time, the selection circuit 101 selects and outputs the count value of the counter 103. When the clock 103 counts "0", a trigger signal is transmitted to the two cables 106 and 107.

Then, the cable 1 for returning the trigger signal.
From 06, when the first trigger signal is transmitted, the trigger signal synchronization circuit 110 detects the timing at which the trigger signal can be latched, and this timing is detected by the path selection signal 1
It outputs as 09. Further, when the next trigger signal is returned, the count value of the counter 103 is stored in the register 104.
Is set to.

In the register 104, the clock controller 1
Since the propagation time of the signal transmitted from 0 to the clock control device 20 is set, the clock 203 of the clock control device 20 operates in synchronization with the clock 103 of the clock control device 10 based on the value of this register 104. Can be made. A similar value is set in the register 204 of the clock control device 20.

[0030]

EXAMPLES The example shown in FIG. 1 will be further described.
When the power is turned on, each subsystem starts up as one system and operates according to the clock of each device incorporating the clock oscillator. The operation immediately after the power is turned on will be described below with respect to the clock control device 10. The same operation is performed by the clock control device 20 which operates with a clock independent of this.

After the power is turned on, the clock control device 10
The values of the path selection signal 109 for latching the trigger signal in synchronization with the clock and the value of the transmission clock number signal 108 indicating the number of τ required for transmission of the trigger signal are determined. The values of the path selection signal 109 and the transmission clock number signal 108 can be determined as follows.

When the power supply of the clock control device 10 is decided, the counter 103 starts counting operation. When the counter 103 counts “0”, a trigger signal is output to the two cables 106 and 107. The clock control device 10 receives the trigger signal transmitted back from the cable 106.

Here, a partial configuration example of the clock control device 10 is shown in FIG. In FIG. 4, the clock control device 10 has a latch 46 that receives the trigger signal transmitted back and forth, and a latch 47 that receives the trigger signal that has passed through the [delay circuit B] 44. The values of both latches are compared by the EOR circuit 49, and the result is set in the latch 48 which outputs the path selection signal 109.

For example, the EOR circuit 49 compares the values of both latches 46 and 47 when either of the two latches 46 and 47 receiving the trigger signal becomes "1".
Then, if they are the same value, that is, "1", "0" is output, and if they are different values, that is, if either one is "0", "1" is output.

This output signal is set in the latch 48,
It is output as the path selection signal 109. At the same time, the value of the latch 48 is selected by the selection circuit 42 and becomes the signal A for controlling the selection circuit 41.

Subsequently, when the next trigger signal is transmitted to the cables 106 and 107, the clock control device 10
The trigger signal transmitted back from the cable 106 is
It is selected by the selection circuit 40 and input to the [delay circuit A] 43.

The output signal of the [delay circuit A] 43 is
It is input to the selection circuit 41 through two types of paths. The selection circuit 41 selects a through path when the signal A equivalent to the path selection signal 109 is “0” and a path passing through the [delay circuit B] 45 when the signal A is “1”.

The output of the selection circuit 41 determines the timing for setting the value of the counter 103 in the register 104.
That is, the register 104 latches the value of the counter 103 when the selection signal 41 outputs the trigger signal. At this time, the value of the counter 103 is the signal of the cable 106,
The time required to transmit 107 is represented by the τ number.

Next, the clock generating operation of each subsystem when the subsystem including the devices 11 to 13 is the master and the subsystem including the devices 21 to 23 is the slave will be described.

As described above, initially, both the master subsystem and the slave subsystem start up as separate systems. At this time, in the master subsystem, the transmission clock number signal 108 and the path selection signal 109 are fixed, and similarly in the slave subsystem,
The transmission clock number signal 208 and the path selection signal 209 are determined.

In the subsystem including the clock controller 10, the master is set. At this time, the clock operation in the clock control device 10 is maintained as it is. On the other hand, a slave is set in the subsystem including the clock control device 20.

In the clock controller 20, since the slave is set, its clock is changed from the clock of the device having the clock oscillator included in the slave subsystem to the device having the clock oscillator included in the master subsystem. Switch to the clock.

The trigger signal sent from the master clock control circuit 10 via the cable 107 is selected by the selection circuit corresponding to the selection circuit 40 shown in FIG. 4 in the slave clock control circuit 20, and the [delay circuit A ] 43 corresponding to [delay circuit A].

In the clock controller 20, the output of the [delay circuit A] is selected by the selection circuit corresponding to the selection circuit 41 of FIG. 4 by the path selection signal 109 sent in advance. That is, if the value of the path selection signal 109 is "0", the through path is "1".
If so, the path passing through the delay circuit B is selected.

Here, in the clock control device 20, when the signal selected by the selection circuit corresponding to the selection circuit 41 in FIG. 4 is "1", the transmission clock number signal already sent from the clock control device 10 The selection circuit 201 selects the transmission τ number of 108, and a value obtained by adding “1” to this τ number is set in the counter 203.

In the clock control device 20, when the signal selected by the selection circuit corresponding to the selection circuit 41 of FIG. 4 is "0", the selection circuit 201 selects the output signal of the counter 203 and the counter 203. Adds "1" to the count value up to then and performs a normal count operation.

By the above operation, the clock controller 10
The counter 103 and the counter 203 of the clock control device 20 count the same value at the same timing. Therefore, the clock generation circuits 105 and 205 in the respective subsystems can generate equivalent clocks.

FIG. 3 shows a timing chart for explaining the above operation. In FIG. 3, each subsystem starts up as an independent system after the power is turned on. Therefore, during the initial period, each counter 103, 20
The counts of 3 are different. Master counter 103
Starts counting “6” and “7” and then outputs a trigger signal to the cable 107 when counting “0”.

The trigger signal output to the cable 107 is transmitted to the slave clock control device 20 and used as a signal indicating the timing of setting the value of the transmission clock number signal 108 in the counter 203. That is, the value of the transmission clock number signal 108 is set to “1” at the timing next to the transmission of the trigger signal to the counter 203.
The value obtained by adding is to be set.

In the figure, the counter 203 counts "1" at the timing when the trigger signal is transmitted. At this time, the selection circuit 201 selects the transmission clock number signal 108 instead of the count value of the counter 203.

Since the value of the transmission clock number signal 108 is "4", the count value of the counter 203 becomes "5" at the next timing. After that, the same clock of 4τ cycle is output from each of the clock generation circuits 105 and 205.

In the above embodiments, the synchronous control method in two subsystems has been described as an example, but it is obvious that the present invention can be applied to a system having more subsystems. The connections in this case may be all connections between clock control devices of each subsystem, or may be a loop-like connection that connects only adjacent devices.

In this case, if the configuration is set to subsystems closer to the master subsystem and to subsystems farther away, the clocks will be synchronized in order, so that the clocks of all subsystems will eventually be synchronized. Can be made.

In addition, the transmission between the subsystems may be different from each other by τ
Even in a system that transmits by number, the cable 10
Clocks can be easily synchronized by setting equal delays only to the cables corresponding to 6, 107 and 206, 207.

[0055]

As described above, according to the present invention,
Even in a system in which a plurality of τ times is required for signal transmission between subsystems, the clocks can be synchronized, so that a large-scale parallel processing system can be constructed. Moreover, even if the clock cycle changes, there is an advantage that the clock can be synchronized in accordance with the number of transmission τ that is automatically measured and determined.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of creating a transmission clock number signal.

FIG. 3 is a timing chart illustrating a clock synchronization operation according to the present invention.

FIG. 4 is a diagram showing a partial configuration example of a clock control device according to the present invention.

FIG. 5 is a schematic diagram of a system.

FIG. 6 is a diagram showing a configuration of a conventional clock control device.

FIG. 7 is a timing chart illustrating a conventional clock generation operation.

[Explanation of symbols]

10, 20, 50, 60 Clock control device 11-13, 21-23, 51-53, 61-63 Processing device 40-42, 101, 201, 506, 606 Selection circuit 43-45 Delay circuit 46-48, 104 , 204, 503 to 505, 50
7,603 to 605,607 Register 49 EOR circuit 54,64 Device incorporating a clock oscillator 103,203,501,601 Counter 105,205,502,602 Clock generation circuit 106,107,206,207 Cable 108,208 Transmission Clock number signal 109,209 Path selection signal 110,210 Synchronization circuit 508,509 Counter information signal

Claims (3)

[Claims] 1. A plurality of devices (11) to (13) operating at the same timing, a device containing a clock oscillator, and a clock control device (10) for supplying the same clock to the plurality of devices. By having multiple subsystems including and, each clock control device of these multiple subsystems creates clocks that are synchronized with each other, all devices of multiple subsystems have the same timing. In a system configured to be operated, a register (104) that stores a time required to transmit a signal for synchronization control generated by a specific clock control device (10) to another clock control device (20). ) Is provided, and this register (10
A means for setting the count value of the counter (203) to the same value as the count value of the counter (103) of the specific clock control device (10) based on the value of 4). Clock synchronization method. 2. A signal for the synchronous control is sent from a specific clock control device (10) to another clock control device (2).
0) is provided with a delay in the means (107) for transmitting to the specific clock control device (10) and a signal for returning the synchronization control signal to the specific clock control device (10), such as the means (107) for transmitting. One set as a delay (10
6. The clock synchronization system according to claim 1, wherein 6) is provided. 3. The clock synchronization according to claim 2, further comprising means for detecting a timing at which the signal returned by the return transmission means (106) can be correctly latched, and means for transmitting the timing to another clock control device. Method.