JPH0613854A - Offset correction type comparator and circuit using the same - Google Patents

Abstract

PURPOSE:To reduce a statistic variance range of the offset voltage by connecting together the outputs of plural differential amplifier circuits or comparators via an OR or AND logic circuit and using these outputs from the comparators. CONSTITUTION:When the offset voltage of a differential amplifier circuit 4 is smaller than that of a differential amplifier circuit 5, i.e., the offset voltage is set at the negative value, the voltage V2 smaller than the voltage V1 increases and exceeds the V1. In this process, a MOSFET 6 is turned on earlier than a MOSFET 7. The drains of both FET 6 and 7 are connected to the input terminal of an OR gate 3 and therefore the output Vout of the gate 3 is set at an H level as soon as the FET 6 is turned on. The output Vout of the gate 3 is kept at an H level until both FET 6 and 7 are turned off. So is even with a case where V1>V2 is satisfied between both circuits 4 and 5 in terms of their offset voltage. Therefore the variance distribution of the offset voltage is automatically comprised and the variance range of the offset voltage is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator or a circuit such as an analog / digital conversion circuit using the comparator, and more particularly to a comparator excellent in offset characteristics or a circuit using the comparator.

[0002]

2. Description of the Related Art Comparators are widely used in analog / digital conversion circuits and the like, and a differential amplifier circuit is used as an input stage amplifier circuit thereof.

In a monolithic IC, transistors formed on the same silicon chip are processed under exactly the same conditions. Therefore, current amplification factor, base-emitter voltage,
The resistance values are essentially the same. Therefore, a circuit such as a differential amplifier circuit in which the balance of transistors and resistances is the basis of circuit design is most suitable.

[0004]

In the differential amplifier circuit of the IC, although there are few variations in the characteristics between the elements used, in reality, there are some finite variations in the characteristics.
Therefore, even when the same input voltage is applied to a plurality of differential amplifier circuits having the same specifications, this variation of each differential amplifier circuit is mainly due to the base-emitter voltage of the differential pair transistor and the direct current amplification factor, and It is caused by imbalance of collector load resistance. These parameters are influenced by, for example, variations in manufacturing such as photoresist processing, ion implantation, and diffusion, variations in resistance value of the taken-out portion of each electrode, and temperature difference in the chip.

The variations in these characteristics appear as variations in the offset voltage of the comparator circuit.

An example of a conventional comparator in consideration of offset voltage is the invention described in Japanese Patent Laid-Open No. 60-113514. According to the present invention, two comparators having the same offset voltage are connected in parallel and with their polarities inverted and connected, and the AND logic of this output is used to cancel the offset voltage possessed by each comparator to reduce the influence of the offset voltage. It is something to be removed. That is, this conventional example aims to improve the offset voltage itself, and does not consider the above variations.

On the other hand, the present invention is a technology which is obviously different in that it is intended to improve the offset voltage in consideration of the variation characteristic of the offset voltage of the comparator between the manufacturing lots.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a comparator and a circuit using the comparator in which the statistical variation range of the offset voltage is reduced.

[0009]

An offset correction type comparator according to the present invention has a plurality of differential amplifier circuits and a logic circuit for performing logical operation of output signals of the plurality of differential amplifier circuits. The first input terminals of the differential amplifier circuits are connected to each other, the second input terminals of the plurality of differential amplifier circuits are connected to each other, and the first output terminals of the differential amplifier circuits are The second output terminal or both are O
It is characterized in that it is connected to an input terminal of a logic circuit which constitutes R logic or NOR logic.

Further, the offset correction type comparator of the present invention has a plurality of differential amplifier circuits and a logic circuit for performing a logical operation of output signals of the plurality of differential amplifier circuits, and each of the plurality of differential amplifier circuits. First input terminals of the differential amplifier circuits are connected to each other, second input terminals of the plurality of differential amplifier circuits are connected to each other, and a first output terminal or a second output of each differential amplifier circuit is connected. It is characterized in that the terminal or both of them are connected to an input terminal of a logic circuit forming AND logic or NAND logic.

Further, the offset correction type comparator of the present invention comprises a plurality of differential amplifier circuits, a first logic circuit for performing an OR logical operation of output signals of the plurality of differential amplifier circuits, and the plurality of differential amplifier circuits. A second logic circuit for performing an AND logical operation of the output signals of the circuit; and a switch means for switching so as to selectively input the output signals of the plurality of differential amplifier circuits to the first or second logic circuit. The first input terminals of the plurality of differential amplifier circuits are connected to each other, the second input terminals of the plurality of differential amplifier circuits are connected to each other, and the switch means is configured to supply the power supply voltage. It is characterized in that the output signals of the plurality of differential amplifier circuits are switched so as to be selectively input to the first or second logic circuit according to the level.

The offset correction type comparator of the present invention has a plurality of comparators and a logic circuit for performing a logical operation of the output signals of the plurality of comparators, and the first input terminals of the plurality of comparators are mutually connected. And the second input terminals of the plurality of comparators are connected to each other, and the output terminals of the plurality of comparators are connected to the input terminals of a logic circuit that forms OR logic or NOR logic. Characterize.

Further, the offset correction type comparator of the present invention has a plurality of comparators and a logic circuit for performing a logical operation of the output signals of the plurality of comparators, and the first input terminals of the plurality of comparators are mutually connected. And that the second input terminals of each of the plurality of comparators are connected to each other and the output terminals of each of the plurality of comparators are connected to the input terminals of a logic circuit forming AND logic or NAND logic. Characterize.

Further, the offset correction type comparator of the present invention includes a plurality of comparators, a first logic circuit for performing an OR or NOR logical operation of the output signals of the plurality of comparators, and an AND of the output signals of the plurality of comparators. A second logic circuit for performing a NAND logic operation; and a switch means for switching the output signals of the plurality of comparators so as to be selectively input to the first or second logic circuit. The first input terminals are connected to each other, the second input terminals of the plurality of comparators are connected to each other, and the switch means outputs the output signals of the plurality of comparators to the first input terminals according to the power supply voltage level. Alternatively, it is characterized in that it is switched so as to be selectively input to the second logic circuit.

Further, the circuit of the present invention is characterized in that it is configured by using the offset correction type comparator.

The offset correction type comparator of the present invention is characterized in that it is formed on a monolithic substrate.

Further, the circuit of the present invention is characterized by being formed on a monolithic substrate.

[0018]

As described above, by logically combining the outputs of a plurality of differential amplifier circuits or comparators and using them as the output of a new differential amplifier circuit or comparator, the finite variation in the statistical offset voltage is reproduced. Since the distribution of the variation of the offset voltage is condensed to the higher or lower side of the offset voltage, the statistical variation range of the offset voltage can be reduced.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an embodiment of a comparator according to the present invention, and FIG. 2 is an implementation of the comparator shown in FIG. 1 with a CMOS configuration.

In these figures, 1 and 2 are comparators, which are connected in parallel with each other. 3 is 2
It is an input OR logic gate, the input end of which is connected to the output ends of the comparators 1 and 2. Numerals 4 and 5 are differential amplifier circuits which form the comparators 1 and 2, respectively, and 6 and 7 are MOSFETs which form the output stage of the comparators 1 and 2, respectively. It turns on when the potential increases. Reference numerals 8 and 9 are reference voltage sources.

In the above configuration, when the offset voltage of the differential amplifier circuit 4 is lower than the offset voltage of the differential amplifier circuit 5, that is, the negative side value, V2 rises from the state of V2 <V1. , V2> V1
MOSFET 6 is MOSFET due to low offset voltage
Turn on before 7.

However, the drain of MOSFET 6 and M
Since the drains of the OSFETs 7 are connected to the input ends of the OR logic gates 3, the output Vout of the OR logic gates 3 becomes high level at the moment when the MOSFETs 6 are turned on, and the output of the OR logic gates 3 is turned off until both the MOSFETs 6 and 7 are turned off. The output Vout maintains the high level.

The same applies when the offset voltage of the differential amplifier circuit 4 is higher than the offset voltage of the differential amplifier circuit 5.
Therefore, the offset voltage of the entire comparator shown in FIGS. 1 and 2 is determined by the offset voltage of the differential amplifier circuit having the lower offset voltage.

By the way, it is known that the offset voltage of the differential amplifier circuit varies due to the imbalance of the differential pair transistors, and the Gaussian distribution shown by the solid line in FIG.

On the other hand, in the comparators shown in FIGS. 1 and 2, since the distribution of the offset voltage variations is concentrated in the lower side than the conventional comparator as described above, the offset voltage variations are indicated by the one-dot chain line in the figures. Is reorganized automatically. Therefore, the variation range of the offset voltage can be reduced. Incidentally, instead of the OR logic gate, NO
Similar effects can be obtained by reconfiguring the circuit using R logic gates.

FIG. 4 shows the configuration of another embodiment of the comparator according to the present invention.

In this embodiment, the reference voltage sources 8 and 9 for supplying the reference voltage to the comparators 1 and 2 in FIG.
The functions of SFETs 6 and 7 are also incorporated in the OR logic gate 3 to reduce the number of parts. As a result, the comparator 1,
There is an advantage that variations in offset voltage caused by variations in characteristics in portions other than the differential amplifier circuit that configures 2 can be reduced.

FIG. 5 shows the configuration of still another embodiment of the comparator according to the present invention.

In this embodiment, n comparators 20-
, 20-n are connected in parallel, and the outputs of these comparators are connected to an n-input OR logic gate 21.

In the above configuration, n comparators 2
The outputs of 0-1, 20-2, ... 20-n are ORed by the OR logic gate 21 to further condense the distribution of offset voltage variations shown in FIG. The variation range can be reduced. Similar effects can be obtained by reconfiguring the circuit by using NOR logic gates instead of OR logic gates.

Next, FIG. 6 shows the configuration of still another embodiment of the comparator according to the present invention. In the figure, 30 is an inverter, 34, 35, 36, 37 are MOSFETs, 3
Reference numerals 8 and 40 are OR logic gates, and 39 is an AND logic gate. In the embodiment shown in FIGS. 1, 2, 4 and 5, the power supply voltage V
When the output voltage of the reference voltage source fluctuates due to fluctuations in cc, etc.,
The current flowing through the differential amplifier circuit that constitutes each comparator fluctuates, and as a result, the center value of the offset voltage moves to high or low, so that there is a possibility that the variation range of the offset voltage will apparently widen as shown by the solid line in FIG. there were.

In the present embodiment, the output voltage value of the reference voltage source 33 is detected by the inverter 30, and the MOSFETs 34, 3 are detected.
5, 36 and 37 are controlled to be turned on and off, and the outputs of the differential amplifier circuit 31 and the differential amplifier circuit 32 are switched between input to the AND gate 39 and OR gate 38. . For example, when the power supply voltage Vcc is at the center value, the output voltage of the reference voltage source is used as the threshold value of the inverter 30. In this case, when the power supply voltage Vcc drops and the output voltage of the reference voltage source 33 becomes equal to or lower than the threshold value of the inverter 30, a high level signal is output at the reference voltage value or lower, so that the MOSFETs 35 and 37 are turned on and the MOSFET 3 is turned on.
4, 36 are turned off, the differential amplifier circuit 31, the differential amplifier circuit 3
Since the output of 2 is input to the AND gate 39, the distribution of offset voltage variations is condensed to the right.

On the contrary, when the power supply voltage Vcc is higher than the central value, the outputs of the differential amplifier circuit 31 and the differential amplifier circuit 32 are O.
It is input to the R gate 38 and the distribution of offset voltage variations is condensed on the left side. As a result, the variation range of the offset voltage is reduced as shown by the dotted line in FIG. Similar effects can be obtained by using a NOR logic gate instead of the OR logic gate and a NAND logic gate instead of the AND logic gate.

Although the CMOS configuration circuit has been described above, the present invention is not limited to this, and the same applies to a bipolar configuration, for example.

Next, FIG. 8 shows the structure of an A / D converter for converting an analog signal to a digital signal to which the present invention is applied. In the figure, the A / D converter includes a reference voltage source 50 including resistor groups R-1, R-2, ... Rn for generating a reference voltage, and comparators 60-1, 60-2 ,.
-N and comparators 60-1, 60-2, ... 60-n
EOR gate 70-which takes the exclusive OR of the output signals of
1, 70-2, 70-3 ... 70-n.

This A / D converter compares the input analog voltage with the reference voltage generated by the reference voltage source 50 by the comparators 60-1, 60-2, ... 60-n,
EOR gates 70-1, 70-
2, 70-3 ... 70-n through output terminals 80-1, 80
A digital signal of 1 or 0 is output from -2, ..., 80-n.

In this A / D converter, the limit of subdivision of the reference voltage is determined by the offset voltage characteristic of each comparator, and the accuracy as the A / D converter is determined. Therefore, by applying the comparator according to the present invention as a comparator of this A / D converter, the accuracy of the A / D converter can be remarkably improved.

Although the above has been described with reference to a typical embodiment of the present invention, the present invention is not limited to this, and various modifications can be made within the scope of the technical idea of the present invention.

[0039]

According to the present invention, it is possible to realize a comparator excellent in offset voltage characteristic and a circuit using this comparator.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of an offset correction type comparator according to the present invention.

FIG. 2 is a circuit diagram showing an example in which the offset correction type comparator shown in FIG. 1 is embodied by a CMOS structure.

FIG. 3 is a characteristic diagram for explaining the effect of the offset correction type comparator shown in FIGS. 1 and 2.

FIG. 4 is a circuit diagram showing another embodiment of the offset correction type comparator according to the present invention.

FIG. 5 is a circuit diagram showing still another embodiment of the offset correction type comparator according to the present invention.

FIG. 6 is a circuit diagram showing still another embodiment of the offset correction type comparator according to the present invention.

FIG. 7 is a characteristic diagram for explaining an effect of the offset correction type comparator according to the present invention shown in FIG.

FIG. 8 is a circuit diagram showing a configuration of an analog / digital converter configured by using an offset correction type comparator according to the present invention.

[Explanation of symbols]

 1 comparator 2 comparator 3 OR logic gate 4 differential amplifier circuit 5 differential amplifier circuit 6 MOSFET 7 MOSFET 8 reference voltage source 9 reference voltage source 10 reference voltage source 20 comparator 21 OR logic gate 22 input terminal 23 input terminal 24 output terminal 30 Inverter 31 Differential amplifier circuit 32 Differential amplifier circuit 33 Reference voltage source 34 MOSFET 35 MOSFET 36 MOSFET 37 MOSFET 38 OR logic gate 39 AND logic gate 40 OR logic gate

Claims (9)

[Claims] 1. A plurality of differential amplifier circuits and a logic circuit that performs a logical operation of output signals of the plurality of differential amplifier circuits, wherein a first input terminal of each of the plurality of differential amplifier circuits is provided. The differential amplifier circuits are connected to each other and the second input terminals of the plurality of differential amplifier circuits are connected to each other, and the first output terminal and / or the second output terminal of each differential amplifier circuit are OR logic or An offset correction type comparator characterized in that it is connected to an input terminal of a logic circuit which constitutes NOR logic. 2. A plurality of differential amplifier circuits, and a logic circuit that performs a logical operation of output signals of the plurality of differential amplifier circuits, wherein a first input terminal of each of the plurality of differential amplifier circuits is The second input terminals of each of the plurality of differential amplifier circuits are connected to each other, and the first output terminal and / or the second output terminal of each of the differential amplifier circuits are ANDed.
An offset correction type comparator characterized in that it is connected to an input terminal of a logic circuit which constitutes logic or NAND logic. 3. A plurality of differential amplifier circuits, a first logic circuit that performs an OR logic operation on output signals of the plurality of differential amplifier circuits, and an AND logic operation of output signals of the plurality of differential amplifier circuits. And a switch means for switching the output signals of the plurality of differential amplifier circuits so as to selectively input to the first or second logic circuit. The first input terminals of the amplifier circuits are connected to each other, the second input terminals of the plurality of differential amplifier circuits are connected to each other, and the switch means is configured to switch the plurality of differential circuits according to a power supply voltage level. An offset correction type comparator, wherein the output signal of the dynamic amplification circuit is switched so as to be selectively input to the first or second logic circuit. 4. A plurality of comparators and a logic circuit that performs a logical operation of output signals of the plurality of comparators, wherein first input terminals of the plurality of comparators are connected to each other, and the plurality of comparators are connected to each other. An offset correction type comparator characterized in that the second input terminals of the comparators are connected to each other, and the output terminals of each of the plurality of comparators are connected to the input terminals of a logic circuit forming an OR logic or a NOR logic. 5. A plurality of comparators and a logic circuit that performs a logical operation of output signals of the plurality of comparators, wherein first input terminals of the plurality of comparators are connected to each other, and the plurality of comparators are connected to each other. An offset correction type comparator characterized in that the second input terminals of the comparators are connected to each other, and the output terminals of each of the plurality of comparators are connected to the input terminals of a logic circuit forming AND logic or NAND logic. 6. A plurality of comparators, a first logic circuit for performing an OR or NOR logical operation of output signals of the plurality of comparators, and A of output signals of the plurality of comparators.
A second logic circuit for performing an ND or NAND logic operation; and a switch means for switching the output signals of the plurality of comparators so as to be selectively input to the first or second logic circuit. The first input terminals of the comparators are connected to each other, the second input terminals of the plurality of comparators are connected to each other, and the switch means outputs the output signals of the plurality of comparators according to the power supply voltage level. An offset correction type comparator characterized by switching so as to selectively input to the first or second logic circuit. 7. A circuit comprising the offset correction type comparator according to any one of claims 1 to 6. 8. The offset correction type comparator according to claim 1, which is formed on a monolithic substrate. 9. The circuit according to claim 7, which is formed on a monolithic substrate.