JPH06120801A - ECL-CMOS level conversion circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable high-speed signal transmission. A master latch circuit 10 that takes in a first signal of an ECL level and a second signal that is an inverted signal of the first signal in accordance with a clock signal, amplifies and latches to a CMOS level, and an output of the master latch circuit A slave latch circuit 15 which takes in according to the clock signal,
It is characterized by having.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable from the ECL level to the CMO.
The present invention relates to an ECL-CMOS level conversion circuit for converting to an S level.

[0002]

2. Description of the Related Art FIG. 6 shows the configuration of a conventional ECL-CMOS level conversion circuit for converting an ECL level to a CMOS level. This ECL-CMOS level conversion circuit is formed on an LSI chip, and has a differential amplifier circuit 2, an emitter follower type buffer circuit 4, a CMOS current mirror type sense amplifier 5, a CMOS buffer 6, and a D type flip-flop ( Hereinafter, also referred to as DFF) 7. The differential amplifier circuit 2 is an NPN type transistor Q.
1, Q2, Q3, Q4, Q5 and resistors R1, R2, R3
And have. The collector of the transistor Q1 is connected to the high voltage power supply V _p1 and its emitter is the transistor Q2.
Connected to the collector and base of the ECL
It is connected to the pad 1 to which a level signal is input.
The emitter of the transistor Q2 is connected to the low voltage power supply V _p2 via the resistor R3. The collectors of the transistors Q3 and Q4 forming a differential pair are connected to the high voltage power supply V _p1 via resistors R1 and R2, respectively, and the emitters thereof are commonly connected to the collector of the transistor Q5. The base of the transistor Q3 is connected to the emitter of the transistor Q2, and the reference potential V _ref is applied to the base of the transistor Q4. The emitter of the transistor Q5 is connected to the low voltage power supply V _p2, and the bias voltage V _Bias is applied to the base.

The emitter follower type buffer circuit 4 is an NP
It has N-type transistors Q6 and Q7 and resistors R4 and R5. The collectors of the transistors Q6 and Q7 are connected to the power supply V _p1 , the emitters are connected to the power supply V _p2 via the resistors R4 and R5, respectively, and the base is the transistor Q _p.
3 and Q4 collectors, respectively.

The CMOS current mirror type sense amplifier circuit 5 includes P channel MOS transistors TP1 and TP2.
And N-channel MOS transistors TN1 and TN2. One end of the transistor TP1 is connected to the power supply V _p1 and the other end is connected to one end of the transistor TN1
The gate is connected to the emitter of the transistor Q6. The other end of the transistor TN1 is connected to the power supply V _p2 . Further, one end of the transistor TP2 is connected to the power supply V _p1 , the other end is connected to one end of the transistor TN2, and the gate is connected to the emitter of the transistor Q7. The other end of the transistor TN2 is connected to the power supply V _p2 . The gates of the transistors TN1 and TN2 are connected to the connection point between the transistor TP1 and the transistor TN1.

The CMOS buffer 6 includes a P channel MOS transistor TP3 and an N channel MOS transistor T.
In the CMOS inverter composed of N3, the input end is connected to the connection point between the transistor TP2 and the transistor TN2 of the sense amplifier circuit 5, and the output end is connected to the D terminal of the flip-flop. In addition, the CMOS inverter 6
_Are driven by power supplies V _p1 and V _p2 .

Next, the operation of the ECL-CMOS level conversion circuit will be described. When an ECL level input signal is input from the pad 1, the potential V of the base of the transistor Q3 is
_in has a value obtained by shifting the base potential of the transistor Q1 downward by the base-emitter voltage V _{BE of} each of the transistors Q1 and Q2. Then, the base potential V _in of the transistor Q3 is compared with the reference potential V _ref applied to the transistor Q4. ECL level input signal is "H"
For level to become higher than the potential V _in the reference potential V _ref, the potential of the base of the base potential becomes lower transistor Q7 of the transistor Q6 which is the output of the differential amplifier circuit 2 becomes higher. On the other hand, the ECL level input signal is "L".
For level becomes lower than the potential V _in the reference potential V _ref, the base potential of the base potential becomes high transistor Q7 of Q6 which is the output of the differential amplifier circuit 2 is lowered.

The output of the differential amplifier circuit 2 is sent to the emitter-follower type buffer circuit 4 and current-amplified. The output of the buffer circuit 4 is sent to the sense amplifier circuit 5 and C
It is converted to a MOS level, sent to the D-type flip-flop 7 via the CMOS buffer circuit 6, and latched.

An example of another conventional ECL-CMOS level conversion circuit is shown in FIG. This level conversion circuit includes an amplifier circuit 3a, a CMOS buffer circuit 3b, and a D-type flip-flop 7. The differential amplifier circuit 3a has N
PN type transistors Q8 and Q9, P type MOS transistors MP1 and MP2, and N type MOS transistor MN
1 and MN2. The collectors of the transistors Q8 and Q9 are connected to the high potential power supply V _p1 and the emitters are connected to the sources of the transistors MP1 and MP2, respectively. E to the base of transistor Q8 via pad 1
A CL level signal is input, and the reference potential V _ref is input to the base of the transistor Q9. On the other hand, the gates of the transistors MP1 and MP2 are commonly connected, and the low potential power
_p2 , each drain having a transistor MN1,
Connected to the drain of MN2. Transistor MN1,
The gates of MN2 are transistor MP2 and transistor M
It is connected to the connection point of N2, and its source is connected to the power supply V _p2 . The output of the differential amplifier circuit 3a is the transistor MP1.
And the CMO
It is sent to the S buffer circuit 3b.

The CMOS buffer circuit 3b is a P channel M
A first CMOS inverter including an OS transistor MP3 and an N-channel MOS transistor MN3, a P-channel MOS transistor MP4 and an N-channel MOS transistor
It has a second CMOS inverter composed of a transistor MN4. The first and second CMOS inverters are connected in series.

Next, the operation of the level conversion circuit shown in FIG. 7 will be described. When an ECL level signal is input to the pad 1, the potential V _{in of} this signal is compared with the reference potential V _ref ,
For potential V _in is at the "H" level, the output of the differential amplifier circuit 3a is high, if the potential V _in the "L" level, the output of the differential amplifier circuit 3a is lowered. Although the output of the differential amplifier circuit 3a is not at the complete CMOS level, it is completely converted to the CMOS level by the CMOS buffer circuit 3b. In addition, since the two stages of inverters are provided, the polarity matches the ECL level signal. The output of the CMOS buffer circuit 3b is latched by the D-type flip-flop 7.

[0011]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the CL-CMOS level conversion circuit, since the amplification capability is large but the number of stages is large, the time from the input of the ECL level signal to the conversion to the CMOS level and the latching in the D-type flip-flop 7, that is, the signal transmission. There was a problem that the time was large.

The present invention has been made in consideration of the above circumstances, and is an ECL- that can perform signal transmission at high speed.
It is an object to provide a CMOS level conversion circuit.

[0013]

A master latch circuit for taking in a first signal of an ECL level and a second signal which is an inversion signal of the first signal in accordance with a clock signal, amplifying it to a CMOS level and latching it. A slave latch circuit that takes in the output of the master latch circuit according to the clock signal.

[0014]

The ECL-CMO of the present invention constructed as described above
According to the S level conversion circuit, the number of passage stages of the gate is smaller than that of the conventional one. As a result, signal transmission can be performed faster than in the conventional case.

[0015]

FIG. 1 shows the configuration of a first embodiment of an ECL-CMOS level conversion circuit (hereinafter also referred to as a level conversion circuit) according to the present invention. The level conversion circuit of this embodiment includes a differential amplifier circuit 2, an emitter follower type buffer circuit 4,
A master latch circuit 10 and a slave latch circuit 15 are provided. The differential amplifier circuit 2 and the emitter follower type buffer circuit 4 have already been described in the section of the prior art, and therefore description thereof will be omitted. The master latch circuit 10 includes transfer gates 11a and 11b composed of MOS transistors, and C
It has MOS inverters 14a and 14b. or,
The slave latch circuit 15 is a clocked inverter 17,
It has 18a and CMOS inverters 18b and 19.

The transfer gate 11a has one end connected to one output of the emitter follower buffer circuit 4, that is, the emitter of the transistor Q7, and the other end connected to the output end of the inverter 14a and the input end of the inverter 14b. Further, the transfer gate 11b has one end of the output of the emitter follower type buffer circuit 4
That is, it is connected to the emitter of the transistor Q8, and the other end is connected to the input end of the inverter 14a and the output end of the inverter 14b. And transfer gate 11
An inverted signal bar φ of the clock signal φ is input to the gates of a and 11b.

The clocked inverter 17 has its input end connected to the output end of the inverter 14a and the input end of the inverter 14b, and its output end connected to the output end of the clocked inverter 18a, the input end of the inverter 18b and the input end of the inverter 19. It is connected. Inverter 1
The output terminal of 8b is connected to the input terminal of the clocked inverter 18a.

Next, the operation of this embodiment will be described. Pad 1
When an ECL level signal is input to, the signal is differentially amplified by the differential amplifier circuit 2 and further sent to the emitter follower type buffer circuit 4 for current amplification. Then, a pair of amplified signals having opposite polarities are output from the two output ends of the emitter follower type buffer circuit 4,
It is sent to the master latch circuit 10 according to the clock signal bar φ. Since the master latch circuit 10 functions as a latch type sense amplifier, the output of the emitter follower type buffer circuit is amplified to the CMOS level. And this C
The signal amplified to the MOS level is latched by the slave latch circuit 15 and is output from the output terminal of the inverter 19. Since the level conversion circuit of the present embodiment has a smaller number of gate passage stages than the conventional level conversion circuit,
Signal transmission can be performed at high speed. In addition, the number of elements is smaller than in the conventional case, and it is possible to make the device compact.

Next, FIG. 2 shows the configuration of the second embodiment of the level conversion circuit according to the present invention. The level conversion circuit of this embodiment is the level conversion circuit of the first embodiment shown in FIG. 1 in which a master latch circuit 12 is provided instead of the master latch circuit 10. The master latch circuit 12 includes the transfer gates 11a and 11b of the master latch circuit 10 shown in FIG.
3a, 13b. The transfer gates 13a and 13b are each composed of a P channel MOS transistor and an N channel MOS transistor, and operate based on the clock signal φ. The level conversion circuit of the second embodiment also has the same effect as the level conversion circuit of the first embodiment.

Next, the configuration of the third embodiment of the level conversion circuit according to the present invention is shown in FIG. The level conversion circuit of the third embodiment is the same as the second embodiment shown in FIG. 2, except that the emitter follower type buffer circuit 4 is deleted and the output of the differential amplifier circuit 2 is directly input to the master latch circuit 12. . The level conversion circuit of the third embodiment has a smaller amplification ability than the level conversion circuit of the second embodiment, but the number of gate passage stages is small, so that the signal can be transmitted at a higher speed. Further, since the number of elements is smaller than that of the second embodiment, it can be made compact.

Next, the configuration of the fourth embodiment of the level conversion circuit according to the present invention is shown in FIG. The level conversion circuit of this embodiment is the same as that of the third embodiment shown in FIG.
Is replaced by the differential amplifier circuit 3a shown in FIG.
It goes without saying that the fourth embodiment also has the same effects as the third embodiment.

Next, the configuration of the fifth embodiment of the level conversion circuit according to the present invention is shown in FIG. In the level conversion circuit of this embodiment, the differential amplifier circuit 2 is eliminated from the third embodiment shown in FIG. 3, and the transfer gate 1 of the master latch circuit 12 is removed.
An input terminal of 3a is connected to a pad 1a to which an ECL level signal is input, and an input terminal of a transfer gate 13b of the latch circuit 12 is connected to a pad 1b to which an inverted signal of the ECL level signal is input. Is. The level conversion circuit of the fifth embodiment has a smaller amplification capability than that of the third embodiment, but since the number of gate passage stages is small, signal transmission can be performed at a higher speed. Further, since the number of elements is smaller than that of the third embodiment, it can be made compact.

[0023]

As described above, according to the present invention, signal transmission can be performed at high speed and the size can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional ECL-CMOS level conversion circuit.

FIG. 7 is a circuit diagram showing another example of a conventional ECL-CMOS level conversion circuit.

[Explanation of symbols]

 1 Pad 2 Differential Amplifier Circuit 4 Emitter Follower Type Buffer Circuit 10 Master Latch Circuit 15 Slave Latch Circuit

Claims (3)

[Claims] 1. A first signal of ECL level and this first signal.
A master latch circuit that takes in a second signal, which is an inversion signal of the above signal, according to a clock signal, amplifies it to a CMOS level and latches it, and a slave latch circuit that takes in the output of the master latch circuit according to the clock signal. An ECL-CMOS level conversion circuit characterized by being provided. 2. The EC according to claim 1, further comprising a differential amplifier circuit which takes in an ECL level signal, differentially amplifies it, and outputs the first signal and the second signal.
L-CMOS level conversion circuit. 3. A differential amplifier circuit which takes in an ECL level signal and differentially amplifies it, and an emitter follower which current-amplifies the differential output of the differential amplifier circuit and outputs the first and second signals. An ECL-CMOS level conversion circuit, further comprising a type buffer circuit.