JPH06120009A - Capacitive varistor - Google Patents

Abstract

PURPOSE:To accomplish a capacitive varistor, having large capacitance, which can cope with surface mounting. CONSTITUTION:In a capacitive varistor 1, two varistor elements 2 and 2, on which electrodes 4a and 4b are formed, are laminated on both main surfaces of a semiconductor substrate 3, and the connection parts 5a, 6a and 6b of input- output terminals 5 and 6 are connected to the above-mentioned electrodes 4a and 4b in such a manner that each varistor element 2 is electrically connected in parallel. Also, each varistor element 2 is coated with a sheathing resin 7, and at the same time, the lead-out parts 5b and 6c of the input-output terminals 5 and 6 are exposed to the outside surface 7a of the sheathing resin 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive varistor having a capacitor function and a varistor function, and more particularly to a structure which can obtain a large electrostatic capacity in a compact size and can be mounted on a surface.

[0002]

2. Description of the Related Art Generally, a capacitive varistor made of a semiconductor ceramic containing SrTiO ₃ as a main component has a function as a capacitor as well as a function as a varistor for absorbing surges and noises. Widely used. Conventionally, this capacitive varistor has a structure in which electrodes are formed on both main surfaces of a semiconductor substrate, input / output terminals are connected to the respective electrodes, and the outer surface of the substrate is covered with an exterior resin. Varistor characteristics and capacitor characteristics have been obtained at the grain boundaries of semiconductor ceramics. Therefore,
The number of grain boundaries of the semiconductor ceramic is controlled to control the varistor voltage and electrostatic capacitance.

[0003]

However, in the conventional capacitive varistor described above, in order to obtain a large capacitance, the electrode area of the semiconductor substrate must be increased,
There is a problem that the outer diameter dimension of the component is increased accordingly. Such a component having a large outer diameter cannot support surface mounting for facilitating the assembly of electronic components in recent years, and improvement in this respect is required.

The present invention has been made in view of the above conventional circumstances, and provides a capacitive varistor capable of increasing electrostatic capacitance in a compact size without increasing the electrode area and capable of supporting surface mounting. It is an object.

[0005]

Therefore, according to the present invention, a plurality of varistor elements having electrodes formed on both main surfaces of a semiconductor substrate are laminated, and the connection portions of input / output terminals are electrically parallel to each other. Is connected to each of the electrodes so that the varistor element is covered with an exterior resin, and the lead-out portion of the input / output terminal is exposed on the outer surface of the exterior resin.

[0006]

According to the capacitive varistor of the present invention, a plurality of varistor elements are laminated and integrated, and the input / output terminals are connected so that the respective elements are electrically parallel to each other, and the varistor element is covered with the exterior resin. Since the lead-out portion of the input / output terminal is exposed on the surface of the exterior resin while covering, the component can be configured in a compact size as compared with the conventional case where the electrode area is increased. As a result, a large capacitance can be easily obtained without increasing the electrode area, and surface mounting can be supported, and the above-mentioned requirements can be met.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are views for explaining a capacitive varistor according to an embodiment of the present invention. In the figure, reference numeral 1 is a capacitive varistor of this embodiment, which is formed by superposing two varistor elements 2 and 2. Each varistor element 2 is formed by forming electrodes 4a and 4b on the front and back surfaces of a disk-shaped semiconductor substrate 3, respectively.
The electrodes 4b and 4a of the lower varistor elements 2 and 2 face each other.

The varistor element 2 is connected to a plate-shaped input / output terminal 5 extending straight and an input / output terminal 6 bent in a bifurcated shape. The two input / output terminals 5 and 6 are formed by punching a hoop material with a die, and the terminals 5 and 6 face each other. The one input / output terminal 6 is formed by bending a central portion of the input / output terminal 6 upward in a stepped manner and bending both end portions of the input / output terminal 6 downward in a stepwise manner, whereby bifurcated connecting portions 6a and 6b are formed.

The connection portion 5a of the other input / output terminal 5 is sandwiched between the electrodes 4b, 4a of the varistor element 2 facing each other, and is soldered to the electrodes 4b, 4a. The upper connection portion 6a of the one input / output terminal 6 is soldered to the front surface electrode 4a of the upper varistor element 2, and the lower connection portion 6b is soldered to the back surface electrode 4b of the lower varistor element 2. It is connected. As a result, the varistor elements 2 are electrically connected in parallel.

An exterior resin 7 is formed on the outer surface of each varistor element 2 to cover the input / output terminals 5 and 6.
The lead-out portions 5b and 6c of No. 2 are projected outward. Resin 7
Is formed by being immersed in a resin bath and then cured. The lead-out portions 5b and 6c are bent along the side surface 7a of the exterior resin 7, whereby the lead-out portions 5b and 6c are exposed on the side surface 7a of the exterior resin 7.

Next, the function and effect of this embodiment will be described. In order to manufacture the capacitive varistor 1 of this embodiment, each varistor element 2 is assembled to each input / output terminal 5, 6 punched from a hoop material, and each electrode 4 of the element 2 and each terminal 5, 6 are assembled. The connection portions 5a, 6a, 6b are connected by soldering. In this state, a resin is molded on the surface portion of the varistor element 2 and cured to form the exterior resin 7. Thereafter, unnecessary portions of the input / output terminals 5 and 6 protruding from the exterior resin 7 are cut to form lead portions 5b and 6c, and the lead portions 5b and 6c are formed on the side surface 7a of the exterior resin 7. Fold along. As a result, a chip component compatible with surface mounting is manufactured.

According to this embodiment, two varistor elements 2 electrically connected in parallel are stacked and integrated, and each element 2 is covered with the exterior resin 7 and the side surface 7 of the exterior resin 7 is covered.
Since the lead-out portions 5b and 6c of the input / output terminals 5 and 6 are exposed at a, it is possible to obtain a large capacitance with a compact size. As a result, it is possible to avoid an increase in size as compared with the conventional case where the electrode area of the semiconductor substrate is increased, and it is possible to improve the strength of the component against impact or the like. Further, in this embodiment,
The structure in which a plurality of varistor elements 2 are stacked and integrated with the exterior resin 7 can reduce the mounting space and the number of mounting steps as compared with the conventional mounting of a plurality of varistor elements one by one. it can. Further, in this embodiment, the lead-out portions 5b and 6c of the input / output terminals 5 and 6 are exposed on the side surface of the exterior resin 7, so that recent surface mounting can be accommodated and the above-mentioned requirements can be met.

In the above embodiment, the input / output terminals 5 and 6 are
The case where the lead-out portions 5b and 6c of No. 3 are exposed to the side surface 7a of the exterior resin 7 has been described as an example, but the present invention is not limited to this. For example, as shown by the chain double-dashed line in FIG. 2, the lead-out portions 5b and 6c of the terminals 5 and 6 are slightly extended to form extension portions 8a and 8b, and the extension portions 8a and 8b are connected to the exterior resin 7. The extension portions 8a and 8b may be bent along the bottom surface 7c or may be bent outward from the bottom surface 7c so as to project.

In the above embodiment, the case where two varistor elements 2 are stacked has been described as an example, but the present invention is not limited to this, and three or more varistor elements may be stacked. . FIG. 3 is an example in which three varistor elements 2 are stacked to form a capacitive varistor 10. In this example, each of the input / output terminals 5 and 6 is formed into a bifurcated shape, and each lead-out portion thereof is connected so that the varistor elements 2, 2 and 2 are electrically parallel to each other. Larger varistor voltage and capacitance can be obtained.

The capacitive varistor 15 shown in FIG. 4 is an example in which four varistor elements 2 are stacked, and in this case as well, the input / output terminals 5 and 6 are connected so that the varistor elements 2 are electrically parallel. By doing so, a larger capacitance can be obtained.

[0016]

As described above, according to the capacitive varistor of the present invention, a plurality of varistor elements are laminated and the input / output terminals are connected so that the respective elements are electrically parallel to each other, and Since the lead-out portions of the input / output terminals are exposed on the surface of the exterior resin while being covered with the exterior resin, a large capacitance can be obtained in a compact size, and a chip component compatible with surface mounting can be obtained. is there.

[Brief description of drawings]

FIG. 1 is a perspective view showing an intermediate product for explaining a capacitive varistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of the capacitive varistor of the above embodiment.

FIG. 3 is a schematic diagram showing a capacitive varistor according to a modification of the above embodiment.

FIG. 4 is a schematic diagram showing a capacitive varistor according to another modification of the above embodiment.

[Explanation of symbols]

 1, 10 and 15 Capacitive varistor 2 Varistor element 3 Semiconductor substrate 4 Electrodes 5 and 6 I / O terminals 5a, 6a and 6b Connection part 5b and 6c Derivation part 7 Exterior resin

Claims (1)

[Claims] 1. A plurality of varistor elements having electrodes formed on both main surfaces of a semiconductor substrate are stacked, and a connecting portion of an input / output terminal is connected to each electrode so that the varistor elements are electrically parallel to each other. Then, the capacitive varistor is characterized in that the varistor element is covered with an exterior resin and the lead-out portion of the input / output terminal is exposed on the outer surface of the exterior resin.