JPH06111019A - Image processing device - Google Patents

Abstract

(57) [Summary] [Purpose] It is possible to reliably detect an identification code added in a yellow dot in an input image. [Structure] The additional pattern image correction circuit includes a dot determination unit 5
A region of a predetermined color component is determined based on the input color image data at 01, and the color image data of the determination region is changed by the OR circuits 504 to 506.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, for example, an image processing apparatus having a function of detecting a specific pattern.

[0002]

2. Description of the Related Art It has been proposed to add an identification code (for example, equipment number) to a copy image in order to prevent abuse of a copy. This method has a drawback that the image quality of the copy is deteriorated because an image which is not in the original document is added to the copy.

Therefore, it has been proposed to add a yellow dot code to an image signal by taking advantage of the fact that the yellow pattern is difficult to be recognized by human eyes.

[0004]

However, in the above conventional example, when the pattern is added to the original,
Alternatively, when a simulated pattern exists, the pattern already added to the original and the newly added pattern are mixed on the copy, which makes it difficult to determine the identification code such as the equipment number. was there.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object thereof is to provide an image processing apparatus capable of detecting a pattern indicating a device number or the like. .

[0006]

[Means for Solving the Problems]
In order to achieve the object, the image processing apparatus according to the present invention determines, from input image data, an identification pattern that is combined with an image represented by the input image data and that is represented by a combination of a plurality of dots. And a removing unit that removes the identification pattern detected by the determining unit from the image.

[0007]

According to this structure, the judging means judges what is expressed by a combination of a plurality of dots, and the removing means removes the identification pattern detected by the judging means from the image.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In the following embodiments, an example of a copying machine is shown as an application example of the present invention, but the present invention is not limited to this, and it is needless to say that it can be applied to various other apparatuses. In addition, each device to which the present invention can be applied is
To prevent counterfeiting, specific documents such as banknotes and securities are made symmetrical. <First Embodiment> FIG. 2 is a side sectional view showing an example of a copying machine to which an image processing apparatus according to the first embodiment of the present invention is applied. In FIG. 2, an image scanner unit 201 is a unit that reads a document and performs digital signal processing. A printer unit 202 is a unit that prints out an image corresponding to the original image read by the image scanner unit 201 on paper in full color.

In the image scanner unit 201, 20
Reference numeral 0 denotes a mirror surface pressure plate, which is a platen glass (hereinafter referred to as “platen”).
The original 204 on the 203 is illuminated by the lamp 205, guided to the mirrors 206, 207, 208, and the lens 2
3-line sensor (hereinafter referred to as "CCD") 2 by 09
An image is formed on 10 and full-color information is provided as a signal processing unit 211 as red (R), green (G), and blue (B) components.
Sent to. Note that 205 and 206 are speeds v, and
7, 208 scans the entire surface of the original by mechanically moving in the direction perpendicular to the electrical scanning direction of the line sensor at 1/2 v. The signal processing unit 211 electrically processes the read signal, decomposes it into magenta (M), cyan (C), yellow (Y), and black (Bk) components, and sends them to the printer unit 202. Further, for each document scanning (scanner) in the image scanner unit 201, M, C,
One component of Y and Bk is sent to the printer unit 202, and a total of four document scans completes one printout.

The M, C, Y or Bk image signal sent from the image scanner unit 201 is sent to the laser driver 212. The laser driver 212 modulates and drives the semiconductor laser 213 according to the image signal. The laser light is a polygon mirror 214, an f-θ lens 215, and a mirror 2.
The photosensitive drum 217 is scanned via the image pickup device 16. A rotary developing device 218 includes a magenta developing unit 219, a cyan developing unit 220, a yellow developing unit 221, and a black developing unit 22.
2 and four developing devices are alternately arranged on the photosensitive drum 21.
7, the electrostatic latent image formed on the photosensitive drum 217 is developed with toner. A transfer drum 223 winds the paper fed from the paper cassette 224 or 225 around the transfer drum 223, and transfers the image developed on the photosensitive drum 217 to the paper.

After the four colors of M, C, Y and Bk are sequentially transferred in this manner, the paper passes through the fixing unit 226 and is discharged. Figure 3 shows CCD (R) 301 and CCD
It is a figure showing relative sensitivity according to a wavelength of light of (G) 302 and CCD (B) 303. FIG. 4 is a block diagram illustrating the configuration of the image scanner unit 201 shown in FIG. In the figure, reference numeral 316 is a counter, which is a line sensor 301 to 30 constituting the above-mentioned three-line sensor 210.
Main scan address 102 for specifying the main scan position for 3
Is output. That is, when the horizontal synchronizing signal Hsync is "1", it is set to a predetermined value by the CPU (not shown) and incremented by the clock signal CLK to the pixel.

The image formed on the three-line sensor 210 is photoelectrically converted by the three line sensors 301 to 303, and amplifiers 304 to 306 and a sample hold circuit are provided as read signals of R component, G component and B component, respectively. 307 to 309 and A / D converters 310 to 312, each color 8-bit digital image signal 313 (corresponding to R), digital image signal 314 (corresponding to G),
The digital image signal 315 (corresponding to B) is output.

FIG. 1 is a block diagram showing the configuration of the signal processing unit (image processing unit) 211 shown in FIG. In the figure, reference numeral 204 is a document, 101 is an additional pattern image correction circuit, 102 is a pattern addition circuit, 103 is a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), and a clock (CLK) signal is generated and output. Control unit,
Reference numeral 402 is a color signal processing unit, 104 is a CPU for controlling the entire apparatus, 104a is a ROM storing a program for operating the CPU 104, and 104b is a RAM used as a work area of each block in the ROM.

Next, the operation of the above signal processing section 211 will be described. The color image signals (R, G, B) read by the image scanner unit 201 are input to the additional pattern image correction circuit 101. The additional pattern correction circuit 101 determines a light yellow character and removes it from the image signal. The color signal processing unit 402 generates a print cutter signal (Y, M, C, K) from the input color (R, G, B) signals.

The pattern adding circuit 102 adds the equipment number to the image signal at the time of yellow printing. The control unit 103 is a circuit unit that generates a synchronization signal. Vsyn
The c signal is a sub-scanning section signal, which is a signal indicating the sub-scanning image output section. The Hsync signal is a main scanning synchronization signal and is a signal for synchronizing the start of main scanning. CLK is a basic clock for image processing.

The CPU 104 is a microprocessor and outputs the frame sequential signal CNO shown in FIG. The laser color printer used in this embodiment prints in the order of M (magenta), C (cyan), Y (yellow), and Bk (black). The frame sequential signal CNO is a signal indicating the print color currently printed. Figure 5
FIG. 3 is a circuit block diagram of an additional pattern image correction circuit 101. In the figure, 501 is a dot determination unit, 502 is a color determination unit, 503 is a NAND circuit, and 504 to 506 are O.
R circuits and 507 to 510 respectively indicate line buffers for one line delay.

Next, the operation of the additional pattern image correction circuit 101 will be described. The dot determination unit 501 determines whether or not the pixel has an isolated dot shape as shown in FIG. The color determination unit 502 determines whether or not the pixel is light yellow. The outputs of the dot determination unit 501 and the color determination unit 502 are ANDed by a NAND 503 and the output signal is inverted.
The R circuits 504, 505, and 506 perform a logical sum operation with the R, G, and B color signals. As a result, when the pixel is light yellow and is a dot portion, the pixel is white (R = 255, G = 255, B = 255), and when not, the image signal is output without being changed.

FIG. 6 is a block diagram showing the configuration of the color determination unit 502. In the figure, 601 is a Lab conversion circuit,
Reference numerals 602 and 604 are comparators for comparing different threshold values C0 and C1 with L, 603 is a look-up table (hereinafter referred to as “LUT”), and 605 is an AND circuit. Next, the operation of the color determination unit 502 will be described.

The Lab conversion circuit 601 has inputs R, G, and B.
3 × for converting a signal into a luminance signal L and color component signals a and b
3 is the product-sum calculator. The comparison calculators 602 and 604 are
The luminance signal L has a predetermined value range (C0 <L <C
It is determined whether it is in 1). The LUT 603 is a ROM memory and outputs “1” when the color component signals a and b are in a specific value range, that is, a yellow component, and outputs “0” otherwise.

FIG. 7 is a block diagram showing the structure of the dot judgment unit 501, and FIG. 8 is a diagram showing a matrix for explaining the operation of the dot judgment unit 501. In FIG. 7, 7
Reference numeral 01 is a dot determination unit, 702 and 703 are pixels, a line buffer for performing line delay, and 704 is a frequency dividing circuit, which divides the horizontal synchronizing signal 704 by 4 to generate an HS4 signal.

In order to detect yellow dots, the judging section 501 uses a B signal having high sensitivity for a yellow image,
The dot part is extracted. The frequency divider circuit 704 and the HS4 signal 106 and CLK generated by the frequency divider circuit 911 shown in FIG.
By controlling the circuit of the dot determination unit 501 with the four signals 912, the interval between the pixel I and the surrounding pixels shown in FIG.

FIG. 21 shows Hsync, HS4 and CLK.
And FIG. 11 is a diagram showing a mutual relationship between CLK4 and CLK4, and FIG. 11 is a diagram illustrating an example of an additional pattern of the present embodiment. Figure 1
1, the 4 × 4 pixels included in the region 1301 are modulated such that the gradation of the image signal is + α,
The 2 × 4 pixels included in the regions 1302 and 1303 are modulated so that the gradation of the image signal becomes −α, for example, and the pixels outside the regions 1301 to 1303 are not modulated. The 8 × 4 pixels included in the areas 1301 to 1303 are set as unit dots of the additional pattern.

12 and 13 are views showing an example of the add-on line of this embodiment. In FIG. 12, 1401 is an add-on line having a width of, for example, 4 pixels. 1401
Each of a to 1401e is a unit dot shown in FIG. 11, and is, for example, 8 × 4 pixels. Unit dot 1401a-
1401e is d1 (for example, 128 pixels) in the main scanning direction.
Are lined up in a substantially constant cycle.

Further, in FIG. 13, 1501 to 15
Reference numeral 10 denotes an add-on line, which has a width of, for example, 4 pixels, and is arranged in the sub-scanning direction at a substantially constant period of d2 (for example, 16 pixels). Although details will be described later, for example, one add-online represents 4-bit information, and
~ 1509 8 add-on lines as a set 3
Two bits of additional information can be represented. The add-on line is repeatedly formed in the sub-scanning direction.
The add-on lines 1501 to 1509 shown in 3 represent the same information.

14 and 15 show an example of a method of expressing information by add online. In FIG. 14, 1
601 and 1602 are add-on lines, and both add-on lines are adjacent to each other in the sub-scanning direction. Also, 1601a, 1
601b and 1602a are unit dots, and in order to prevent adjacent unit dots of adjacent add-on dots from approaching and conspicuous, adjacent add-on line unit dots are separated by at least d3 (for example, 32 pixels) in the main scanning direction. Set to open.

The data represented by the unit dot is determined by the phase difference between the unit dot 1602a and the unit dot 1601a. Although FIG. 14 shows an example showing 4-bit information, in FIG.
02a represents the data "2". For example, if the unit dot 1602a is at the leftmost end, data "0" is represented, and if the unit dot 1602a is at the rightmost end, data "F" is represented.

In FIG. 15, of the set of add-on lines representing all the additional information, FIG. 15A shows the first add-on line Line0, and FIG. 15B shows the fourth add-on line Line3. As shown in FIG. 15, Line
In 0, dots 1702a to 1702d are added to the right side of all the original unit dots 1701a to 1701d at intervals of d4 (for example, 16 pixels), and in Line 3,
On the right side of all the original unit dots 1704a to 1704d, dots 1705 are arranged at an interval of d5 (for example, 32 pixels).
a to 1705d are added. This additional dot
Each ad online is a marker for clarifying the number of the ad online. The reason why the markers are added to the two add-on lines is that the upper and lower sides in the sub-scanning direction can be determined even from the output image.

Further, for example, the pattern to be added is added only with the Y toner by utilizing the fact that the human eye has a low discrimination ability with respect to the pattern drawn with the Y toner. Also, the dot spacing in the main scanning direction of the additional pattern,
The repeat interval of all additional information in the sub-scanning direction must be determined so that all information can be reliably added to a thin and uniform area where dots can be surely identified in a specific original document. . As a guide, information may be added at a pitch that is ½ or less of the width of a thin and uniform area that allows dots to be reliably identified in the target specific document.

[Pattern Adding Circuit] Next, an example of the pattern adding circuit of this embodiment will be described. 16 and 1
7 and 18 are block diagrams showing a configuration example of the pattern adding circuit 102. In the figure, the sub-scanning counter 181
At 9, the main scanning synchronization signal HSYNC is sent to the main scanning counter 1
At 814, the pixel synchronization signal CLK is repeatedly counted with a 7-bit width, that is, 128 cycles. The AND gate 1820 connected to the outputs Q2 and Q3 of the sub-scanning counter 1819 outputs H when the bit 2 and the bit 3 of the sub-scanning counter 1819 are both H. That is, A
The output of the ND gate 1820 becomes H for a period of 4 lines for every 16 lines in the sub-scanning direction, and this is used as an add-on enable signal.

The gate 1822 inputs the output of the AND gate 1820 and the upper 3 bits (Q4 to Q6) of the sub-scanning counter 1819, and the enable signal LINE0 of the line 0 of the add-on line is supplied to the gate 18
21 generates the enable signal LINE3 of line 3 of add-on line. On the other hand, the main scanning counter 1
Although details will be described later, an initial value is loaded into 814, and the gates 1815 to 1817 input the upper 4 bits (Q3 to Q6) of the main scanning counter 1814. The output of the AND gate 1815 becomes H in the interval of 8 pixels for every 128 pixels, and this is used as the dot enable signal. Further, the gates 816 and 817 are provided in addition to the upper 4 bits of the main scanning counter 814, and the signal LI
NE0 and LINE3 are input to generate enable signals for the marks of line 0 and line 3, respectively. these,
The dot and mark enable signals are OR gates 18.
18 are grouped from 7 and further OR gate 1818
And the output of the AND gate 1820 are logically ANDed by the AND gate 824 and become the dot and mark enable signals which become H only on the add-on line.

The output of the AND gate 1824 is F / F1.
At 828, synchronized with the pixel sync signal CLK,
The AND gate 1830 is logically ANDed with the 2-bit output color selection signal CNO. Output color selection signal C
Bit 0 of NO is negated by the inverter 1829 and A
Input to the ND gate 1830 and output color selection signal C
Since bit 1 of NO is directly input to the AND gate 1830, the signal CNO = “10”, that is, the dot and mark enable signal becomes valid when the Y color image is printed.

Further, the output of the AND gate 1824 is
It is also connected to the clear terminal CLR of the counter 1825, and the counter 1825 counts the pixel synchronization signal CLK only when the AND gate 1824 is H, that is, when the add-on dots are enabled, and the counter 1
Bits 1 and 2 of the output of 825 are input to the Ex-NOR gate 1826, and the output of the Ex-NOR gate 1826 becomes L during the period of 4CLK in the middle of the add-on dot period (8CLK). Ex-NOR gate 1
The output of 826 is synchronized with the pixel synchronization signal CLK by the F / F 1827 and is output as the signal MINUS. When the signal MINUS is L, the add-on dots are modulated to + α.

The F / F 1827 is a signal MINUS.
This is for removing the beard of and also for aligning the phase with the enable signal of the add-on dot. Signal MI
NUS is input to the selection terminal S of the selector 1838. The AND section 1832 receives the 8-bit modulation amount α and the output of the AND gate 1830 from the register 1831. At the timing of the add-on dot, the output of the AND gate 1830 becomes H, so A
The ND unit 1832 outputs the modulation amount α at the timing of the add-on dots. Therefore, the pixels other than the add-on dots are not modulated because the modulation amount output from the AND circuit 1832 is 0.

Reference numeral 1833 is an adder and 1835 is a subtractor.
In both cases, for example, an 8-bit image signal V is input to the terminal A. Modulation amount α output from AND section 1832 to terminal B
However, the output of the addition unit 1833 is input to the OR circuit 1834, and the output of the subtraction unit 1835 is input to the AND circuit 1837. The OR circuit 1834 is the addition circuit 18
When the addition result V + α of 33 overflows and the carry signal CY is output, the calculation result is forcibly set to 255, for example. When the subtraction result V-α of the subtraction circuit 1835 underflows and the carry signal CY is output, the AND circuit 1837 forces the carry signal CY inverted by the inverter 1836 to force the operation result to, for example, 0. It is something to do.

Both calculation results V + α and V−α are obtained by the selector 1
838, and is output from the selector 1838 according to the signal MINUS. With the above circuit configuration, the dot modulation shown in FIG. 11 is performed. The value to be loaded into the main scan counter 1814 is generated as follows. First, the F / F 181 is set by the sub-scanning synchronization signal VSYNC.
3 and the counter 1809 are reset, the initial value of the main scanning counter 1814 is set to 0 in the first add-on line.

Here, the counter 1809 and the F / F 181
The signal ADLIN input to the clock terminal No. 3 of the AND gate 182 is an add-on enable signal.
The output of 0 is output by the F / F 1823 to the main scanning synchronization signal HSYNC.
This signal is synchronized with C. The selector 1810 is responsive to, for example, a 3-bit signal input to the select terminal S,
For example, one of the registers 1801 to 1808 in which the 4-bit value of each of the eight add-on lines is set is selected, and the value set in the selected register is output.

The select signal of the selector 1810 is generated by the counter 1809 which counts the signal ADLIN. At the first add-on timing, the count 1809 is cleared by the sub-scanning synchronization signal VSYNC, so the select signal is 0. Therefore, the selector 1810 selects the register 1801. Then, when the signal ADLIN rises, the count value of the counter 1809 advances by 1, and the selector 1810 causes the register 1
Select 820. After that, the selector 1810 outputs the signal A
Registers 1803 to 18 sequentially in synchronization with DLIN
The selection of 08 is repeated.

The output of the selector 1810 is the adder 181.
In 1, the sum is added to the output of the adder 1812, and the F / F181
3 and is latched at the falling edge of the signal ADLIN,
It is input to the main scanning counter 1814. In addition, F / F1
The output of 813 is sent to the main scanning counter 1814 and also to the terminal B of the adder 1812, and is added to the constant value, for example, 8 input to the terminal A of the adder 1812, and sent to the adder 1811. To be This is an offset value for making a gap between the dot position of the add-on line and the dot position of the add-on line one line before in the sub-scanning direction.

[Copy Result] FIG. 19 is a diagram showing an example of the copy result according to this embodiment, but shows only an example of the arrangement of the unit dots of the add-on line. In FIG. 19, 19
01 is, for example, a specific document image. Also, the unit dots of add-on line are represented by black squares.

As described above, according to the first embodiment, by detecting the yellow dots from the color input image signal of the original and changing the image data, the dots of the yellow component are added in the output image. The identification information to be obtained can be surely added. Second Embodiment Now, in the first embodiment,
The thin yellow dots in the original were detected and changed to white data. With the method of the first embodiment, it is possible to ensure the reading of the yellow dot code in the copy image. However, depending on the input original, a dot-shaped blank area may occur in the copy image. .

Therefore, in the second embodiment, the image data of the yellow dot portion in the original is smoothed and printed, so that it is possible to detect the additional code in the copied image while reducing the image quality deterioration of the copied image. Can be done. Next, a configuration for obtaining the above effects will be described. 22 is a block diagram showing the configuration of an additional pattern image correction circuit according to a second embodiment of the present invention.

In FIG. 22, smoothing circuits 2201-2
Reference numeral 203 denotes a circuit shown in FIG. 23, which smoothes image data. Selector 2208-2210
Is a selector controlled by the determination signal 2210,
When the determination signal 2210 is 0, the smoothed image data is output, and when the determination signal 2210 is 1, the delay circuit 2
The data of 204 to 2206 are output. Reference numeral 2207 is a determination signal delay circuit.

The above delay circuits 2204 to 2206 and
The determination signal delay circuit 2207 constitutes a delay circuit for smoothing and matching the phases of the image data and the signal. In FIG. 23, a typical configuration of the smoothing circuits 2201 to 2203 is a D-type flip-flop 2301.
2304 and an arithmetic circuit 2305. <Third Embodiment> FIG. 24 is a block diagram for explaining the third embodiment of the present invention. In the present embodiment, not only the yellow pattern is added by the pattern adding circuit 102 as in the second embodiment, it is further determined whether or not the input original image is a specific original (for example, banknote). If the original is determined to be a specific original, the determination signal is sent to the printer unit 202, and when the CNO signal is 3 (black image formation), the solid signal is converted into an image signal. It is designed to be synthesized. Here, the determination circuit 3501 makes a determination by, for example, previously examining the tint distribution of the specific document and comparing this tint distribution with the tint distribution of the input image. The other structure is similar to that of the second embodiment. According to the present embodiment, when the yellow pattern is added as described above, it is possible to prevent the pattern from being difficult to see due to the mixture of the original pattern and the newly added pattern, and to add the additional pattern image correction circuit. Since the determination circuit 3501 performs determination based on the image signal smoothed by 101, the determination accuracy is improved. The present invention may be applied to a system including a plurality of devices or an apparatus including one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

In each of the above-mentioned embodiments, the laser beam printer has been described as an example, but the present invention is not limited to this, and can be applied to an ink jet printer and a thermal transfer printer. In particular, a so-called bubble jet type printer that uses a head that ejects droplets by utilizing film boiling due to thermal energy may be used. Further, in each of the above-described embodiments, the color to be added is yellow, but the present invention is not limited to this, for example, an inconspicuous color such as yellow-green or gray, or lightness such as light purple or light green. It may be color.

Further, in each of the above-described embodiments, the original image is input by the image scanner unit, but the present invention is not limited to this, and a still video camera, an input by a video camera, and a computer graphic. It may be created by the user.

[0046]

As described above, according to the present invention,
It is possible to reliably detect the identification information added by the predetermined dots in the input image.

[Brief description of drawings]

FIG. 1 is a signal processing unit (image processing unit) shown in FIG.
2 is a block diagram showing the configuration of 211. FIG.

FIG. 2 is a side sectional view showing an example of a copying apparatus to which the image processing apparatus according to the first exemplary embodiment of the present invention is applied.

FIG. 3 CCD (R) 301, CCD (G) 302, C
It is a figure showing the relative sensitivity according to the wavelength of the light of CD (B) 303.

4 is a block diagram illustrating a configuration of an image scanner unit 201 shown in FIG.

5 is a circuit block diagram of an additional pattern image correction circuit 101. FIG.

FIG. 6 is a block diagram showing a configuration of a color determination unit 502.

7 is a block diagram showing a configuration of a line drawing determination unit 501. FIG.

FIG. 8 is a diagram illustrating an operation of a line drawing determination unit 501.

9 is a block diagram showing a configuration of a dot detection circuit 701. FIG.

FIG. 10 is a block diagram showing a configuration of a dot detection circuit 701.

FIG. 11 is a diagram illustrating an example of an additional pattern according to the first embodiment.

FIG. 12 is a diagram showing an example of an add-on line according to the first embodiment.

FIG. 13 is a diagram illustrating an example of an add-on line according to the first embodiment.

FIG. 14 is a diagram showing an example of a method of expressing information by add online according to the first embodiment.

FIG. 15 is a diagram showing an example of an information expressing method by add online according to the first embodiment.

FIG. 16 is a block diagram showing a configuration example of a pattern adding circuit according to the first embodiment.

FIG. 17 is a block diagram showing a configuration example of a pattern adding circuit according to the first embodiment.

FIG. 18 is a block diagram showing a configuration example of a pattern adding circuit according to the first embodiment.

FIG. 19 is a diagram showing an example of a copy result according to the present embodiment.

FIG. 20 is a diagram illustrating a frame sequential signal CNO.

FIG. 21 is a timing chart related to frequency dividing circuits 911 and 704.

FIG. 22 is a block diagram showing the configuration of an additional pattern image correction circuit 101 according to the second embodiment.

FIG. 23 is a block diagram showing a typical configuration of smoothing circuits 2201 to 2203.

FIG. 24 is a block diagram illustrating a third embodiment of the present invention.

[Explanation of symbols]

 101 additional pattern image correction circuit 102 pattern addition circuit 103 control unit 104 CPU 104a ROM 104b RAM 201 image scanner 202 printer 200 mirror surface plate 203 platen 204 original document 205 lamp 206, 207, 208 mirror 209 lens 210 CCD 211 signal processing unit 212 laser driver 213 Semiconductor laser 214 Polygon mirror 215 f-θ lens 216 Mirror 217 Photosensitive drum 218 Rotational developing device 219 Magenta developing part 220 Cyan developing part 221 Yellow developing part 222 Black developing part 223 Transfer drum 224, 225 Paper cassette 226 Fixing unit 301-303 Line sensor 304 to 306 Amplifier 307 to 309 Sample and hold circuit 310 to 312 A / D converter 316 counter 402 color signal processing unit

[Procedure amendment]

[Submission date] August 6, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 23

[Correction method] Change

[Correction content]

FIG. 23

Claims (3)

[Claims] 1. A determination unit that determines, from input image data, an identification pattern that is combined with an image represented by the input image data and that is expressed by a combination of a plurality of dots; An image processing apparatus comprising: a removing unit that removes the detected identification pattern from the image. 2. The determining means includes a detecting means for detecting a dot shape of a predetermined color component.
The image processing device described. 3. The image processing apparatus according to claim 1, further comprising a synthesizing unit for synthesizing a predetermined identification pattern with the image from which the identification pattern has been removed.