JPH06119303A - Loosely coupled multiprocessor system - Google Patents

Abstract

(57) [Summary] [Purpose] A master processor can restart a slave processor that has fallen into a failure that cannot be recovered autonomously, and improves the system operation rate. Structure: In addition to a data passing bus 10 for data communication, reset signal lines 12-2 to 12-n are provided. The master processor 11-1 monitors the operating states of the plurality of slave processors 11-2 to 11-n by passing a message such as a survival confirmation message, and resets the slave processors when no response is received from the slave processors. Signal lines 12-2 to 1
The reset signal is transmitted via 2-n. This allows
The failing slave processor is reset and you can try to restart it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loosely coupled multiprocessor system, and more particularly to a loosely coupled multiprocessor system including a master processor and a plurality of slave processors coupled via a data communication bus.

[0002]

2. Description of the Related Art Generally, a loosely coupled multiprocessor system comprises a plurality of processors, which are interconnected via a data passing bus for data communication. In such a loosely coupled multiprocessor system, each processor is operated by an individual operating system. Therefore, even if a certain processor fails due to a hardware or software failure and cannot operate normally, the failed processor can be replaced with another new processor, which allows the loosely coupled multiprocessor system as a whole. The reliability of the operation can be maintained.

The failed processor is found by a monitoring process for detecting whether the processor is operating normally. This monitoring processing is performed by utilizing inter-processor communication based on the message passing method, and specifically, the following two methods are known.

One is a method in which each of the normally operating processors broadcasts a message indicating the normal operation to all the other processors. In this method, since the operating state of each processor is notified to all the other processors, each processor can recognize the operating state of all the other processors, that is, the normal operating state or the faulty state. However, in this monitoring method, a message indicating that the system is operating normally is frequently issued. Therefore, if the number of processors that make up the loosely coupled multiprocessor system is large, the frequent data processing will result in the data processing originally performed by the loosely coupled multiprocessor system. There is a drawback that the function is impaired.

Another monitoring method is a master-slave method in which a plurality of processors forming a loosely coupled multiprocessor system are divided into a master processor and a slave processor, and the master processor monitors the operating states of the plurality of slave processors. . This monitoring method can maintain the original data processing function of the system because the monitoring message does not occur frequently in the multiprocessor system unlike the former method.

Therefore, in a system requiring relatively high speed operation, for example, a loosely coupled multiprocessor system constituting a communication control system such as a digital exchange, the latter master / slave system is used as a monitoring processing system. Is effective.

By the way, each processor is provided with a function of self-detecting and recovering from the failure state, and in the case of a relatively minor failure, it is possible to recover from the failure by autonomously resetting itself. it can. However, depending on the circumstances of the failure, it may not be possible to self-detect and the failure may not be recovered autonomously. In particular, in a processor used in a communication control system such as a digital exchange, such a failure that cannot be self-detected is likely to occur due to noise mixed from a communication line.

For example, a plurality of slave processors are respectively used as exchange modules of a digital exchange,
When the master processor is used as a control module for controlling the exchange modules, a communication line is connected to each exchange module, so that a failure easily occurs in the slave processors constituting the exchange module. When a slave processor experiences such a failure that cannot be detected by itself, the master processor has no way of recovering the slave processor. Operations such as restarting are required. For this reason, failure recovery cannot be performed automatically, and as a result, there arises a problem that the system operation rate is lowered.

[0009]

In the conventional loosely coupled multiprocessor system, when the slave processor cannot autonomously recover from the failure, it is necessary to perform an artificial operation such as restarting the slave processor by the system administrator. As a result, there is a drawback that the system operation rate is lowered.

The present invention has been made in view of the above circumstances, and when a failure occurs such that the slave processor cannot autonomously recover from the failure, the master processor can automatically restart the slave processor. It is an object of the present invention to provide a loosely coupled multiprocessor system capable of improving the system operating rate.

[0011]

Means and Actions for Solving the Problems
In a loosely coupled multiprocessor system composed of a master processor and a plurality of slave processors coupled via a data communication bus, the master processor and the plurality of slave processors are arranged between the plurality of slave processors. A reset signal distribution wiring for distributing a reset signal is provided, and the operating state of each slave processor is monitored by passing messages to and from the slave processor via the data passing bus to the master processor. And a reset signal transmitting means for transmitting a reset signal to the slave processor whose failure is detected by the monitoring means through the reset signal distribution wiring.

In this loosely coupled multiprocessor system, a reset signal distribution wiring is provided in addition to the usual data communication bus. The master processor monitors the operating states of a plurality of slave processors by passing messages such as survival confirmation messages, and, for example, when there is no response from the slave processor, it sends a reset signal to the slave processors via the reset signal distribution wiring. To do. This resets the failing slave processor and attempts to restart it. Therefore, if a slave processor is experiencing intermittent failures, a reset will recover the slave processor from the failure and integrate it into the loosely coupled multiprocessor system, resulting in improved system uptime. be able to.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the system configuration of a loosely coupled multiprocessor system according to an embodiment of the present invention. This loosely coupled multiprocessor system is applied to, for example, a packet switch, and is composed of a plurality of processors 11-1 to 11-n interconnected via a data passing bus 10 for transmitting / receiving message data. There is. These multiple processors (P1 to Pn)
11-1 to 11-n are operated by separate operating systems. The message exchange between the plurality of processors (P1 to Pn) 11-1 to 11-n is performed by using, for example, the CMSA / CD method.

In this case, the processor (P1) 11-1 operates as a master processor that controls the entire system, and the processors (P2 to Pn) 11-2 to 11-n.
The exchange function of is controlled by sending and receiving messages. Each of the processors (P2 to Pn) 11-2 to 11-n operates as a slave processor, is connected to a corresponding communication line, performs an exchange operation between the communication lines, and exchanges with another slave processor. Take action.

The operation monitoring of each processor in this loosely coupled multiprocessor system is realized by the above-mentioned master / slave system. That is, the master processor (P1) 11-1 is connected to the slave processors (P2 to Pn) 11-2 to 11 via the data passing bus 10.
For each of the -n, an inquiry message for existence confirmation is transmitted, and a response message "I am liv" indicating existence is present.
e ”are those slave processors (P2 to Pn) 11-
2-11-n, the slave processors (P2-Pn) 11-2 ...
11-n fault is detected. Further, the master processor (P1) 11-1 has a function of supplying a reset signal to a slave processor which has fallen into a failure that cannot be autonomously recovered and tries to restart the slave processor.

Specifically, the master processor (P1) 1
1-1 is a slave processor (P2 to Pn) 11-2 to 1 to send an inquiry message for confirmation of existence at a fixed time interval.
1-n are sequentially transmitted, and the time from the transmission of the inquiry message to the return of the response message indicating existence is monitored. When the response message indicating the existence is not returned within the fixed period, the master processor (P1) 1
1-1 considers that the slave processor which does not send back the response message has a failure. Then, by further monitoring the time from the time when the failure is detected, it is checked whether a message indicating recovery is transmitted from the slave processor within a certain period, and if there is no recovery message, the slave processor recovers autonomously. It considers that it has fallen into the impossible failure and supplies a reset signal to the slave processor. The supply of the reset signal is performed using the reset signal distributor 13 and the reset signal lines 12-2, 12-3, ... 12-n described below.

That is, the loosely coupled multiprocessor system is provided with reset signal lines 12-1 to 12-n and a reset signal distributor 13. The reset signal lines 12-1 to 12-n are connected to the plurality of slave processors 1
It is a dedicated reset signal distribution wiring arranged to distribute the reset signal to each of 1-2 to 11-n. The reset signal line 12-1 is connected to the slave processor (P2) 11-2 and is used for supplying a reset signal to the slave processor (P2) 11-2. Similarly, the reset signal line 12-2 is connected to the slave processor (P3) 11-3 and is used for supplying a reset signal to the slave processor (P3) 11-3, and the reset signal line 12-n is used. It is connected to the slave processor (Pn) 11-n and is used to supply a reset signal to the slave processor (Pn) 11-n.

The reset signal distributor 13 selectively outputs a reset signal to the reset signal lines 12-1 to 12-n in response to a reset request (reset address, reset trigger signal) from the master processor (P1) 11-1. Send out. Specifically, the reset signal distributor 13 first degodes the reset address from the master processor (P1) 11-1, and selects one of the reset signal lines 12-1 to 12-n according to the degault result. To do. The reset signal distributor 13 is a master processor (P
1) A reset pulse is generated in response to the reset trigger from 11-1, and the pulse is supplied to the selected reset signal line as a reset signal.

FIG. 2 shows an example of a concrete circuit configuration of the reset signal distributor 13. As illustrated, the reset signal distributor 13 includes a decoder 131, a reset pulse generation circuit 132, and AND gates G2 to Gn. An output signal line from the decoder 131 is connected to each first input of the AND gates G2 to Gn, and a reset pulse from the reset pulse generation circuit 132 is commonly supplied to each second input of the AND gates G2 to Gn. To be done. The outputs of the AND gates G2 to Gn are connected to the reset signal lines 12-2 to 12-n, respectively.

When the presence of a slave processor which has fallen into a failure that cannot be recovered autonomously is detected, the master processor (P1) 11-1 sends an address indicating the slave processor and a reset trigger signal to the reset signal distributor 13. Supply. In the reset signal distributor 13,
The decoder 131 is a master processor (P1) 11-1.
The reset address from the reset signal line 12-1 to 12-n 1
AND gate G2 for enabling signal for selecting one
~ Gn. Further, the reset pulse generation circuit 132 generates a reset pulse in response to the reset trigger signal from the master processor (P1) 11-1. This reset pulse is applied to all AND gates G2 to G2.
It is commonly supplied to the second input of Gn.

One of the AND gates G2 to Gn receiving the enable signal supplies a reset pulse to one of the corresponding reset signal lines 12-2 to 12-n as a reset signal. This reset signal is sent to the slave processor which has fallen into a failure that cannot be autonomously recovered. Next, the monitoring processing operation of the loosely coupled multiprocessor system of FIG. 1 will be described with reference to FIG.

The master processor (P1) 11-1 periodically sends an inquiry message for existence confirmation to each of the slave processors (P2 to Pn) 11-2 to 11-n. The slave processors (P2 to Pn) 11-2 to 11-n that are operating normally send a response message "I am Live" indicating that they are alive. In the master processor (P1) 11-1, the time from the transmission of the inquiry message for confirming the existence to the return of the response message indicating the existence of each slave processor (P2 to Pn) 11-2 to 11- Monitored every n.

Whether or not a failure has occurred in each slave processor is detected depending on whether or not a response message indicating existence is returned within the time T1. When the failure of the slave processor is detected, the master processor (P
1) 11-1 removes the faulty slave processor from the system and notifies other slave processors of the faulty slave processor name so that the operation of the entire system is not hindered. Perform processing such as Furthermore, the master processor (P1) 11-
In order to detect whether or not the recovery message is notified within the time T2 from the time of occurrence of the failure, 1 continues the time monitoring of the failed slave processor.

In the slave processor in which a failure has occurred, a function such as a WDT (watchdog timer) function for autonomously detecting the failure and starting itself is operated. If the failure can be recovered autonomously, the WDT function restarts after a certain period of time from the occurrence of the failure. As a result, the slave processor that has returned to the normal operation notifies the master processor (P1) 11-1 of the recovery message. On the other hand, when a failure that cannot be recovered autonomously occurs, self-startup by WDT is not executed.

When the recovery message is notified from the failed slave processor within the time T2, the master processor (P1) 11-1 performs processing such as notifying other slave processors of the recovered slave processor name. , Incorporate the slave processor into the system. Further, when the recovery message is not notified within the time T2, the master processor (P1) 11-1 determines that the failure that the slave processor has fallen into is a failure that cannot be recovered autonomously, and notifies the slave processor. The corresponding address and the reset trigger signal are supplied to the reset signal distributor 13. As a result, the reset signal distributor 1
3 and the corresponding reset signal line, a reset signal is supplied to the slave processor that is in a failure that cannot be autonomously recovered, and a forced restart process is attempted. Then, the master processor (P1) 11-1
Performs the process of incorporating the slave processor into the system when the recovery image is supplied from the slave processor that has fallen into trouble.

As described above, in this embodiment, the reset signal lines 12-2 to 12-n are provided in addition to the data passing bus 10 for data communication. The master processor 11-1 includes a plurality of slave processors 1
The operating states of 1-2 to 11-n are monitored by passing a message such as a survival confirmation message. For example, when there is no response from the slave processor, the slave processor is reset signal lines 12-2 to 12-n. To send a reset signal. This resets the failing slave processor and attempts to restart it. Therefore, if the failure that the slave processor is experiencing is intermittent due to noise, etc., the slave processor can be recovered from the failure by resetting without human intervention, and as a result, the operating rate of the system is improved. Can be made.

[0028]

As described above in detail, according to the present invention,
When a failure occurs such that the slave processor cannot autonomously recover from the failure, the master processor can automatically restart the slave processor, and the system operating rate can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a loosely coupled multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a reset signal distributor provided in the loosely coupled multiprocessor system of the embodiment.

FIG. 3 is a diagram for explaining the flow of operation monitoring processing operation in the loosely coupled multiprocessor system of the embodiment.

[Explanation of symbols]

10 ... Data passing bus, 11-1 ... Master processor, 11-2 to 11-n ... Slave processor, 12
-2 to 12-n ... Reset signal line, 13 ... Reset signal distributor.

Claims (1)

[Claims] 1. A loosely coupled multiprocessor system comprising a master processor and a plurality of slave processors coupled via a data communication bus, wherein the loosely coupled multiprocessor system is arranged between the master processor and the plurality of slave processors. Each slave processor is provided with a reset signal distribution wiring for distributing a reset signal to each of the plurality of slave processors, and by passing a message to and from each of the slave processors via the data passing bus to the master processor. And a reset signal transmitting means for transmitting a reset signal to the slave processor whose failure is detected by the monitoring means through the reset signal distribution wiring. Loosely coupled multi-pro Ssashisutemu.