JPH06102835A - Dot clock phase adjusting device, method thereof and liquid crystal display device - Google Patents

Abstract

(57) [Summary] [Purpose] The phase adjustment of the dot clock, which is necessary when displaying an image of a computer or the like on an LCD monitor, is made non-tone. [Structure] It is assumed that A / D conversion is performed in a mountain portion of a dot clock. When an analog color signal is passed through the differentiator 8, a sharp voltage is generated at the rising and falling edges of the waveform, and the comparator 10
Then, the edge is detected by comparing with the reference voltage 11. The OR circuit 12 ORs the edges. On the other hand, the dot clock generated by the clock generation circuit 5 based on the synchronization signal is delayed by the delay circuit 6 and output from any of the five terminals having different delay times. The AND circuit 13 ANDs the ridges of the edge and the dot clock output, and when these are at the same time, a signal is sent to the counter 15 and the counter 1
Reference numeral 5 increases the count number by 1, and in response to this, the selection switch 7 switches the selection of the output terminal of the delay circuit 6 to the terminal of the next delay time amount. Then, the edge is positioned at the valley of the dot clock waveform and the phase is adjusted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot clock required for displaying an image on a computer or the like in an LCD monitor.

[0002]

2. Description of the Related Art When an LCD monitor is connected to a computer or the like, the output terminals of the computer or the like are analog black and white signals or R, G, B color signals, and horizontal and vertical synchronizing signals. Black and white signal or R,
The G and B color signals must be sampled and A / D converted, and for that purpose, the above-mentioned synchronization signal must be used to generate a dot clock that serves as a sampling timing signal.

That is, as shown in FIG. 3, a dot clock having a period of one pixel is generated from a synchronizing signal obtained from an output terminal of a computer or the like using a dot clock generating circuit 31, and this dot clock is generated. Is input to the A / D converter 32 of, for example, R, G, B color signals obtained from an output terminal of a computer or the like. Since the R, G, and B color signals are signals determined for each pixel, sampling is performed in accordance with the dot clock cycle.

As a result, the number of samplings per time becomes equal to the frequency of the dot clock, the number of samplings per time is reduced, and the operating speed of the electronic component can be slowed down, thus reducing the cost of the electronic component. And power consumption can be reduced.

However, the dot clock has different frequencies and phases depending on the model such as computer, and there are individual differences even within the same model. Further, the computer or the like may output the horizontal synchronizing signal and the color signals of R, G, B, etc. in a phase-shifted state due to the AC power supply voltage, environmental temperature, etc. The phase of the dot clock generated from the generation circuit 31 becomes inappropriate.

If the phase of the dot clock sent to the A / D converter 32 is not appropriate, horizontal image shake (at the 1-dot level) occurs on the LCD screen, so the phase must be adjusted. .

Conventionally, the phase adjustment of this dot clock is
This is done by the user himself moving the adjustment buttons and the like to a position where the image does not shake while looking at the LCD screen.

[0008]

Therefore, when a plurality of computers or the like are switched and used by connecting to the LCD monitor, the user himself / herself moves the adjustment button or the like to switch the phase of the dot clock every time the switching is performed. It had to be adjusted and it was complicated.

Further, even while one computer or the like is connected to the LCD monitor and used, the phase of the dot clock changes due to the AC power supply voltage, the environmental temperature, etc., so that the user must change the adjustment button or the like each time. Move it
The dot clock phase had to be readjusted, which was extremely complicated for the user.

Therefore, an object of the present invention is to provide a dot clock phase adjusting device, a method therefor, and a liquid crystal display device in which the user does not need to adjust the phase of the dot clock.

[0011]

In order to achieve the above object, the dot clock phase adjusting apparatus of the present invention compares a black and white signal or color signal differentiating circuit with a voltage differentiated by the differentiating circuit and a reference voltage. And a phase shift means for comparing the edge detected by the comparison circuit with the phase of the dot clock to correctly adjust the phase of the dot clock. is doing.

In order to achieve the above object, the dot clock phase adjusting method of the present invention differentiates a black and white signal or a color signal, compares the differentiated voltage with a reference voltage,
The edge of the black-and-white signal or the color signal is detected, the detected edge is compared with the phase of the dot clock, and the phase of the dot clock is adjusted correctly.

In the dot clock phase adjusting device, in the case of a color signal, a differentiation circuit and a comparison circuit are formed for each of the three signals of R, G and B.
It is preferable that all the edges of the three G and B signals are detected and summed.

The phase shift means is a dot clock delay circuit having a plurality of different delay time output terminals,
It is preferable that the edge circuit and the dot clock include a counting circuit that counts when peaks or valleys of the dot clock are in the same period, and a selection switch that changes the selection of the output terminal of the delay circuit according to the count number of the counting circuit.

In the liquid crystal display device, the dot clock phase adjusting device and the liquid crystal panel may be inseparably configured.

[0016]

The rising edge and the falling edge of the black-and-white signal or the color signal become sharp voltages by passing through the differentiating circuit. Therefore, by detecting this sharp voltage by comparing it with the reference voltage, Edges are detected. The phase shift means compares the edge and the phase of the dot clock and adjusts the phase of the dot clock correctly, whereby the phase of the dot clock is automatically adjusted.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In the present embodiment, a color image is displayed on an LCD monitor using R, G, B color signals output from a computer or the like. In addition, in this embodiment, A
It is assumed that the / D conversion is performed in the mountain portion (H) section of the dot clock.

In FIG. 1, the A / D conversion device 1 to which the dot clock phase adjusting device of the present invention is applied exists as a separate product, and is provided between a computer or the like (not shown) and the liquid crystal display device 2. Connected.

Analog R, G, and B signals are input to the A / D converter 1 from output terminals of analog R, G, B color signals of a computer or the like. Each of these signals is input to the A / D converter 3, converted into an 8-bit digital signal, and its output terminal is connected to the liquid crystal display device 2.

Next, when a synchronizing signal is input to the A / D converter 1 from an output terminal of the synchronizing signal of a computer or the like, and this signal is directly transmitted to the output terminal and connected to the liquid crystal display device 2. At the same time, part of the sync signal is input to the dot clock generation circuit 5.

The dot clock generated by the dot clock generation circuit 5 is input to the delayed buffer 6. The variable range of the delayed buffer 6 requires a dot clock cycle or more. For example,
When the dot clock is 30 MHz, the dot clock cycle is 1 / (30M) [s] = 33.4 [ns], so the variable range of the delayed buffer 6 is 33.4.
[Ns] or more is required. When connecting to a plurality of computers or the like, the dot clock is selected so that its variable range is equal to or larger than the cycle of the computer having the maximum dot clock cycle. Next, in this embodiment, the delayed buffer 6
Has five output terminals whose delay time increases or decreases with a phase interval width obtained by dividing the variable range into five. The delayed buffer 6 is connected to a selection switch 7 which will be described later, and one of the five output terminals of the delayed buffer 6 is selected by the selection switch 7 and its output is changed to the A / It is input to the D converter 3. The output selected by the selection switch 7 is simultaneously transmitted to the output terminal, and the liquid crystal display device 2
Connected to.

Next, the analog R, G and B signals input to the A / D converter 1 are input to the differentiator 8, respectively. As a result, sharp voltages are obtained at the rising edge portion and the falling edge portion of each signal.

Next, each differentiator 8 is connected to a comparator 10.
Is connected to the reference voltage 11, and a portion larger or smaller than the reference voltage 11 is found, and an edge portion is detected.

The outputs from the respective comparators 10 are input to the OR circuit 12 and the logical sum operation is performed.

The output of the OR circuit 12 is input to the AND circuit 13 together with the dot clock from the output terminal of one delayed buffer 6 selected by the selection switch 7. In the AND circuit 13, when the section of the mountain portion H of the dot clock and the detected edge are at the same time,
Output is done.

Next, the output from the AND circuit 13 is input to the counter 15. The counter 15 has an upper limit of the number of counts, the number of outputs of the selection switch 7, which will be described later, that is,
It is preset corresponding to the number of outputs of the buffer 6.
That is, the upper limit of the number of counts of the counter 15 is set to 5, and after counting up to 5, it returns to the first count of 1. The counter 15 inputs the count number as 3-bit parallel data to the selection switch 7 described later.

The selection switch 7 is an eight-to-one type switch and has eight selection branches, but since the delayed bufferer 6 has five output terminals,
Only five of the selected branches are used. Each time the number of counts sent from the counter 15 increases, the output terminals of the delayed buffer 6 having different delay times are
Sequentially, the delay time is selected to increase or the delay time decreases.

Next, the operation of the present invention will be described with reference to FIGS.

The A / D conversion device 1 is connected between the computer or the like used and the liquid crystal display device 2. When there are a plurality of computers or the like to be used, the changeover switch is used to switch the plurality of computers or the like to the A / D converter 1.
Connect to.

When the liquid crystal display device 2 is operated, the analog R signal, G signal, and B signal (see FIG. 2, hereinafter the same) are input to the differentiator 8, and the edge portion becomes a sharp voltage. The edge timing is detected by the instrument 10 in comparison with the reference voltage. The signal of the edge portion is input to the OR circuit 12 to perform a logical sum, and this signal and the dot clock signal selected by the selection switch 7 are input to the AND circuit 13 to perform a logical product. As a result, during the A / D conversion period
It is determined whether there is no change in the input signal of. If there is a change, this signal is input to the counter 15.

That is, when the phase of the dot clock is incorrect, the signal at the edge portion and the peak portion H of the dot clock signal are at the same time, as shown in FIG. Signal is output from the counter, and the number of the signal is counted by the counter 15.

Then, the counter 15 converts the count number at that time into a binary number and outputs it as 3-bit parallel data to the selection switch 7. Then, the counter 15
Since the count number indicated by the 3-bit parallel data increases by 1 each time the count number of 1 increases, the selection switch 7 has a delay time next larger or next smaller corresponding to this control signal. , Delayed
Select the output terminal of the buffer 6.

The operation in which the counter 15 counts and the selection switch 7 selects the next output terminal of the delayed buffer 6 is R, G during the A / D conversion period (the period where the dot clock is the peak portion H). , B is repeated while there is a change in the input signal.

Then, as shown in (a) of FIG.
When there is no change in the input signals of R, G, and B during the / D conversion period, the signal input from the AND circuit 13 to the counter 15 becomes low as shown in the same manner, and therefore the changeover switch 7 does not change over the switch. After that, the phase of this dot clock is fixed.

As described above, the phase of the dot clock is automatically determined.

Even when the computer is switched to another computer or the like, the phase of the dot clock is automatically adjusted as described above, and while the one computer or the like is used, the AC power supply voltage and the environmental temperature are changed. Etc.
The dot clock phase adjusting device of the present invention immediately and automatically re-adjusts the phase of the dot clock.

As a result, the analog R, G, B color signals are correctly converted into digital signals by the A / D converter based on the dot clock of the correct phase, and input to the liquid crystal display device 2. Therefore, the liquid crystal display device 2 displays a correct color screen without horizontal image shake based on these digital signals and horizontal and vertical synchronizing signals and dot clock signals input from the other terminals. Therefore, the user can always obtain the color liquid crystal display screen in which the image shake does not occur, without adjusting the image by himself.

In the above embodiment, the reference voltage 11 of the comparator 10 is brought sufficiently close to the sharp voltage value obtained by the differentiator 8, or the counter 15 is set to 2.
The signal input to the counter 7 may be reduced and the switching time of the changeover switch 7 may be lengthened by providing a stage configuration or by inserting a one-shot multivibrator in front of the counter 15. As a result, it is possible to sufficiently deal with the case where the response speed of the change in the phase of the dot clock of the delayed buffer 6 is slow.

In the above embodiment, the color image is displayed on the LCD monitor by using the R, G, B color signals output from the computer or the like.
Of course, when a black and white signal output from a computer or the like is used to display on a monochrome LCD monitor, it can be applied by connecting the differentiator 8 and the comparator 10 to the black and white signal.

Further, in this embodiment, the A / D conversion is performed during the period of the mountain portion (H) of the dot clock.
Since the conversion period varies depending on the type of IC and the circuit configuration, the correspondence between the A / D conversion period and the dot clock waveform is determined according to the actual circuit. And in this case,
Instead of the AND circuit 13 of the above embodiment, another logic circuit is constructed. For example, when A / D conversion is performed in the valley (L) period of the dot clock, the dot clock output is invertered and then input to the AND circuit 13.

Furthermore, in the above embodiment, the A / D conversion device 1 to which the dot clock phase adjusting device of the present invention is applied exists as a separate product, and includes a computer (not shown) and a liquid crystal display device 2. I was supposed to be connected between
By incorporating the A / D conversion device 1 into the liquid crystal display device 2,
The A / D conversion device 1 and the liquid crystal panel may be inseparably configured, that is, the A / D conversion device 1 and the liquid crystal panel may be arranged in one housing. As a result, the liquid crystal display device need only be connected to a computer or the like, which facilitates the connection.

Further, although the above embodiment is applied to the digital liquid crystal display device 2, the present invention is applied to an analog liquid crystal display device in which, for example, the sample hold circuit is integrally formed on the substrate of the liquid crystal panel. Is also applicable.

[0044]

Since the present invention is constructed as described above, the phase adjustment of the dot clock is atoned, and even when a plurality of computers or the like are switched and used by connecting to the LCD monitor, the user is required to switch each time. There is no need to adjust the dot clock phase.

Further, while one computer or the like is connected to the LCD monitor and used, even if the phase of the dot clock changes due to the AC power supply voltage, the environmental temperature, etc., the phase of the dot clock can be readjusted. No longer needed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

2A and 2B are timing charts showing the states of signals at respective positions in the block diagram of FIG. 1, where FIG. 2A is a state in which the dot clock phase is correct, and FIG. 2B is an incorrect dot clock phase. Indicates the state.

FIG. 3 is a block diagram of a conventional A / D conversion device.

[Explanation of symbols]

 2 liquid crystal display device 6 delay circuit 7 selection switch 8 differentiating circuit 10 comparing circuit 15 counting circuit

Claims (5)

[Claims] 1. A black / white signal or color signal differentiating circuit, a comparator circuit for comparing the voltage differentiated by the differentiating circuit with a reference voltage to detect an edge of the black / white signal or color signal, and the comparator circuit. 2. A dot clock phase adjusting device comprising: a phase shifter that compares the edge detected by the above with the phase of the dot clock and adjusts the phase of the dot clock correctly. 2. A black-and-white signal or color signal is differentiated, the differentiated voltage is compared with a reference voltage to detect an edge of the black-and-white signal or color signal, and the detected edge and the phase of the dot clock are detected. And a dot clock phase adjusting method for adjusting the dot clock phase correctly. 3. The color signal according to claim 1, wherein each of the three signals of R, G and B comprises the differentiating circuit and the comparing circuit, and the three signals of R, G and B are included. A dot clock phase adjusting device characterized in that all edges of a signal are detected and summed. 4. The dot shift circuit according to claim 1 or 3, wherein the phase shift means has a plurality of different delay time output terminals, the edge and the peak portion of the dot clock, or A dot clock phase adjusting device comprising a count circuit for counting the times when the valleys are in the same period and a selection switch for changing the selection of the output terminal of the delay circuit according to the count number of the count circuit. . 5. A liquid crystal display device, wherein the dot clock phase adjusting device according to any one of claims 1, 3 and 4 and the liquid crystal panel are inseparably configured.