JPH06101726B2 - Clock synchronization circuit - Google Patents

Description

The present invention relates to a clock synchronization circuit, and more particularly to a clock synchronization circuit during demodulation of digital data transmission.

[Conventional technology]

Although a tank circuit or the like is exclusively used for clock synchronization of digital data transmission, the same clock as that of the transmission side is required for reproducing the transmission data on the reception side at the time of synchronization. Therefore, it is common to transmit reference data for clock synchronization for a certain period of time before transmitting data so that the same clock is reproduced on the receiving side.

[Problems to be solved by the invention]

In the above-described conventional clock synchronization, the reference data for clock synchronization is transmitted for a fixed time, and the data is transmitted only after the clock is prepared on the receiving side.
The time taken for the transmitting side to send out the reference data for clock synchronization is a dead time from the viewpoint of information transmission. Therefore, the shorter the time, the better. That is, conventionally, there is a problem that useless reference data is transmitted.

An object of the present invention is to provide a clock synchronization circuit that enables clock synchronization without receiving reference data from the transmission side, which is also called waste information.

[Means for solving problems]

The clock synchronization circuit of the present invention is an interpolation filter that restores the signal waveform by inputting a discrete signal obtained by sampling the signal waveform of the data transmitted at the interval Tb at the interval Ts, and a clock extracted from the restored signal waveform. A clock control circuit that outputs demodulated data by punching the restored signal waveform with a signal, and a memory that stores the N discrete signals sampled at the interval Ts and outputs the stored values in reverse order. A circuit and a switch for changing the connection of the interpolation filter input from the discrete signal input to the storage circuit output;
In step, the discrete signal is inputted to the interpolation filter and N pieces are inputted to the memory circuit, and then the switch is switched to the memory circuit output. At the time of switching by the switch, the difference between the Nth sample timing and the demodulated data output timing. An initial phase difference estimator which outputs a value obtained by dividing the value obtained by adding the interval N · Ts to Ψ modulo the interval Tb as an initial phase difference, and the initial position in the interpolation filter when switching by the switch. And a control circuit for giving the initial phase difference estimated by the phase difference estimator, and the data demodulated in the second step after the switch change is output from the clock control circuit.

[Action]

FIG. 1 is a block diagram for explaining the configuration of the present invention. Initially, the switch 4 is tilted to the 41 side, and when a Ts-synchronized sample value is input from the terminal 100, this input sample value is stored in the memory circuit 3. The sampled value is input to the successive interpolation filter 1, and the signal waveform before sampling is reproduced at the output terminal 300 thereof. This signal waveform is applied to the clock control circuit 2 to synchronize the clock. Although this output is output from the terminal 400, the transmitted data cannot be faithfully reproduced because the phase is not aligned at first. After inputting N sample values sufficient for clock synchronization to be completed by the clock control circuit 2, the switch 4 is switched to the terminal 42 side, and the interpolation filter 1 inputs the value stored from the storage circuit 3. Enter in sequence. At this time, since the demodulated data that is finally interpolated and clock-synchronized and the demodulated data after switching by the switch 4 do not have continuous phases due to the clock initial phase difference and the clock frequency difference, clock synchronization is completed. Nevertheless, the synchronization will be lost after switching. If the clock frequency difference can be ignored, for example, if the clock accuracy is very good or the data length is short, then only the clock initial phase difference becomes a problem. It is difficult to specify the clock frequency difference as the clock initial phase difference, but it can be easily specified when the data length is known.

When N pieces of transmission data at the interval Tb are sampled at the interval Ts,
Letting Ψ be the time difference between the Nth sample time at the Nth time and the demodulated data due to it, Φ is the clock initial phase difference (that is, the time difference between the first sample time and the first demodulated data). It is expressed by the following formula.

Φ = modTb (N · Ts + Y) (1) The modx (y) in the equation (1) is a method (modulo) that represents the remainder when y is divided by x. Here, N, Ts, and Tb are known, and Ψ is the time difference from the input of the Nth sample value to the demodulation data, so it can be easily obtained.
The part that performs this calculation is the initial phase difference estimator 5. Therefore, by changing the phase of the interpolation filter by the control circuit 6 so as to compensate the phase difference calculated by the equation (1) at the time of outputting the demodulated data after the switch 4 is switched, the first step in the second step after the switch 4 is switched. The phases of and become continuous, and the transmission data with the matched clock phase are completely demodulated.

〔Example〕

Next, the present invention will be described in detail with reference to FIGS.

FIG. 2 is a block diagram showing an embodiment of the clock synchronizing circuit of the present invention. As a configuration of the interpolation filter 1 used in this embodiment, there is an interpolation filter described in Japanese Patent Application No. 60-002388.

FIG. 3 is a block diagram showing an example of the interpolation filter in FIG. 2, and FIG. 4 is a block diagram showing an example of the basic interpolation filter in FIG.

In FIG. 3, the interpolation filter 1 includes an input circuit 60 for distributing the input multilevel digital sample value of the terminal 200 to each value,
The basic interpolation filters 50, 57 shown in FIG. 4 and a synthesizing circuit 70 for synthesizing the outputs of the basic interpolation filters 50, 57 are shown.

The clock control circuit 2 may be of various types such as the clock phase control circuit described in Japanese Patent Application No. 58-057529. Further, the memory circuit 3 can be configured by a first-in first-out memory (hereinafter referred to as FIFO).
The initial phase estimator 5 obtains the time (corresponding to the phase difference) Ψ until the clock signal 1002 after the switching signal 1001 is turned on,
Equation (1) is calculated. The control circuit 6 clears the shift register 85 and the binary counter 86 shown in FIG. 4 through the terminal 700 between the input of the value 1003 of the clock initial phase difference Φ and the input of the next clock signal 1002. Then, a control signal for compensating for the initial phase difference is generated. There are two types of control signals, A and B, A = modTs (Φ) (3) The int (x) in the equation (2) indicates the maximum integer that does not exceed x.

Next, formulas (2) and (3) will be described with reference to FIG. FIG. 5 is a diagram showing how control signals are generated at the time of switching in FIG. 2, and when the interval Ts <Tb, the sample value is 1
One or more samples are sampled between symbols. It is assumed that in the first step, up to the sample value a _N is input and the demodulated data Sm in which the clock phase matches is output. The phase difference (time difference) between the sampled value a _N and the demodulated data Sm at this time is Ψ. Here, the switch 4 (illustrated in FIG. 2) is switched from the terminal 41 side to the terminal 42 side. Further, the initial phase difference estimator 5 calculates the equation (1). Initial phase difference Φ of the calculation result
Is the value shown in FIG. This initial phase difference Φ is the initial phase difference from the first sample value a ₁ . However, the address of the binary counter 86 (shown in FIG. 4) in the interpolation filter 1 is operating modulo of the interval Ts. Therefore, when Φ> Ts, this interpolation filter cannot create a phase difference of Ts or more. However, in the case of Φ> Ts, the shift register 87 shifts the sample values by the number of sample values B calculated by the equation (2).
If it is taken in (illustrated in FIG. 4), it can be represented by the phase difference obtained by the expression A shown in FIG. In other words, Φ = B · Ts + A (4) In this way, clearing is canceled by expressing the initial phase difference as shown in equation (4), the shift register 87 is shifted by the number of B, and the binary counter 86 is set to the value of A. , After demodulation data Sm output, interval Tb
After time, demodulation data S ₁ is obtained with the clock phase being synchronized.

〔The invention's effect〕

As described above, when the clock frequency offset can be ignored, the clock synchronization circuit of the present invention can demodulate data without reverse order even if the reference data for clock synchronization added before the normal data is removed. There is.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of a clock synchronization circuit of the present invention, and FIG. 3 shows an example of an interpolation filter in FIG. FIG. 4 is a block diagram, FIG. 4 is a block diagram showing an example of the basic interpolation filter in FIG. 3, and FIG. 5 is a diagram showing how control signals are generated at the time of switching in FIG. 1 ... Interpolation filter, 2 ... Clock control circuit, 3 ...
Storage circuit (FIFO), 4 ... Switch, 5 ... Initial phase estimator, 50, to 57 ... Basic interpolation filter, 60 ... Input circuit, 61 ... Pulse generation circuit, 62 ... Counter, 63 ... … Clock, 70 …… Synthesis circuit, 86 …… Binary counter, 87 ……
Shift register, 88 …… ROM.

Claims (1)

[Claims] 1. An interpolation filter for restoring a signal waveform by inputting a discrete signal obtained by sampling a signal waveform of data transmitted at an interval Tb at an interval Ts, and a clock signal extracted from the restored signal waveform. A clock synchronization circuit composed of a clock control circuit that outputs demodulated data by punching out the restored signal waveform, stores N discrete signals sampled at the interval Ts, and reverses the stored values. , A switch for connecting the interpolation filter input from the discrete signal input to the storage circuit output, and a step of inputting the discrete signal to the interpolation filter in the first step and to the storage circuit. After N switches have been input, the switch is switched to the output of the memory circuit, and at the time of switching the switch, the Nth sample timing and demodulation data output timing are switched. Ringing difference Ψ plus the value of the interval N · Ts and dividing the value obtained by dividing the interval Tb as the initial phase difference estimator, and the internal filter to the internal filter at the time of switching by the switch. A control circuit for providing the initial phase difference estimated by the initial phase difference estimator,
A clock synchronization circuit, wherein the data demodulated in the second step after switching the switch is output from the clock control circuit.