JPH06101691B2 - PLL synthesizer system tuning circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a PLL synthesizer system channel selection circuit particularly suitable for a multi-channel access system transceiver for performing empty channel search.

[Outline of Invention]

The present invention is a synthesizer type tuning circuit configured with a PLL circuit, for example, when scanning a communication channel to select an empty channel, the scan width,
That is, the lock-in time of the PLL circuit is shortened by detecting the control signal having the pulse width corresponding to the jump width of the frequency and switching the characteristic of the PLL loop by this control signal. Therefore, it becomes possible to complete the tuning operation within a predetermined time regardless of the jump width.

[Conventional technology]

For example, in a cellular car phone implemented in the United States, etc., a channel for making a call is designated by a base station for each zone, and an effective channel can be used by using an empty channel in that zone. Has been done.

Therefore, a transceiver equipped with a so-called PLL synthesizer type channel selection circuit is used, and a call is made by a multi-channel access system that searches for an empty channel.

Generally, the basics of the tuning circuit by the PLL synthesizer system are
For example, as shown in FIG. 5, a reference signal source 21, a phase detector
22, low-pass filter 23, variable voltage oscillator (VCO) 24,
It is composed of a frequency dividing circuit 25 and the like. And frequency divider
The output frequency of the VCO 24 is changed by changing the division ratio of 25, and the reception or transmission frequency is set.

At this time, the open loop transfer function of the PLL circuit is G (S) = K _P F
(S) K _V / SN ... It is shown by the equation (1).

However, F (S): Transfer characteristic of low-pass filter K _P : Conversion characteristic of phase detector N: Dividing ratio Also, the PLL circuit changes the dividing ratio of the dividing circuit,
When the oscillation frequency f is changed from f ₁ to f ₂ , for example, the response characteristic has a settling time T _S (lock-in time) that varies depending on the damping coefficient ζ and the natural angular frequency ωn as shown in FIG. Further, in the PLL circuit configured by the same open circuit transfer function, the lock-in time becomes longer as the frequency change of the VCO to be stepped next becomes larger.

Natural angular frequency ωn is 1/2 of loop gain as shown in the following equation.
It is proportional to the power of 2 and inversely proportional to the 1/2 power of the integration time constant CR of the low pass filter.

ωn = (K _P · K _V / CRN) ^1/2 (2) Thus, the lock-in time of the PLL circuit depends on the loop gain, the bandwidth of the loop, the initial operating frequency, etc., and the natural angular frequency ωn Is larger, the lock-in time is shorter, but if ωn is larger, the stability of the PLL circuit becomes worse. Therefore, the natural angular frequency ωn is usually set to an optimum value in terms of stability and responsiveness.

[Problems to be solved by the invention]

However, when searching for an empty channel in a PLL synthesizer channel selection circuit, the larger the number of channels separated from the current channel selected to the empty channel, the longer the lock-in time and the slower the communication start time. There is.

So, in such a PLL synthesizer type tuning circuit,
It has been considered to provide a lock detection circuit separately and reduce the time constant CR of the low-pass filter to shorten the lock-in time until a steady state is reached, but in this case a separate lock detection circuit is required. There is a problem that the circuit becomes complicated.

The present invention has been made to solve such a problem, and in particular, in the case of a tuning operation of a PLL synthesizer system, a PLL that enables access to a designated channel within a predetermined time regardless of the number of jump channels. A synthesizer channel selection circuit is provided.

[Means for solving problems]

FIG. 1 is a block diagram showing an outline of the PLL synthesizer system of the present invention, in which 1 is a tuner 1a and an intermediate frequency amplifier 1
b, a receiver 2 including a demodulator 1c and the like, 2 is a variable voltage oscillator (VCO) for channel selection, and as is well known, a frequency divider 3 and a phase comparator 4 to which a reference signal _fr is input. , PLL (Phased Lock Loo) whose oscillation frequency is controlled by the feedback circuit consisting of low-pass filter 5
p) circuit.

Reference numeral 6 is a control unit for controlling the oscillation frequency of the VCO 5, which sends out a control signal C ₂ for setting the division ratio of the frequency dividing circuit 3 and at the same time closes the switch S of the low pass filter 5 to change the time constant C ₁ Is being sent.

[Action]

When the communication channel is selected, the control signal C ₂ is sent from the control unit 6 and the frequency division ratio of the frequency dividing circuit 3 is set so as to correspond to the channel to be selected.
In the L synthesizer channel selection circuit, the control unit 6 calculates the sag between the frequency of the current communication channel and the frequency of the channel to be selected next (hereinafter referred to as jump frequency or jump width), and the jump frequency The control signal C ₁ having a pulse width corresponding to is supplied to the low-pass filter 5.

Therefore, the switch S of the low-pass filter 5 is closed for a predetermined period to widen the loop band and shorten the lock-in time.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of a PLL synthesizer system tuning circuit of the present invention. As in FIG. 1, 10 is a voltage variable oscillator (VCO) for channel tuning, and 11 is a preset terminal ps. Frequency divider circuit, 12 is a phase comparator to which the reference signal f _r is input, 13 is a low-pass filter that limits the frequency band of the detection signal of the phase comparator 12, a switch S for time constant switching, and a lag lead. It is composed of an amplifier A, resistors R ₀ , R ₁ and R ₂ , a capacitor C and the like which form a type integration circuit.

Reference numeral 14 is a latch circuit for supplying the preset value of the frequency dividing circuit 11, and after the channel selection data output from the control unit 16 is read to the shift register 15 as described later, the channel selection data D Latch signal (L)
Is to be held by.

Reference numeral 17 denotes a system controller (CPU) that controls a channel selection signal of a communication transceiver, and an input key device 18
Command to set the operation mode such as empty channel scan and channel preset, and at the same time read the data for shortening the lock-in time.

Reference numeral 19 is a memory in which predetermined tuning data, data corresponding to the jump frequency described above, and the like are stored.

The operation of the above-described embodiment will be described below with reference to the waveform chart of FIG.

When selecting an empty channel according to a command from the input key device 18 or an external base station, as described above, the tuning data D for receiving the channel from the control unit 16 is serially input to the shift register 15 by the clock signal CLK. Is read as. Then, the latch signal S output after that
The rising edge of (L) loads the latch circuit 14 and presets the tuning data D to the frequency dividing circuit 11.

The PLL circuit is the tuning data D preset in the frequency dividing circuit 11.
Then, the frequency of the voltage variable oscillator 10 is set to a predetermined value.

In this case, according to the embodiment of the present invention, as shown in the waveform diagram of FIG. 3, the latch signal S (L) having the pulse width (T ₁ ) corresponding to the jump frequency of the tuning data D ₁ is output. Controlled as

That is, when jumping from the current tuning channel N ₁ to the next tuning channel N ₁₀ , the latch pulse P ₁ having the pulse width T ₁ corresponding to the 10-channel jump is output to output new tuning data D ₁ . The time constant of the low pass filter is reduced only during the period T ₁ by controlling the switch S of the low pass filter 13 by the latch pulse P ₁ at the same time as presetting in the frequency dividing circuit 11. (R ₀ <R ₁ ) Also, from the currently selected channel N ₁₀ to the next selected channel N
When jumping to ₁₀₀ , latch pulse P ₂ with pulse width T ₂ (T ₂ <T ₁ ) corresponding to 90 channel jump
Is output to preset the new tuning data D ₂ in the frequency divider circuit 11 and the switch S of the low pass filter 13 is controlled by the latch pulse P ₂ to reduce the time constant of the low pass filter 13 only for T ₂ time. Control to be.

Therefore, the higher the jump frequency is, the smaller the time constant is controlled by the latch pulse P that makes the time constant switching time of the low-pass filter 13 longer. It is possible to prevent the intime from becoming long,
For example, 0.1 ms for 10-channel jump, 5 ms for 150-channel jump, 10 m for 300-channel jump
When the latch pulse P of s is supplied, a predetermined time (for example, 15 m
It will be possible to complete the tuning operation within s).

Particularly, in this embodiment, since the pulse width of the latch signal S (L) for latching the tuning data is made variable according to the magnitude of the jump frequency, the latch for latching the tuning data is used. The signal and the control signal for shortening the lock-in time can be shared, and it is not necessary to form the control signal for shortening the lock-in time in another circuit.

In other words, since the latch signal normally required for latching data is used as it is, there is an advantage that the circuit configuration is simplified.

The pulse width T of the latch pulse P does not need to be continuously set corresponding to the jump frequency, and changes stepwise with respect to the jump frequency Δf or the jump channel number ΔN as shown in FIG. 4, for example. You may do it.

The switching for shortening the lock-in time of the PLL circuit is not limited to the time constant of the low-pass filter 13, and, for example, the control sensitivity (K _V ) of the VCO 10 or the conversion gain of the phase comparator 12 as a latch signal as shown by a dashed line. The configuration may be switched according to the pulse width T of S (L).

〔The invention's effect〕

As described above, the PLL synthesizer system tuning circuit of the present invention, when setting the reception frequency or the transmission frequency, the transfer characteristics of the PLL circuit depending on the jump frequency, the number of jump channels, or the size of the jump division ratio. Is controlled so that the lock-in time is shortened by switching for a predetermined time, and therefore the voltage variable oscillator can be locked and stably operated within a predetermined time without providing a lock detection circuit.

Further, there is an effect that the lock-in time of the selected channel can be made almost constant regardless of the jump frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a PLL synthesizer system channel selection circuit of the present invention, and FIG. 2 is a PL which is a main part of the present invention.
FIG. 3 is a block diagram showing an embodiment of an L circuit, FIG. 3 is a waveform diagram of tuning data, a clock signal, and a latch signal, and FIG. 4 is a graph showing the relationship between the pulse width of the latch signal and the jump frequency (the number of channels). 5 is a general explanatory view of the PLL circuit, and FIG. 6 is an explanatory view of the response characteristic of the PLL circuit. In the figure, 1 is a receiving unit, 2 is a voltage variable oscillator (VCO), 3 is a frequency dividing circuit (programmable counter), 4 is a phase comparator, 5 is a low-pass filter, S is a switch for time constant switching, and 6 is a selection. The control part which outputs a station control signal and a control signal for lock-in time reduction is shown.

Claims (1)

[Claims] 1. A voltage-controlled oscillator, a phase comparator,
In a PLL synthesizer type tuning circuit equipped with a low-pass filter and a frequency dividing circuit, the frequency dividing ratio of the frequency dividing circuit is set to a predetermined value in response to a channel tuning control signal, and the initial channel selection is performed. A control unit for outputting a control signal having a pulse width corresponding to the jump width of the frequency and the channel frequency to be selected next is provided, and the loop characteristic is switched by the control signal so that the lock-in time of the PLL loop is shortened. The PLL synthesizer system tuning circuit characterized in that.