JPH06101564B2 - Amorphous Silicon Semiconductor Device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to amorphous silicon semiconductor devices such as thin film transistors.

[Technical background of the invention]

In recent years, as an amorphous silicon semiconductor device, a thin film transistor (hereinafter referred to as TFT) using a semiconductor layer of amorphous silicon (hereinafter referred to as a-Si) has attracted attention. The TFT has a wide range of applications and can be applied to integrated circuits, CCDs, etc. In particular, recently, its use as a switch element of an active matrix type liquid crystal display element has been widely studied.

The following is an example of this TFT. That is, it consists of a gate electrode, a gate insulating film and a
This is a structure in which after sequentially forming a semiconductor layer made of —Si, a source electrode and a drain electrode are formed on the semiconductor layer so as to sandwich the gate electrode. Usually, in order to obtain ohmic contact between the source and drain electrodes and the semiconductor layer, the portions where the source and drain electrodes are in contact with the semiconductor layer are disclosed in JP-A-56-135968 and JP-A-58-190061. As described in the publication, an n ⁺ layer having a-Si as a matrix,
Alternatively, a laminated film of this layer and a molybdenum film is sandwiched.

[Problems of background technology]

However, when such a layer is sandwiched between the source and drain electrodes and the semiconductor layer, sufficient ohmic contact may not be obtained. Fig. 4 shows n ⁺ with a-Si matrix
Regarding the TFT using the layer as an ohmic contact layer,
FIG. 7 is a diagram showing a relationship between a source-drain voltage V _DS and a drain current I _D when the gate voltage V _G is 5V, 10V, 15V, and 20V. As shown in FIG. 4, _ID does not rise near V _DS = 0.

This incomplete ohmic contact results in n ⁺ with a-Si matrix.
It is considered that this is because the activation rate of impurities in the layer is low and there is substantially no contribution as a donor, and the electron injection amount from the source electrode is reduced.
In particular, when a semiconductor layer made of a-Si and an n ⁺ layer having a-Si as a base cannot be continuously formed and a patterning process using a photoresist or the like is performed in between, an n-type having a-Si as a base is used. ^It is considered that the activation rate of impurities on the surface of the ⁺ layer is so low.

[Object of the Invention]

The present invention has been made to solve such a conventional drawback, and an object thereof is to provide an amorphous silicon semiconductor device in which ohmic contact between an a-Si film and an ohmic electrode is good.

[Outline of Invention]

That is, the present invention is a gate electrode disposed on an insulating substrate,
In an amorphous silicon semiconductor device having a gate insulating film disposed on the gate electrode, an amorphous silicon film facing the gate electrode through the gate insulating film, and a source and drain electrode on the amorphous silicon film, an amorphous silicon film It is characterized in that an n ⁺ layer having a dark conductivity of 1 (Ωcm) ^-1 or more and having a base of microcrystalline silicon is provided between the n ⁺ layer and the source or drain electrode.

Example of Invention

 Details of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention and shows a staggered TFT. This is because a source electrode (2) and a drain electrode (3) made of, for example, ITO are arranged as ohmic electrodes on an insulating substrate (1) such as a glass substrate, and on both electrodes (2) and (3). , A phosphorus-doped n ⁺ layer (4) whose base is microcrystalline silicon (hereinafter referred to as μc-Si) is formed to a thickness of about 500 Å. Where this n
⁺ Layer (4) a substrate temperature of 250 ° C., RF power density 0.6 W / cm ^2, pressure 1.0 Torr, SiH ₄ 10 _SCCM diluted to 10% in H _2, with H ₂ 2500P
It was obtained by depositing for 10 minutes by the plasma CVD method under the condition of PH ₃ 4 _SCCM diluted to pm, and the dark electric conductivity was 2 (Ω
cm) ^-1 . And source and drain electrodes (2),
An a-Si film (5), which is a semiconductor layer, is formed on the insulating substrate (1) so as to cover (3) and the n ⁺ layer (4) with a thickness of about 3000 Å. (2), (3)
Partially comes into contact with the surface of the a-Si film (5) through the n ⁺ layer (4). A gate insulating film (6) made of, for example, SiN and having a thickness of about 4000Å is formed so as to cover the a-Si film (5). Further, a gate electrode (7) made of, for example, Al is formed on the gate insulating film (6), and the gate electrode (7) is a through the gate insulating film (6).
It comes to face the -Si film (5). Thus the element is a
An amorphous silicon semiconductor device, which is a TFT having the -Si film (5) as a semiconductor layer, can be obtained.

FIG. 2 shows a gate voltage V _G of 5V, 10V, 15 for this embodiment.
Source-drain voltage V _DS and drain current at V and 20 V
It is a figure which shows the relationship with _ID . As shown in Fig. 2, the ohmic contact characteristics are better than before, especially V
Significant improvement in small areas of _DS . This results in a large I _D
And the on-resistance of the TFT is reduced,
In the case of an active matrix type liquid crystal display element using a TFT, the limit frequency of the circuit using the TFT is increased, so that more pixels can be displayed.

Usually, μc-Si is a mixed phase of 60 to 100 Å island-shaped crystal regions and a-Si, and can be produced by the same plasma CVD method used for forming an a-Si semiconductor layer. But μc
It is necessary to increase the input electric power and the flow rate of H ₂ at the time of film formation of -Si, as compared with the case of film formation of a-Si. Specifically, the power density is 0.1 W / cm ² or more, and the flow rate of H ₂ is 10 times or more that of SiH ₄ . In addition, the μc-Si impurity-doped film has a high impurity activation rate. The dark electric conductivity of the n ⁺ layer obtained by adding phosphorus to a-Si as an impurity is on the order of 10 ^-3 (Ωcm) ^-1 , whereas the n ⁺ layer of phosphorus added to μc-Si is ,
It is easy to obtain a dark electric conductivity of about 1 (Ωcm) ^-1 . Since the dark electric conductivity of the n ⁺ layer of μc-Si is large, it is due to the high mobility and the large number of activated impurities contributing to the electric conduction. Actually, the mobility of μc-Si is about 10 to 50 times that of a-Si, and the difference in dark electric conductivity of about three digits is considered to be due to the large difference in the activation rate of impurities.

[Other Embodiments of the Invention]

FIG. 3 is a diagram showing another embodiment of the present invention, which shows an inverted staggered type TFT, and the portions corresponding to those in FIG. A gate electrode (7) made of, for example, ITO is arranged on an insulating substrate (1), for example, a glass substrate, and a gate insulating film (6) made of, for example, SiN and having a thickness of about 4000 Å is covered therewith. Then, an a-Si film (5) having a thickness of about 3000Å is formed on the gate insulating film (6), and the gate electrode (7) is a through the gate insulating film (6).
It comes to face the -Si film (5). The thickness of the a-Si film (5) is about 500 with a part of μc-Si as a matrix.
A source electrode (2) and a drain electrode (3) made of, for example, Al are formed as ohmic electrodes so as to be in contact with each other via the n ⁺ layer (4) of Å. In this way, the element is a-Si
An amorphous silicon semiconductor device which is a TFT having the film (5) as a semiconductor layer is obtained. Also in this embodiment, the same result as shown in FIG. 2 is obtained, and the ohmic contact characteristics are improved as compared with the conventional case.

Up to now, the case where the device is a TFT has been described,
The present invention can be applied to the case where the element is, for example, a resistance element having a structure corresponding to that of the element shown in FIG. 1 excluding the gate insulating film (6) and the gate electrode (7). The a-Si film (5) may be either a dangling bond of Si atoms terminated with hydrogen or fluorine.

〔The invention's effect〕

As described above, the amorphous silicon semiconductor device of the present invention has a dark conductivity of 1 (Ω) with microcrystalline silicon as a matrix at the contact portion between the a-Si film and the electrode connected to this film.
cm) ^-1 or more n ⁺ layer is interposed, so the a-Si film and n ⁺ layer
The contact interface with the layer can be formed very well, which results in good ohmic contact characteristics, thus obtaining a large drain current (I _D ) even in a region where the source-drain voltage (V _DS ) is small. You can

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a relation between a source-drain voltage and a drain current of the embodiment shown in FIG. 1, and FIG. FIG. 4 is a diagram showing the relationship between the source-drain voltage and the drain current of a conventional TFT. (1) …… Insulating substrate (2) …… Source electrode (3) …… Drain electrode (4) …… n ⁺ layer (5) …… Amorphous silicon film

Claims (1)

[Claims] 1. A gate electrode arranged on an insulating substrate, a gate insulating film arranged on the gate electrode, an amorphous silicon film facing the gate electrode through the gate insulating film, and an amorphous silicon film. In an amorphous silicon semiconductor device having source and drain electrodes arranged above, a dark conductivity having microcrystalline silicon as a matrix between the amorphous silicon film and the source or drain electrode is 1 (Ωcm). ) An amorphous silicon semiconductor device having an n ⁺ layer of ^-1 or more.