JPH06101498B2 - Semiconductor device failure analysis method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device failure analysis method, and more particularly to a method capable of easily performing a semiconductor device failure analysis by an electron beam tester.

[Conventional technology]

Conventionally, the failure analysis of this kind of semiconductor integrated circuit is, as a first method, a potential using an electron beam tester (or strobe SEM) without removing the passivation film 8 and the insulating film II8 between the conductor wirings 7 at all. Observing contrast and waveform.

The second method is shown in FIGS. 2 (a) and 2 (b).
As shown in, the insulating film II8 is removed by etching and the same observation is performed.

[Problems to be solved by the invention]

In the case of the conventional semiconductor integrated circuit failure analysis method described above,
First, the first method has a drawback that the potential contrast cannot be determined when the absolute value of the potential to be observed by the electron beam tester is small. Further, in the second method, when the insulating film is a silicon nitride film, isotropic plasma etching or the like is used. However, as shown in FIG. 2B, the lower conductor wiring and the upper layer are used. There is a drawback that the silicon nitride film between the first and second conductor wirings is removed and the lower conductor wiring and the upper conductor wiring are short-circuited.

[Means for solving problems]

A failure analysis method for a semiconductor device according to the present invention is a semiconductor integrated circuit having a diffusion region such as a semiconductor element and a multilayer conductor wiring on one main surface. A first step of removing the insulating film by reactive ion etching;
Only the insulating film left on the surface of the conductor wiring of each layer exposed on the surface in the first step is subjected to focused ion
Complete removal by beam etching 2nd
And the third step of performing failure analysis on the surface of the conductor wiring of each layer from which the insulating film has been completely removed by the second step by an electron beam tester using a strobe SEM.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

1 (a) to 1 (e) are cross-sectional views showing an embodiment of the present invention in the order of steps, showing an embodiment applied to a method of failure analysis of a silicon semiconductor integrated circuit having two-layer wiring by an electron beam tester. is there.

First, as shown in FIG. 2A, a semiconductor in which a silicon oxide film 2 is formed on an n-type silicon substrate 1 and two-layer wiring of aluminum 3 is formed between layers and a silicon nitride film 4 as a passivation film. When analyzing an integrated circuit, first, as shown in FIG. 2B, the silicon nitride film 4 is anisotropically etched by using RIE (reactive ion etching), and as shown in FIG. become. The silicon nitride film 4 remains on the first-layer aluminum wiring 3 and the second-layer aluminum wiring 3. Further, as shown in FIG. 3D, the silicon nitride film 4 left on the aluminum wiring 3 of the first layer and the aluminum wiring 3 of the second layer by using FIB (focused ion beam) etching. Only is removed. And the same figure (e)
As shown in, the electron beam is irradiated on the first and second layers of aluminum wiring, and at the same time, this silicon integrated circuit is started by using an LSI tester or the like, and the principle of the strobe scanning electron microscope 1 (SEM) is shown. To observe the potential contrast and the internal potential waveform. As the potential difference
The potential below 0.5V to 0.25V can be observed.

In this way, the electron beam tester performs the failure analysis.

〔The invention's effect〕

As described above, according to the present invention, the reactive ion etching (RIE) is performed on the insulating film for passivation of the semiconductor integrated circuit having the multilayer wiring and the insulating film between the layers of the multilayer conductive wiring.
The focused ion beam (FI
B) By completely removing it by etching, the surface of the conductor wiring of each layer is subjected to a very small potential difference, for example, a potential difference of 0.25V or 0.5V by the potential contrast method and the waveform method by the electron beam tester using strobe SEM. This has the effect that failure analysis can be performed easily.

[Brief description of drawings]

1 (a) to 1 (e) are cross-sectional views of an embodiment of the present invention, and FIGS. 2 (a) to 2 (b) are cross-sectional views for explaining problems in the conventional method. 1 ... n-type silicon substrate, 2 ... silicon oxide film, 3 ...
... Aluminum wiring, 4 ... Silicon nitride film, 5 ... Semiconductor substrate, 6 ... Insulating film I, 7 ... Conductor wiring, 8 ... Insulating film II.

Claims (1)

[Claims] 1. A failure analysis method for a semiconductor integrated circuit having a diffusion region such as a semiconductor element and a multi-layer conductor wiring on one main surface, wherein an insulation film for passivation on the semiconductor integrated circuit and insulation between layers of the multi-layer conductor wiring are provided. The focused ion beam is used only for the first step of removing the film by reactive ion etching and the insulating film left on the surface of the conductor wiring of each layer exposed on the surface by the first step. The second step of completely removing the insulating film by the etching, and the failure analysis of the surface of the conductor wiring of each layer in which the insulating film is completely removed by the second step by an electron beam tester using a strobe scanning electron microscope. A failure analysis method for a semiconductor device, comprising: a third step.