JPH06105898B2 - Interference compensation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a configuration of an interference compensation circuit that removes interference from other systems that a digital signal receives in a digital communication system.

(Conventional Circuit) An example of a conventional configuration is shown in FIG. 3 (Japanese Patent Application No. 60-287881). FIG. 3 will be described in detail below. Main antenna for receiving main signal 1
The signal received from is passed through the bandpass filter 2 to improve the S / N as necessary, and then converted into the IF band by the frequency converter 3. On the other hand, the interfering signal received by the auxiliary antenna 4 for receiving the interfering signal is passed through the band pass filter 5 to improve the S / N as necessary, and then the local oscillator 7 common to the main signal is used.
Is converted to the IF band by the frequency converter 6. Since the interference signal converted into the IF band adjusts the phase and the amplitude, the interference signal passes through the variable phase circuit 9 and the variable amplitude circuit 8 so that the interference signal has almost the opposite phase and the same amplitude as the interference component leaking into the main signal. Controlled. Synthesizing circuit of the interference signal and the main signal
By adding at 11, the interference component in the main signal is removed. Next, the control method of the variable phase circuit and the variable amplitude circuit will be described. Demodulator 10 for the main signal after combining by combiner 11
Enter 0. In the demodulator, the regenerated reference carrier wave 20 is used for quadrature phase detection 12, 13 and the output signals thereof are passed through harmonic elimination filters 14, 15 to obtain in-phase and quadrature baseband signals. The obtained baseband signals are input to error signal generation circuits 102 and 103, respectively. Here, consider a 16QAM signal as the main signal. When demodulating 16QAM, a 4-level baseband signal is obtained. As shown in FIG. 4, by passing the 4-valued signal through an A / D converter having an output of 3 bits or more, the upper 2 bits of the output represent an identification signal and the upper 3 bits represent an error signal. . Therefore, the residual interference component can be detected by using the output of the upper 3rd bit.

On the other hand, the interference signal is branched by the branch circuit 10 and one of the two is subjected to quadrature phase detection 22 and 23 using the main carrier 20 for the main signal, then passed through the harmonic elimination filters 24 and 25, and regenerated by the main signal demodulator. Using the signal, the discriminators 27 and 28 obtain the discrimination result of the interference signal. Then, correlation detection is performed between the identification result of the in-phase and quadrature component interference signals and the error signal. That is, the result of multiplication of the in-phase interference identification signal and the in-phase error signal (multiplier 30) (digitally performed here) and the orthogonal interference identification signal and the orthogonal error signal The result of multiplication with the result of multiplication (multiplier 29) is added in an analog manner using the resistance circuits 33 and 34, and an integrator 38
Is used as the control signal for the variable amplitude circuit 8. In addition, the result of multiplication 31 of the interference identification signal of the quadrature component and the error signal of the same phase and the result 32 of the multiplication 32 of the identification signal of the interference of the same phase and the quadrature component error signal are subtracted 35, 36 Is passed through an integrator 37 and integrated to obtain a control signal for the variable phase circuit 9.

As described above, the interference compensation can be automatically performed.

(Problems to be Solved by the Invention) However, the above-described conventional circuit has a complicated configuration because the variable amplitude circuit and the variable phase circuit are used to control the amplitude and phase of the interference signal.

The present invention aims to improve this point.

(Means for Solving the Problems) The present invention performs the functions of the conventional variable amplitude circuit and variable phase circuit by the quadrature amplitude modulator, and one of the features is that the main antenna for receiving the main signal and the interference are provided. A signal receiving means, a quadrature amplitude modulator for adjusting the relative relationship between the phase and amplitude of the output of the interference signal receiving means and the output of the main antenna, and the main antenna and the interference signal receiving means adjusted by the modulator. A synthesizing circuit for synthesizing the outputs, a first quadrature phase detector for decomposing the output of the synthesizing circuit and a reference carrier reproduced from the main signal into in-phase components and quadrature components, and the in-phase component and the quadrature component respectively And a second quadrature phase detector for decomposing the output of the interference signal receiving means into an in-phase component and a quadrature component by the same reference carrier as that of the first quadrature phase detector. A first multiplier for providing a product of the output of the phase component error signal generating circuit and the in-phase component output of the second quadrature phase detector; the output of the quadrature component error signal generating circuit; and the second quadrature A second multiplier that provides a product of the quadrature component output of the phase detector, and a third multiplier that provides a product of the output of the quadrature component error signal generating circuit and the in-phase component output of the second quadrature phase detector. , A fourth multiplier that provides a product of the output of the in-phase component error signal generating circuit and the quadrature component output of the second quadrature phase detector, and the output of the first multiplier, the second multiplier First integrator that receives the output of the multiplier or the sum of the two, and a second integrator that receives the output of the third multiplier, the output of the fourth multiplier, or the difference between the two. And controlling the in-phase component of the quadrature amplitude modulator by the output of the first integrator, and the quadrature by the output of the second integrator. In interference compensating circuit for controlling the quadrature component width modulator.

(Example) An example of claim (1) is shown in FIG. The digital signal received from the main antenna 1 for receiving the main signal passes through the band pass filter 2 to improve the S / N as necessary, and is converted into the IF band by the frequency converter 3. On the other hand, the interference signal received from the auxiliary antenna 4 for receiving the interference signal has a band-pass filter 5 to improve the S / N as necessary.
And is converted to the IF band by the frequency converter 6 using the local oscillator 7 common to the main signal side. The quadrature amplitude modulator 20 controls the amplitude and phase of the interference signal converted to the IF band.
Entered in 0. The output signal has almost the same phase and amplitude as the interference component leaked into the main signal. Therefore, almost no interference component appears in the output of the combiner 14.

The quadrature amplitude modulator 200 includes a distributor 9 that divides a signal into two,
After passing through the bipolar variable attenuator 11 that inputs one of the signals and the phase shifter 10 that shifts the phase of the other output of the distributor 9 by 90 °, the bipolar variable attenuator 12 and the two bipolar variable It is composed of a combiner 13 for combining the attenuator outputs.

The control method of the above two bipolar variable attenuators will be described below. The main signal synthesized by 14 is input to the demodulator 100. In the demodulator, 15 by the reference carrier by 21 reproduced
16 and 16 perform quadrature detection, and after passing through the harmonic elimination filters 22 and 23, demodulated baseband signals are obtained. The in-phase and quadrature component baseband signals are connected to error signal generation circuits 102 and 103 for detecting residual interference signals. 1
Taking a 6QAM signal as an example, the demodulated baseband signal is 4
It becomes a value. Using this signal as input,
By using an A / D converter having an output of more than 1 bit, the upper 2 bits of the output can detect the identification signal and the upper 3 bits of the error signal, that is, the residual interference component can be detected. On the other hand, the low-pass filter 2 that removes the harmonic components after the quadrature phase detection is performed by 17, 18 using the reference carrier 21 regenerated by the main signal demodulator for the interference signal converted to the IF band
The signal is passed through 4,25 and the in-phase and quadrature component interference signals binarized by the discriminators 31 and 32 are obtained by using the clock signal reproduced by the main signal demodulator. Correlation detection is performed between the obtained in-phase and quadrature component error signals and the in-phase and quadrature component interference signals. That is, the result of multiplication of the in-phase error signal and the in-phase interference signal by 34 (here, the EX-OR circuit is used to perform digitally) and the orthogonal error signal and the orthogonal interference signal are multiplied by 33. The results are passed through resistor circuits 37 and 38 for adding both in an analog manner and an integrator 42 for integrating the outputs. The output controls the 0-phase bipolar variable attenuator 11 of the quadrature amplitude modulator 200. In addition, the error signal of the in-phase component and the interference signal of the quadrature component
The result of multiplication by 35 and the result of multiplication of the error signal of the quadrature component and the interference signal of the in-phase component by 36 are subtracted by the resistance circuits 39 and 40, and the output is passed to the integrator 41 for integration. The output controls the π / 2-phase bipolar variable attenuator 12 of the quadrature amplitude modulator 200. As described above, the interference is automatically removed.

An embodiment of claim (2) is shown in FIG. The difference from FIG. 1 which is an embodiment of claim (1) is that
In the case of FIG. 1, the quadrature phase detector is used for processing the interference signal, but in FIG. 2, a simple phase detector 17 is used. Therefore, in the case of FIG. 2, there is an advantage that the circuit configuration can be simplified accordingly. Details will be described below. The interference signal converted to the IF band is detected by the phase detector 17 using the carrier wave 21 regenerated by the demodulator for the main signal and then passed through the harmonic elimination filter 24, and then regenerated by the demodulator on the main signal side. The discriminator 31 obtains the binarized interference signal using the clock signal thus generated. The interference signal and the error signal (103) output relatively in phase with it are multiplied by 33 (EX-OR is used here because it is digitally performed), and then the integrator 4
Passing 1 controls the 0-phase bipolar variable attenuator 11 of the quadrature amplitude modulator (200). In addition, the binarized interference signal and the error signal (102) output and 3
After being multiplied by 5, it is passed through an integrator 42 to control the π / 2-phase bipolar variable attenuator 12 of the quadrature amplitude modulator (200).

Therefore, the interference compensation can be automatically performed.

Although the case where the embodiment of the present invention is applied to the IF band has been described above, it is of course possible to directly perform the operation on the RF band.

For the embodiment of FIG. 1 or FIG. 2, in fact, tau _1,
Adjust the relative timing with the delay line of τ ₂ , τ ₃ ,
It is necessary to maximize the compensation effect.

1 or 2 of the embodiment of the present invention, in the case of a QAM (quadrature amplitude modulation) signal as a main signal, for example, a 16QAM signal, the error signal generating circuits 102 and 103 have outputs of 3 bits or more. Using the / D converter, the error signal can be directly taken out from the upper 3rd bit as shown in FIG. Generally, in the case of 2 2 ^N value QAM, the demodulated baseband signal becomes a 2 ^N value signal, and this signal is identified, and in order to obtain an error signal, an A / D converter having an output of N + 1 bits or more is used, and the upper N + 1 bits are used. The error signal can be taken directly from the eye.

On the other hand, if the demodulated baseband signals are not evenly spaced, such as 8PSK and 16PSK, it is not possible to extract only one bit and use it as an error signal.

For example, in the case of 8PSK
An example of using an A / D converter is shown in FIG. By quadrature detection of 8PSK, the demodulated baseband waveform becomes a four-valued signal with different signal intervals. By digitizing this with 8 bits, the signal point 1 becomes Signal point 2 is, for example, Signal point 3 Signal point 4 And As for the error signal, the shaded portion shows a positive error and the blank portion shows a negative error. Therefore, the output of the A / D converter is constantly monitored, and when an oblique line is entered, a conversion circuit is provided by a ROM or the like so as to obtain a positive error signal and a negative error signal otherwise, an error signal generation circuit is provided. Can be realized.

(Effects of the Invention) As described above, when varying the amplitude and phase of the interference signal received from the auxiliary antenna, the quadrature amplitude modulator is used to control the 0-phase and π / 2-phase bipolar variable attenuators. By doing so, it is possible to automatically eliminate the interference component leaked into the main signal.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, FIG. 3 is a block diagram of a conventional interference compensation circuit, and FIG. 4 is an error signal generation circuit. Illustration,
FIG. 5 is a diagram for explaining the operation of the error signal generating circuit. (Description of symbols; Fig. 1) 1 ... Main antenna, 4 ... Auxiliary antenna, 2,5 ... Bandpass filter, 3,6 ... Frequency conversion circuit, 7 ... Local oscillator, 8, 9 ... Distributor, 10 …… 90 ° phase shifter, 11,12 …… Bipolar variable attenuator, 13,14 …… Combiner, 15,16,17,18 …… Phase detector, 19,20 …… 90゜ Phase shifter, 21 …… Regenerated carrier wave, 2
2,23,24,25 …… Low pass filter, 27,28,31,32 …… Identification circuit, 29,30 …… Subtractor, 26 …… Reproduced clock, 33,3
4,35 …… EX-OR circuit, 36 …… EX-NOR circuit, 37,38,39,40…
… Resistor circuit, 41,42 …… Integrator, 100 …… Main signal demodulator,
101 ... Control circuit, 102, 103 ... Error signal generation circuit, 200
...... Quadrature amplitude modulator

Claims (2)

[Claims] 1. A main antenna for receiving a main signal, an interference signal receiving means, and a quadrature amplitude modulator for adjusting a relative relationship between a phase and an amplitude of an output of the interference signal receiving means and an output of the main antenna. A synthesis circuit for synthesizing the outputs of the main antenna and the interference signal receiving means adjusted by the modulator, and a first circuit for decomposing the output of the synthesis circuit and the reference carrier regenerated from the main signal into in-phase components and quadrature components. A quadrature phase detector, two error signal generating circuits each having the in-phase component and the quadrature component as inputs, and the same reference carrier as the first quadrature phase detector, the output of the interference signal receiving means as an in-phase component A second quadrature phase detector for decomposing into a quadrature component; a first multiplier for providing a product of the output of the error signal generating circuit for the in-phase component and the in-phase component output of the second quadrature detector; Ingredient A second multiplier that provides a product of the output of the difference signal generation circuit and the output of the quadrature component of the second quadrature detector; the output of the error signal generation circuit of the quadrature component; and the second quadrature detector And a fourth multiplier that provides a product of the output of the error signal generation circuit of the in-phase component and the quadrature component output of the second quadrature phase detector. And a first integrator that receives the output of the first multiplier, the output of the second multiplier, or the sum of the two, and the output of the third multiplier, the output of the fourth multiplier, or A second integrator having a difference between the two as an input; the in-phase component of the quadrature amplitude modulator is controlled by the output of the first integrator; and the quadrature amplitude modulator by the output of the second integrator. An interference compensation circuit characterized by controlling the quadrature component of the. 2. A main antenna for receiving a main signal, an interference signal receiving means, and a quadrature amplitude modulator for adjusting the relative relationship between the phase and amplitude of the output of the interference signal receiving means and the output of the main antenna. A synthesis circuit for synthesizing the outputs of the main antenna and the interference signal receiving means adjusted by the modulator, and a first circuit for decomposing the output of the synthesis circuit and the reference carrier regenerated from the main signal into in-phase components and quadrature components. A quadrature phase detector, two error signal generating circuits each having the in-phase component and the quadrature component as inputs, and the same reference carrier as the first quadrature phase detector, phase-detects the output of the interference signal receiving means. A phase detector, a first multiplier that provides a product of the output of the in-phase component error signal generation circuit and the output of the phase detector, an output of the quadrature component error signal generation circuit, and an output of the phase detector When A second multiplier for providing a product and first and second integrators coupled to the outputs of each multiplier, the output of the first integrator controlling the in-phase component of the quadrature amplitude modulator An interference compensation circuit, wherein the quadrature component of the quadrature amplitude modulator is controlled by the output of the second integrator.