JPH06105894B2 - Internal frame configuration method of digital cross connect - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a cross-connect system for digital transmission, and in particular to digital transmission used to switch interconnections of time-division multiplexed digital signal transmission lines within a station. Cross connect method

[Conventional technology]

With the expansion of the application area of digital communication in recent years, the initial setting of routes for digital transmission lines, the addition of lines during operation,
Compared to the cross-connect method for changing the service or changing the route in response to the occurrence of a failure, downsizing of the equipment, reduction of the concentrating space, labor saving of connection work, and diversification of switchable hierarchy levels, etc. There are increasing demands on many fronts.

The conventional cross-connect method for digital transmission of this type uses a distribution rack provided with a switch group for switching interconnections (cross-connects) of a plurality of signal lines (for example, coaxial cables) and manually operating the switches. This is the method of switching the connection by. There are two types of digital signals on the transmission line: synchronously multiplexed synchronous systems and stuff-multiplexed asynchronous meters. For asynchronous digital signals, a time switch is used to switch connections by exchanging time slots. Since there is no applicable technology, space switches that interconnect the signal lines are used as the switch group of the distribution rack. In addition, it was considered that the time division switch could be used as a necessary condition for both the low-order group signal and the high-order group signal to be perfectly synchronized.

[Problems to be solved by the invention]

Since the above-mentioned conventional cross-connect method for digital transmission uses a space switch as a switching means for interconnecting transmission lines, there are demands for miniaturization of equipment, saving of concentrating space, and diversification of switching units. It has a problem that it is impossible to respond sufficiently.

In other words, the time switch can be easily miniaturized by the integration of the circuit, but the space switch can be miniaturized. Furthermore, in order to diversify the switching unit, it is necessary to decompose the high-order group into its constituent low-order groups and perform connection switching in units of the low-order groups. In the conventional method using the space switch,
The digital signals of the higher-order group are decomposed into lower-order groups by a demultiplexer, then led to the distribution rack, the interconnections of the lower-order groups are exchanged on the distribution rack, and then the lower-order groups are converted into higher-order groups by the multiplexer. There is no choice but to adopt a configuration that multiplexes. As a result,
In addition to the distribution rack, a multiplexer and a demultiplexer must be provided, and the number of signal lines increases in order to guide the decomposed low-order group digital signals, reducing the size of the device and concentrating space. Becomes impossible.

The object of the present invention is to apply the same time switch to both the asynchronous digital signal and the synchronous digital signal at the same time in order to solve the above-mentioned problems, and to connect at either the high-order group unit level or the low-order group unit level. Another object of the present invention is to provide a method of constructing an internal synchronization frame that enables replacement.

[Means for solving problems]

According to the present invention, m digital M-order group signals are multiplexed by stuff synchronization multiplexing or synchronism multiplexing, and one N (where N> M) order group signal is n-order group unit or m-order group unit. Time division switch (TST (Time division-Space d
(including the time division switch of the ivision-Time division configuration), (1) Set the internal frame configuration frequency to a frequency h'which is slightly higher than the nominal frequency h of the Nth order group signal, and The next group signal is stuff-synchronized in units of one, the frame length is set to l, stuff bits and variable bits are inserted at appropriate intervals, and further frame bits are added if necessary, and the multiframe length is set. A method of constructing an internal frame of a digital cross-connect, characterized in that L is 1 × m bits, or (2) setting the internal frame constructing frequency to a frequency h ′ slightly higher than the nominal frequency h of the Nth order group signal, If the Mth-order group signals are asynchronous with each other, the Nth-order group signal is first decomposed into m Mth-order group signals, and stuff bits and The varying bit and the appropriate number empty bits are arranged at appropriate intervals, and stuff synchronization,
By arranging m stuff-synchronized signals,
A method for constructing an internal frame of a digital cross connect, characterized in that a multiframe length L is set to 1 × m bits,
Or (3) The internal frame configuration frequency is set to a frequency h'slightly higher than the nominal frequency h of the Nth-order group signal, and when the Mth-order group signal is a synchronous system, h'is set to the nominal Mth-order group signal. Synchronize to the frequency 1 and once decompose the Nth order group signal into m Mth order group signals, and insert an appropriate dead pulse in the frame length 1 in each M order group unit to achieve synchronization. Data is embedded in the frame, and the embedded signal is m
With this arrangement, the multiframe length L is set to 1 × m bits, and the higher-order group frequency h ′ and the M-order group signal frequency l
In order to correct the speed of the above, an internal frame configuration method of digital cross-connect is obtained, in which all 1 bit of 1 frame are made empty slots at a certain frame interval.

Further, according to the present invention, in the North American Hierarchy,
In the method of cross-connecting a 44.736 Mb / s (DS3) digital signal obtained by multiplexing 28 44 Mb / s (DS1) digital signals at the DS1 level or DS3 level using a time division switch, h '= 45.808 An internal frame configuration method for a digital cross connect is obtained, characterized in that MHz, l = 204 bits, L = 204 × 28 = 5712 bits.

〔Example〕

Next, an embodiment of the present invention in the case of handling a North American Hi-Araki digital signal will be described.

First, we describe a method to obtain the internal frame structure for cross-connecting the DS3 signal directly at the DS3 level using a time-resolved switch. Define the symbols needed to determine the inner frame.

ρ: Stuff rate H: Number of DS3 bits allocated in one frame H '... Total number of bits in one frame h ... Frequency of stuffed signal h' ... Internal synchronization frequency Now DS3 signal In order to obtain the internal frame structure that directly stuffs, the formula (1) must be satisfied.

Next, a method for obtaining the internal frame structure required to synchronize 28 asynchronous DS1 signals to the internal synchronization frequency h'by stuff synchronization will be described. Define the symbols needed to determine the inner frame.

ρ: Stuff rate L '... Number of bits of 1DS1 allocated in one frame H' ... Total number of bits in one multiframe length l ... Frequency of stuffed signal h '... Internal synchronization frequency N ...... Multiplicity (28) Now, it is necessary to satisfy equation (2) in order to construct an internal frame by stuff-synchronizing each of 28 DS1 signals.

Next, a method for obtaining the internal frame structure required to synchronize the synchronous DS1 signal with the internal synchronization frequency h ′ without damaging the information of each Digroup will be described. In order to simply implement the mixed implementation of the synchronous system and the asynchronous system, slip operation should be avoided when inputting the synchronous signal to the time-division switch. In order to obtain the frame configuration, the variable frame length stuff operation is required. The concept of should be introduced and realized by synchronous staff. The symbols necessary for determining the internal frame in this case are defined.

l …… Low-order group (DS1) frequency N …… Multiplicity (28) l …… Frame length per low-order group …… Frame length variable ratio (simple rational number) Dl …… 1 Digroup frame length (193 bits) ) Now, in order to synchronously multiplex 28 synchronous DS1 signals to the internal synchronization frequency h ′ without damaging the information of each Digroup, the expression (3) must be satisfied.

The first frame structure that simultaneously satisfies Eqs. (1), (2), and (3) is based on the following conditions: synchronization frequency h ′ = 45.808 (MHz) Multiframe length is 204 × 28 = 5712
Is a bit.

Conditions DS3 nominal frequency …… 44.736 (Mb / s) DS1 nominal frequency …… 1.544 (Mb / s) DS1 Digroup frame length …… 193 (bit) DS1 multiplicity within DS3 …… 28 This will be explained using an example.

FIG. 1 is a diagram showing a synchronization frame structure in the case of converting a DS3 signal into a signal synchronized with a common frequency h '(hereinafter referred to as a DS3' signal) by direct stuff synchronization. 1
The frame length is 204 bits, the frame alignment signal is allocated to the first, and the stuff control bit is allocated to the 51st and 103rd. Also, the parity check bit is allocated to the 204th position. By arranging 28 frames in series, one multi-frame is formed.

Figure 2 shows an asynchronous DS1 signal converted to DS3 'by stuff synchronization.
It is a figure which shows the synchronous frame structure at the time of converting into a signal.

FIG. 3 is a diagram showing a synchronization frame structure in the case of converting a synchronous DS1 signal into a DS3 ′ signal in a state where the DS0 information is stored without destroying the Digroup information sequence. In this case, frequency synchronization is established between the DS1 signal and the DS3 ′ signal. In Figure 3, the first frame is DS1 Digroup1
However, DS1 Digroup2 is allocated to the second frame and DS1 Digroup28 is allocated to the 28th frame. Also, each Digroup
Complete synchronization between DS1 and DS3 'is established by inserting an empty bit in every frame once every 409 frames.

〔The invention's effect〕

As described above, according to the present invention, the same time switch is applied to both the asynchronous digital signal and the synchronous digital signal at the same time, and the connection can be exchanged at either the high-order group unit level or the low-order group position level. A method of constructing an internal frame is provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a frame configuration method according to a first embodiment of the present invention, and is a diagram showing a DS3 ′ frame configuration in the case of direct DS3 conversion. F _{1 to} F ₂₈ ... Frame bits C ₁ and C ₂ ... Stuff control bits P ... Parity bits 1-200 ... Data bits (1 bit is a variable bit) FIG. 2 is a second embodiment of the present invention. FIG. 7 is a diagram for explaining a frame configuration method according to an example, and is a diagram showing a DS3 ′ frame configuration when 28 DS1s are stuff-multiplexed. F _{1 to} F ₂₈ ...... Frame bits C ₁ , C ₂ , C ₃ ...... Stuff control bits V _{1 to} V ₆ ...... Empty time slot P ...... Parity bit 1 to 193 ...... Data bit (1 bit of which is variable (Bit) FIG. 3 is a diagram for explaining the frame configuration method according to the third embodiment of the present invention. D when 28 DS1s are synchronously multiplexed
It is a figure which shows a S3 'frame structure. F _{1 to} F ₂₈ …… Frame bits ₁ to 193 …… Data bits S _{1 to} S ₄ …… Other information bits (1) (for example, signal bits) Sa, Sb …… Other information bits (2) (for example, signals (Distribution bit) V _{1 to} V ₃ ... Empty bit P ... Parity bit.

Claims (6)

[Claims] 1. N-th group of m N-th group signals (where N> M) obtained by multiplexing m number of digital M-th group signals by stuff synchronization multiplexing or synchronization multiplexing In the method of cross-connecting using a time division switch, the internal frame configuration frequency is set to a frequency h'which is slightly higher than the nominal frequency h of the Nth order group signal, and the Nth order group signal is stuff-synchronized in units of one. , Frame length is set to l, stuff bits and variable bits are inserted at appropriate intervals, and frame bits are added if necessary,
A method for constructing an internal frame of a digital cross connect, characterized in that a multiframe length L is set to 1 × m bits. 2. N-th group of m N-th group signals (where N> M) obtained by stuffing m digital M-th group signals by stuff synchronous multiplexing or synchronous multiplexing In the method of cross-connecting using the time division switch, if the internal frame configuration frequency is set to a frequency h'which is slightly higher than the nominal frequency h of the Nth order group signal, and the Mth order group signal is asynchronous, First, the Nth group signal is decomposed into m Mth group signals, and stuff bits and variable bits and an appropriate number of empty bits are arranged at appropriate intervals in the frame length l in each Mth group signal. A method of constructing an internal frame of a digital cross connect, characterized in that a multi-frame length L is set to 1 × m bits by arranging stuff-synchronized and stuff-synchronized signals. 3. The method for constructing an internal frame of a digital cross-connect according to claim 2, wherein when an asynchronous Mth order group signal is directly input, it is incorporated into the above frame without performing the above decomposition. , A method of constructing an internal frame of a digital cross-connect with multiframe length L = 1 × m bits. 4. N-th group of m N-th group signals (where N> M) obtained by multiplexing the m-th group of digital M-th group signals by stuff synchronization multiplexing or synchronization multiplexing In the method of cross-connecting using the time division switch, when the internal frame constituent frequency is set to a frequency h'slightly higher than the nominal frequency h of the Nth order group signal and the Mth order group signal is a synchronous system, h ′ Is synchronized with the nominal frequency l of the M-th order group signal, and once the N-th order group signal is decomposed into m M-th order group signals, each M-th order group unit has an appropriate dead pulse within the frame length l. By inserting the data into the frame in a synchronous state,
With this arrangement, the multiframe length L is set to 1 × m bits, and the higher-order group frequency h ′ and the M-order group signal frequency l
An internal frame configuration method for digital cross-connect, characterized in that all 1 bit of 1 frame is made an empty slot at a certain frame interval for speed correction. 5. The method for constructing an internal frame of a digital cross-connect according to claim 4, wherein when a synchronous Mth order group signal is directly input, it is incorporated in the above frame without performing the above decomposition. , A method of constructing an internal frame of a digital cross-connect with multiframe length L = 1 × m bits. 6. In North American Hierarchy, 1.544 Mb / s
Obtained by multiplexing 28 (DS1) digital signals44.
In the method of cross-connecting a 736 Mb / s (DS3) digital signal at the DS1 level or DS3 level using a time division switch, h ′ = 45.808 MHz, l = 204 bits, L = 204
A method for constructing an internal frame of a digital cross connect, characterized in that x28 = 5712 bits.