JPH06104405A - Static memory - Google Patents

Abstract

(57) [Summary] [Object] It is an object of the present invention to provide a static type memory capable of suppressing an increase in cell area to improve the degree of integration and reducing the manufacturing cost per bit. . [Structure] The NMOS transistors Q1 and Q2 form a flip-flop circuit. NMOS transistor Q2
Between the node N1 connected to the gate of the gate and the bit line BL, and between the node N2 connected to the gate of the NMOS transistor Q1 and the bit line / BL, a P-channel thin film transistor that also serves as a transfer gate and a load resistance. T1 and T2 are respectively connected. By forming the P-channel thin film transistors T1 and T2 overlying the NMOS transistors Q1 and Q2, the area of the circuit pattern can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a static memory, and more particularly to a static memory having a small area suitable for high integration.

[0002]

2. Description of the Related Art FIG. 10 shows an example of a conventional static memory cell. In this static memory cell, one end and a gate of a current path of N-channel MOS field effect transistors (hereinafter referred to as NMOS transistors) Q1 and Q2 that form a flip-flop are cross-connected to each other, and the other end of the current path is grounded. It is connected to the potential V _SS . That is, one end of the current path of the NMOS transistor Q1 is connected to the gate of the NMOS transistor Q2,
One end of the current path 2 is connected to the gate of the NMOS transistor Q1. A resistor R1 is connected between one end of the current path of the NMOS transistor Q1, that is, the node N1 holding one of complementary data and the power supply V _DD, and one end of the current path of the NMOS transistor Q2, that is, Node N that holds the other complementary data
A resistor R2 is connected between 2 and the power source Vcc. Between the node N1 and the bit line BL, an NMOS transistor Q3 as a transfer gate is connected to which one end and the other end of the current path are connected. The gate of the NMOS transistor Q3 is connected to the word line WL. The node N2 and the bit line / B
An NMOS transistor Q4 as a transfer gate having one end and the other end of the current path connected to each other is connected between the L transistors. This NMOS transistor Q4
Is connected to the word line WL.

The static memory cell having the above structure is
Generally, it is called a high resistance load type cell, and the resistance values of 1T to 10TΩ can be obtained by configuring the resistors R1 and R2 with polysilicon not doped. This static memory cell can suppress the current consumption to several μA even with a capacity of 1 Mbit. Figure 1
1 is a pattern plan view of the static memory cell shown in FIG. 10, and the same portions as those in FIG.

In the figure, NMOS transistors Q1 to Q4 are formed at the intersections of the diffusion layer 10 and the first polysilicon layer (gate polysilicon) 11 (WL) which are element-isolated by the field oxide film. The NMOS
One end of the first polysilicon layer 11 forming the gate of the transistor Q2 has an NMOS via a contact portion 12.
It is connected to the diffusion layer 10 of the transistor Q1 so that the NMOS transistors Q1 and Q2 are cross-connected. The other end of the first polysilicon layer forming the gate of the NMOS transistor Q2 is connected to the diffusion layer 10 of the NMOS transistor Q3 at the contact portion 13. Further, the other end of the first polysilicon layer forming the gate of the NMOS transistor Q1 is connected to the diffusion layer 10 of the NMOS transistor Q4 at the contact portion 14.

The resistors R1 and R2 are formed by a second polysilicon layer (not shown) provided above the first polysilicon layer, and the second polysilicon layer is formed by the contact portions 15 and 16 (nodes). NM via N1, N2)
It is connected to the diffusion layer 10 of the OS transistors Q1 to Q4. In this way, the cell layout is reduced by forming the resistor with the second polysilicon layer.

The ground potential wiring of the memory cell is formed by a third polysilicon layer (not shown) provided above the second polysilicon layer, and the third polysilicon layer is formed by the contact portions 17, 18. It is connected to the diffusion layer 10 via. Further, the bit lines BL and / BL are usually composed of metal wiring (not shown) such as aluminum,
The metal wiring is connected to the diffusion layer 10 via the contact portions 19 and 20.

The static memory cell having the above structure is
The minimum processing size is 0.5 μm, and the alignment accuracy is 0.2 μm. It is 18.2 μm ² among the cells that use MOS transistors. And the smallest area.

[0008]

By the way, in the static memory cell, it is necessary to planarly integrate four transistors, two resistance elements and nine contact portions in one cell. For this reason, the cell area is about four times as large as that of a dynamic memory cell having one transistor and one capacitor, which is formed by using the above-mentioned processing size. Therefore, the cost per bit is higher than that of the dynamic memory cell, although the operation is stable.

Further, in order to stabilize the electrical holding operation of the cell at the time of reading, it is necessary to make the driving current capability of the flip-flop NMOS transistors Q1 and Q2 larger than that of the transfer gate NMOS transistors Q3 and Q4. There is. Therefore, when the NMOS transistors Q1 to Q4 are formed on the silicon substrate of the same process, it is necessary to make the gate lengths of the NMOS transistors Q1 and Q2 and the gate widths of the NMOS transistors Q3 and Q4 larger than the minimum processing size. Also contributes to increasing the cell area. Furthermore, it is necessary to provide a wiring for the power supply V _{DD and} a wiring for the ground potential V _{SS in} the memory cell, which also contributes to increasing the cell area.

The present invention has been made to solve the above problems, and an object thereof is to suppress an increase in cell area to improve the degree of integration and to reduce the manufacturing cost per bit. It is intended to provide a static type memory capable of

[0011]

In order to solve the above problems, the present invention provides a second conductivity type first insulated gate transistor formed in a first conductivity type semiconductor substrate, and a second conductivity type first insulated gate transistor in the semiconductor substrate. A second insulated gate transistor of the second conductivity type formed, the gate of the first insulated gate transistor is connected to one end of a current path, and the gate is connected to one end of the current path of the first insulated gate transistor. A power supply line connected to the other ends of the current paths of the first and second insulated gate transistors, and at least a portion of the power supply line overlapped above the first insulated gate transistor. The first insulated gate transistor is connected to one end of a current path, and the other end of the current path is a first path.
A first thin film transistor connected to the bit line and having a gate connected to the word line, and at least a part of the first thin film transistor overlapped with the second insulated gate transistor, and one end of a current path has the second insulated gate transistor. A second thin film transistor is provided, which is connected to one end of the current path of the gate transistor, the other end of the current path is connected to the second bit line, and the gate of which is connected to the word line.

Further, N-channel MOS transistors are used as the first and second insulated gate transistors, P-channel thin film transistors are used as the first and second thin film transistors, and the word line is set to the same potential as the potential of the power supply wiring. The first and second thin film transistors are made conductive, the word line is made higher than the potential of the power supply wiring, and the first and second thin film transistors are made non-conductive, and the bit line read potential higher than the potential of the power supply wiring. Data is held in the first and second insulated gate transistors by the leak current when the first and second thin film transistors are non-conducting.

Further, N-channel MOS transistors are used as the first and second insulated gate transistors,
N-channel thin film transistors are used as the first and second thin film transistors, the word line is set to the same potential as the power supply line to make the first and second thin film transistors non-conductive, and the word line is set to a potential higher than that of the power supply line. The first and second thin film transistors are rendered conductive at a high potential, and the first and second thin film transistors are leaked when the first and second thin film transistors are non-conductive due to a bit line read potential higher than the potential of the power supply wiring. Holds data in the insulated gate transistor.

Further, according to the present invention, there is provided a first insulated gate transistor of a second conductivity type formed in a semiconductor substrate of a first conductivity type and a first insulated gate transistor formed in the semiconductor substrate. A second conductive type second insulated gate transistor having a gate connected to one end of a current path and a gate connected to one end of a current path of the first insulated gate transistor; and the first and second insulated gates. At least a part of the power supply wiring connected to the other end of the current path of the transistor and the first insulated gate transistor are provided to overlap each other, and one end of the current path is connected to the current path of the first insulated gate transistor. The other end of the current path is connected to the first bit line, the first gate is connected to the word line, and the second gate is connected to the second insulated gate transistor. At least a part of the first thin film transistor of the first conductivity type connected to one end of the current path and the second insulated gate transistor are overlapped with each other, and one end of the current path is the second insulated gate transistor. Is connected to one end of the current path of the
Second bit of the first conductivity type having a first gate connected to the word line and a second gate connected to one end of a current path of the first insulated gate transistor.
And a thin film transistor of.

Further, the current flowing when the first and second first thin film transistors are turned on by the first gate is different from the current flowing when turned on by the second gate. It is set to 1/100 or less. The second gates of the first and second first thin film transistors are shared with the gates of the first and second insulated gate transistors. Further, the first,
The second insulated gate transistor retains data by the leak current when the first and second thin film transistors are non-conducting.

Further, according to the present invention, there are provided a first insulated gate transistor of a second conductivity type formed in a semiconductor substrate of a first conductivity type and a first insulated gate transistor formed in the semiconductor substrate. A second conductive type second insulated gate transistor having a gate connected to one end of a current path and a gate connected to one end of a current path of the first insulated gate transistor; and the first and second insulated gates. At least a part of the power supply wiring connected to the other end of the current path of the transistor and the first insulated gate transistor are provided to overlap each other, and one end of the current path is connected to the current path of the first insulated gate transistor. A second thin film transistor of the second conductivity type, which is connected to one end, the other end of the current path is connected to the first bit line, and the gate is connected to the word line; Provided between the gate transistor and the first thin film transistor, one end of the current path is connected to one end of the current path of the first insulated gate transistor, and the other end of the current path is connected to the first bit line. And a second thin film transistor of the first conductivity type whose gate is connected to one end of a current path of the second insulated gate transistor, and at least a part of which is provided above the second insulated gate transistor, One end of the current path is connected to one end of the current path of the second insulated gate transistor, and the other end of the current path is connected to the second bit line,
A third thin film transistor of the second conductivity type whose gate is connected to the word line and a second insulated gate transistor and a third thin film transistor are provided between each other, and one end of a current path has the second insulating film. A first conductive type transistor connected to one end of a current path of the gate transistor, the other end of the current path connected to the second bit line, and a gate connected to one end of the current path of the first insulated gate transistor; And a fourth thin film transistor. Further, the first and second insulated gate transistors hold data by the leak current when the first to fourth thin film transistors are non-conducting. Further, the current paths of the first to fourth thin film transistors are made of an amorphophus semiconductor. The current paths of the first to fourth thin film transistors are made of a polycrystalline semiconductor. Furthermore, the current paths of the first to fourth thin film transistors are made of a single crystal semiconductor. Also,
The power supply wiring is composed of a diffusion layer provided in the half body substrate.

[0017]

That is, according to the present invention, one end of the current path is located above one of the first and second insulated gate transistors for storing data, and one end of the current path is located at one end of the current path of the first and second insulated gate transistors. At least some of the first and second thin film transistors, which are connected to each other, the other ends of the current paths are connected to the first and second bit lines, and the gates are connected to the word line, are provided in an overlapping manner. Therefore, since the first and second thin film transistors also serve as the transfer gate and the load resistor and the power supply V _DD can be omitted, the number of circuit elements can be reduced and the circuit pattern can be reduced as compared with the conventional one.

Further, the circuit operation can be stabilized by making the gates of the first and second thin film transistors have a double structure or by using two thin film transistors having different conductivity types in combination.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those in FIG. 11 are designated by the same reference numerals and only different parts will be described. FIG. 1 shows a first embodiment of the present invention. In FIG.
The same parts as those in FIG. 10 are designated by the same reference numerals.

In this static memory cell,
One ends of the current paths and the gates of the NMOS transistors Q1 and Q2 forming the flip-flop circuit are cross-connected to each other, and the other ends of the current paths are connected to the ground potential V _SS . That is, one end of the current path of the NMOS transistor Q1 is connected to the gate of the NMOS transistor Q2, and one end of the current path of the NMOS transistor Q2 is connected to the gate of the NMOS transistor Q1. One end of the current path of the NMOS transistor Q1 and the gate of the NMOS transistor Q2 are connected, and a P-channel thin film transistor T1 as a transfer gate and a load resistor is provided between the node N1 holding one of complementary data and the bit line BL. One end and the other end of the current path of are connected. This thin film transistor T
The gate of 1 is connected to the word line WL. Also, one end of the current path of the NMOS transistor Q2 and the NMO
The gate of the S transistor Q1 is connected, and between the node N2 holding the other of the complementary data and the bit line / BL, a transfer gate and a P as a load resistance are provided.
One end and the other end of the current path of the channel thin film transistor T2 are connected. The gate of the thin film transistor T2 is connected to the word line WL.

In the above structure, when reading data,
The word line WL connected to the selected memory cell is set to low potential, and the thin film transistors T1 and T2 are turned on. The data read time depends on the thin film transistors T1, T
2 on current. At present, since the current is lower than that of the conventional memory cell by two digits or more, the read time is
become longer. However, it is possible to realize a read time equivalent to that of a conventional memory cell as the manufacturing technology of the thin film transistor advances.

On the other hand, at the time of writing data, the word line WL connected to the selected memory cell is set to the low potential, and the thin film transistors T1 and T2 are turned on. In this state, when the potential of the bit line on the side where the node is desired to be low potential is set to low potential, the potential of the node which was high potential is discharged through the thin film transistor T1 or T2, and the flip-flop circuit is inverted. At this time, the high-potential voltage of the memory cell group connected to the same bit line as the writing cell is lowered. Therefore, this write time must end before the data in the unselected memory cells are destroyed. The on-current of the thin film transistor that determines the writing time needs to be sufficiently larger than the off-current, and the on-current / off-current ratio needs to be 100 or more.

Further, in the memory cell in the non-selected state, the thin film transistors T1 and T2 are turned off, and the bit line BL, through the thin film transistors T1 and T2 in the off state.
The write data is held by the current leaking from / BL.

Normally, a bulk NMOS transistor formed in a silicon substrate has an on-current of 10 ⁻³ A and an off-current of 10 ^−14. It is set to A or less. On the other hand, a thin film transistor has an on-current of 10 ⁻⁶ A and an off-current of 10 ^{−12 in} recent years.
It has characteristics of about A. In order to obtain this off-current, the equivalent resistance when the thin film transistor is off may be set to 1 TΩ. By using such thin film transistors T1 and T2, a current for holding data from the bit line potential near the power supply potential to the flip-flop circuit configured by the NMOS transistors Q1 and Q2 using the thin film transistors T1 and T2 as load resistances. Can be supplied.

According to the static memory cell,
The thin film transistors T1 and T2 are used as a transfer gate and a load resistance. Therefore, since the static memory cell can be configured without using the resistance element, the number of elements can be reduced and the number of power supply wirings and contacts connected to the resistance element can be eliminated. Therefore, the area of the cell can be reduced. FIG. 2 shows a second embodiment of the present invention.

In this embodiment, the P-channel thin film transistors T1 and T2 in the first embodiment are composed of N-channel thin film transistors T3 and T4, and the other structure is the same as that of the first embodiment. In the case of this embodiment, the word line WL is set to a high potential when the memory cell is selected, and the word line WL is set to a low potential when the memory cell is not selected. FIG. 3 shows a third embodiment of the present invention.

In this embodiment, the P-channel thin film transistors T1 and T2 in the first embodiment are double gate type P.
The channel thin film transistors T5 and T6 are used. The thin film transistors T5 and T6 have first and second gates G51, G52, G61 and G6, respectively.
A thin film is provided between the two. The first gates G51 and G61 of the thin film transistors T5 and T6 are connected to the word line WL, respectively. The second gate G52 of the thin film transistor T5 is connected to the node N2,
The second gate G62 of the thin film transistor T6 is connected to the node N1.

In the above structure, the node N1 has a high potential,
Consider a case where the node N2 stores a low potential, that is, "1" data. When the word line is not selected, the thin film transistor T5 is turned on by the second gate G52, and the thin film transistor T6 is turned off by the second gate G62. The equivalent resistance between the node N1 holding the high potential and the bit line BL is small, and the equivalent resistance between the node N2 holding the low potential and the bit line / BL is large.

In this way, the thin film transistors T5 and T6
By changing the resistance value of, the potential of the node holding the high potential can be stabilized, and the current flowing through the thin film transistor connected to the node holding the low potential can be reduced. Therefore, in the case of this embodiment, the power consumption of the memory cell can be reduced.

The write and read operations of the memory cell of this embodiment are similar to those of the first embodiment. In the write operation, the first condition is to prevent the memory cells from being destroyed.
The driving current of the thin film transistor T1 when the gate G51 of the first gate G51 has a low potential and the second gate G52 has a high potential is 100 times higher than the driving current when the first gate G51 has a high potential and the second gate G52 has a low potential. It is necessary to be more than twice as large.

On the contrary, the first gate G51 has a high potential,
The driving current of the thin film transistor T1 when the second gate G52 has a low potential is
Of the thin film transistor T1 when the gate G52 of the
Drive current of 100 times or more. FIG. 4 shows a fourth embodiment of the present invention.

In this embodiment, an N channel thin film transistor and a P channel thin film transistor are combined as a transfer gate and a load resistor. That is, the current paths of the N-channel thin film transistor T7 and the P-channel thin film transistor T8 are connected between the node N1 and the bit line BL, the gate G7 of the N-channel thin film transistor T7 is connected to the word line WL, and the gate channel G7 of the P-channel thin film transistor T8 is connected. The gate G8 is the node N2
It is connected to the. Also, the node N2 and the bit line / BL
The current paths of the N-channel thin film transistor T9 and the P-channel thin film transistor T10 are connected between the
The gate G9 of the N-channel thin film transistor T9 is connected to the word line WL, and the P-channel thin film transistor T10
Gate G10 is connected to the node N1. With the above structure, the cell flip operation similar to that in FIG. 3 can be stabilized, and the write and read operations similar to those in FIG. 2 can be realized. FIG. 5 shows a pattern of the circuit shown in FIG. 3, and FIGS. 6 and 7 respectively show 6 patterns shown in FIG.
FIG. 6 is a cross-sectional view taken along line -6, 7-7.

In FIGS. 5 to 7, the diffusion layer 3 as the source and drain regions is provided inside the P-type semiconductor substrate 30.
1 is provided. A gate oxide film 32 is provided on the semiconductor substrate 30, and a gate G1 of the NMOS transistors Q1 and Q2 is formed on the gate oxide film 32 by the first polysilicon layer 33. An insulating layer 34 is provided on the first polysilicon layer 33, and a second polysilicon layer 35 is provided on the insulating layer 34. One end of the second polysilicon layer 35 is connected to the diffusion layer 31 via the first polysilicon layer 33 at the contact portion C1. A channel region CH of the P-channel thin film transistor TFT5 is provided in a portion of the second polysilicon layer 35 facing the gate G1, and source and drain regions are provided on both sides of the channel region CH. The NMO
The gate G1 of the S transistor Q1 is a thin film transistor T.
It is shared with the second gate G52 of FT5. Although it is possible to separately provide a polysilicon layer for the gate of the thin film transistor TFT5, the polysilicon layer can be reduced by adopting the configuration of this embodiment.

An insulating layer 36 is provided on the second polysilicon layer 35, and a third polysilicon layer 37 is provided on the insulating layer 36. The third polysilicon layer 37 constitutes the first gate G51 and the word line WL of the thin film transistor TFT5.

An insulating layer 38 is provided on the third polysilicon layer 37, and bit lines BL and / BL made of aluminum wiring are provided on the insulating layer 38. The bit lines BL and / BL are connected to the other end of the second polysilicon layer 35 at the contact portion C2.

The first gate G51 is longer than the channel region CH and constitutes an overlap transistor. Further, the second gate G52 is made shorter than the channel length of the channel region CH to form an offset transistor.

Further, the thickness of the insulating layer 34 between the second gate G52 and the second polysilicon layer 35 is equal to that of the insulating layer 36 between the second polysilicon layer 35 and the first gate G51. The first and second gates G5 are made thicker than the thickness
1, the driving force of the thin film transistor T5 is different depending on G52.

6 and 7 show the NMOS transistor Q1.
Also, regarding the P-channel thin film transistor T5, the NMOS transistor Q2 and the P-channel thin film transistor T6 are mirror-projected from FIGS. 6 and 7. FIG. 8 shows a modification of FIG. 8, the same parts as those in FIG. 5 are designated by the same reference numerals.

In FIG. 5, the diffusion layer 31 is used for the power supply line of the ground potential V _SS . On the other hand, in FIG. 8, a polysilicon layer 40 is separately provided, and the polysilicon layer 40 is provided with a diffusion layer 31 through a buried contact (not shown).
It is connected to.

According to the above embodiment, the NMOS transistors Q1 and Q2 and the NMOS transistors Q1 and Q2 are used.
The thin film transistors T1 and T2 having a sufficiently small current driving capability as compared with those of Example 2 are stacked, the thin film transistors T1 and T2 serve as a resistance element and a transfer gate, and the wiring of the power supply potential V _DD is omitted. Therefore, the area of the circuit pattern can be reduced as compared with the conventional case. That is, FIG. 5 and FIG.
Shows the processing technology of 0.5 μm as in FIG. The area of the circuit pattern shown in FIG. 5 is 2.9 × 3.9 =
11.31 μm ² The area of the circuit pattern shown in FIG. 8 is 2.9 × 3.1 = 8.99 μm ² Is. Therefore, FIG.
The area can be reduced by 62% to 49% as compared with the circuit pattern shown in FIG.

FIG. 9 is a sectional view showing the structure of the circuit shown in FIG. The cutting position is the same part as the line 6-6 shown in FIG. 5, the same parts as those in FIGS. 5 and 6 are designated by the same reference numerals, and only different parts will be described.

In the case of this embodiment, the gate G1 of the NMOS transistor Q1 also serves as the gate G8 of the P-channel thin film transistor T8. The second polysilicon layer 35 is provided with the source, drain and channel region CH of the P-channel thin film transistor T8. An insulating layer 51 is provided on the second polysilicon layer 35, and a fourth polysilicon layer 52 is provided on the insulating layer 51. The fourth polysilicon layer 52 is provided with the source, drain and channel region CH of the N-channel thin film transistor T7. One end of the fourth polysilicon layer 52 is connected to one end of the second polysilicon layer 35 at the contact portion C1 and the other end is connected to the second polysilicon layer 35 at the contact portion C2.
Is connected to the other end and the bit lines BL and / BL.
An insulating layer 36 is provided on the fourth polysilicon layer 52, and a third word line is formed on the insulating layer 36.
Of polysilicon layer 37 of FIG. The third polysilicon layer 37 constitutes the gate G7 of the N-channel thin film transistor T7. Also in this embodiment, the area of the circuit pattern can be reduced as in the above-described embodiments.

The embodiments shown in FIGS. 1 and 2 also differ in the number of layers, but when viewed two-dimensionally, the circuit pattern is almost the same as that in FIGS. 5 and 8. Therefore, these embodiments also have substantially the same area as the above-mentioned embodiments.

In the above embodiment, the current paths of the thin film transistors T1 to T10 are made of polysilicon, but the present invention is not limited to this. For example, amorphous silicon or single crystal silicon can be used. . Of course, various modifications can be made without departing from the scope of the invention.

[0045]

As described above in detail, according to the present invention, it is possible to provide a static type memory capable of suppressing an increase in cell area to improve the degree of integration and reducing the manufacturing cost per bit. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

5 is a pattern plan view of the circuit shown in FIG.

6 is a sectional view taken along line 6-6 shown in FIG.

7 is a cross-sectional view taken along the line 7-7 shown in FIG.

FIG. 8 is a pattern plan view showing a modified example of FIG.

9 is a cross-sectional view showing the structure of the circuit shown in FIG.

FIG. 10 is a circuit diagram showing an example of a conventional static memory cell.

11 is a pattern plan view of the circuit shown in FIG.

[Explanation of symbols]

Q1, Q2 ... NMOS transistors, T1, T2, T
5, T6, T8, T10 ... P-channel thin film transistors, T3, T4, T7, T9 ... N-channel thin film transistors, BL, / BL ... Bit line, WL ... Word line.

Claims (13)

[Claims] 1. A first insulated gate transistor of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and a gate of the first insulated gate transistor formed in the semiconductor substrate having a current path. A second insulated gate transistor of a second conductivity type, the gate of which is connected to one end of the first insulated gate transistor and the gate of which is connected to one end of a current passage of the first insulated gate transistor, and the current paths of the first and second insulated gate transistors. A power supply line connected to the other end of the first insulated gate transistor and at least a part of the current line connected to the other end of the first insulated gate transistor, and one end of the current path is connected to one end of the current path of the first insulated gate transistor. A first thin film transistor having the other end of the current path connected to the first bit line and a gate connected to the word line, and above the second insulated gate transistor. If at least some of them are provided in an overlapping manner, one end of the current path is connected to one end of the current path of the second insulated gate transistor, the other end of the current path is connected to a second bit line, and the gate is the word. A second thin film transistor connected to the line, and a static memory. 2. An N-channel MOS transistor is used as each of the first and second insulated gate transistors, and
A P-channel thin film transistor is used as the second thin film transistor, the word line is set to the same potential as the power supply line to make the first and second thin film transistors conductive, and the word line is set to a higher potential than the power supply line. , The second thin film transistor is made non-conductive, and the first and second insulated gates are caused by a leak current when the first and second thin film transistors are non-conductive due to a bit line read potential higher than the potential of the power supply wiring. The static type memory according to claim 1, wherein the transistor holds data. 3. An N-channel MOS transistor is used as the first and second insulated gate transistors, and
An N-channel thin film transistor is used as the second thin film transistor, the word line is set to the same potential as the power supply line to make the first and second thin film transistors non-conductive, and the word line is set to a higher potential than the power supply line. The first and second insulated gates are made conductive by the leakage current when the first and second thin film transistors are non-conductive due to the bit line read potential higher than the potential of the power supply wiring. The static type memory according to claim 1, wherein the transistor holds data. 4. A first insulated gate transistor of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and a gate of the first insulated gate transistor formed in the semiconductor substrate having a current path. A second insulated gate transistor of a second conductivity type, the gate of which is connected to one end of the first insulated gate transistor and the gate of which is connected to one end of a current passage of the first insulated gate transistor, and the current paths of the first and second insulated gate transistors. A power supply line connected to the other end of the first insulated gate transistor and at least a part of the current line connected to the other end of the first insulated gate transistor, and one end of the current path is connected to one end of the current path of the first insulated gate transistor. , The other end of the current path is connected to the first bit line, the first gate is connected to the word line, and the second gate is one end of the current path of the second insulated gate transistor. A first thin film transistor of a first conductivity type connected to the second insulated gate transistor and at least a part of the second insulated gate transistor are provided so as to overlap each other, and one end of the current path is connected to the current path of the second insulated gate transistor. One end of the current path is connected to the second bit line, the first gate is connected to the word line, and the second gate is connected to the first bit line.
And a second thin film transistor of the first conductivity type connected to one end of the current path of the insulated gate transistor. 5. The current flowing when the first and second first thin film transistors are turned on by the first gate is different from the current flowing when the second thin film transistor is turned on by the second gate. The static type memory according to claim 4, wherein the static type memory has a size of 1/100 or less. 6. The second gate of each of the first and second first thin film transistors is shared with the gates of the first and second insulated gate transistors. Static memory. 7. The static type memory according to claim 4, wherein the first and second insulated gate transistors hold data by a leak current when the first and second thin film transistors are non-conducting. . 8. A first insulated gate transistor of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and a gate of the first insulated gate transistor formed in the semiconductor substrate having a current path. A second insulated gate transistor of a second conductivity type, the gate of which is connected to one end of the first insulated gate transistor and the gate of which is connected to one end of a current passage of the first insulated gate transistor, and the current paths of the first and second insulated gate transistors. A power supply line connected to the other end of the first insulated gate transistor and at least a part of the current line connected to the other end of the first insulated gate transistor, and one end of the current path is connected to one end of the current path of the first insulated gate transistor. A second thin film transistor of the second conductivity type having the other end of the current path connected to the first bit line and a gate connected to the word line; and the first insulated gate transistor. And one end of the current path is connected to one end of the current path of the first insulated gate transistor, and the other end of the current path is connected to the first bit line. ,
A second thin film transistor of the first conductivity type whose gate is connected to one end of a current path of the second insulated gate transistor; and at least a part of which is provided above the second insulated gate transistor, Of the second conductivity type, one end of which is connected to one end of the current path of the second insulated gate transistor, the other end of the current path is connected to the second bit line, and the gate of which is connected to the word line. Provided between the second insulated gate transistor and the third thin film transistor, one end of the current path is connected to one end of the current path of the second insulated gate transistor, and the other end of the current path is provided. Is connected to the second bit line,
A fourth thin film transistor of the first conductivity type, the gate of which is connected to one end of the current path of the first insulated gate transistor, and the static type memory. 9. The static memory according to claim 8, wherein the first and second insulated gate transistors retain data by a leak current when the first to fourth thin film transistors are non-conducting. . 10. The static memory according to claim 1, wherein the current paths of the first to fourth thin film transistors are made of an amorphous semiconductor. 11. The static memory according to claim 1, wherein the current paths of the first to fourth thin film transistors are made of a polycrystalline semiconductor. 12. The static memory according to claim 1, wherein the current paths of the first to fourth thin film transistors are made of a single crystal semiconductor. 13. The static memory according to claim 1, wherein the power supply wiring is composed of a diffusion layer provided in a half-body body substrate.