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JPH0581499A - Memory package - Google Patents

Memory package

Info

Publication number
JPH0581499A
JPH0581499A JP3239083A JP23908391A JPH0581499A JP H0581499 A JPH0581499 A JP H0581499A JP 3239083 A JP3239083 A JP 3239083A JP 23908391 A JP23908391 A JP 23908391A JP H0581499 A JPH0581499 A JP H0581499A
Authority
JP
Japan
Prior art keywords
integrated circuit
substrate
memory card
storage elements
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3239083A
Other languages
Japanese (ja)
Inventor
Takeshi Kijino
剛 来住野
Hisashi Ishikawa
久 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Computertechno Ltd
Original Assignee
NEC Corp
NEC Computertechno Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Computertechno Ltd filed Critical NEC Corp
Priority to JP3239083A priority Critical patent/JPH0581499A/en
Publication of JPH0581499A publication Critical patent/JPH0581499A/en
Pending legal-status Critical Current

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  • Credit Cards Or The Like (AREA)

Abstract

PURPOSE:To improve performance such as an access time by providing an integrated circuit, and a memory card where storage elements are mounted on both sides, and plural different-height connectors which connect the memory card and a substrate to the back of a substrate where the integrated circuit is mounted. CONSTITUTION:A memory card 3 which has plural storage element 4 mounted on both its surfaces is controlled by the integrated circuit 1 and a substrate 5 and memory card 3 are connected through plural kind of connectors 2 which are mounted on the substrate 5 and differ in height. Consequently, the space is effectively used to increase the package density. Further, the pattern length from the integrated circuit to the storage elements 4 becomes short, so the skew or delay of the medium is reducible. Namely, the memory card mounted with the storage elements 4 is mounted on the back of the substrate where the integrated circuit is mounted to improve the performance such as the access time and a cycle time.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はメモリーパッケージに関
する。
FIELD OF THE INVENTION This invention relates to memory packages.

【0002】[0002]

【従来の技術】従来、この種のメモリーパッケージは図
2のように基板に集積回路1と記憶素子4が複数個実装
されているSIM6とを実装する構成と、図3(a),
(b)のように基板の表には集積回路1と記憶素子4を
実装し、基板の裏面には、表面の集積回路の実装されて
いる裏を除くスペースを使い記憶素子を実装する構成等
がある。
2. Description of the Related Art Conventionally, a memory package of this type has a structure in which an integrated circuit 1 and a SIM 6 having a plurality of storage elements 4 are mounted on a substrate as shown in FIG.
As shown in (b), the integrated circuit 1 and the memory element 4 are mounted on the front surface of the substrate, and the memory element is mounted on the back surface of the substrate using a space other than the back surface on which the integrated circuit is mounted. There is.

【0003】[0003]

【発明が解決しようとする課題】従来のメモリーパッケ
ージは、基板に実装される記憶素子が多くなると、集積
回路と記憶素子との距離が長くなり、アクセスタイム,
サイクルタイムが大きくなるという欠点がある。
In the conventional memory package, as the number of memory elements mounted on the substrate increases, the distance between the integrated circuit and the memory elements increases, which results in an increase in access time,
There is a drawback that the cycle time becomes large.

【0004】[0004]

【課題を解決するための手段】本発明のメモリーパッケ
ージは、集積回路と、記憶素子を両面に実装させたメモ
リーカードと、前記集積回路の実装されている基板の裏
に前記メモリーカードと基板とを接続させる高さの異な
る複数種類のコネクタとを有している。
A memory package according to the present invention comprises an integrated circuit, a memory card having storage elements mounted on both sides, and the memory card and the substrate on the back of the substrate on which the integrated circuit is mounted. And a plurality of types of connectors having different heights for connecting with each other.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1(a),(b)は本発明の一実施例の断面図お
よび裏面図である。記憶素子4をカードの両面に複数個
実装しているメモリーカード3は集積回路1により制御
され、基板5に実装されている複数種類の高さの異なる
コネクタ2を通して、基板5とメモリーカード3を接続
することにより、空間を有効に使い実装密度を上げるこ
とが可能になり、又、集積回路1から記憶素子4のパタ
ーン長が短くなる為メディアのスキューあるいはディレ
イを小さくする事ができる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 (a) and 1 (b) are a sectional view and a rear view of an embodiment of the present invention. The memory card 3 having a plurality of memory elements 4 mounted on both sides of the card is controlled by the integrated circuit 1, and the substrate 5 and the memory card 3 are mounted on the substrate 5 through the connectors 2 having different heights. By connecting, the space can be effectively used and the packaging density can be increased, and since the pattern length of the integrated circuit 1 to the memory element 4 is shortened, the skew or delay of the medium can be reduced.

【0006】[0006]

【発明の効果】以上説明したように本発明は、記憶素子
を複数個実装しているメモリーカードを集積回路の実装
されている基板の裏に実装することにより、集積回路
と、記憶素子とのパターン長が短くでき信号のディレイ
やスキューを小さくすることが可能になる。よってアク
セスタイム・サイクルタイム等の性能を向上させる事が
できる効果がある。
As described above, according to the present invention, a memory card having a plurality of storage elements mounted thereon is mounted on the back side of a substrate on which the integrated circuit is mounted. The pattern length can be shortened and the signal delay and skew can be reduced. Therefore, there is an effect that the performance such as access time and cycle time can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a),(b)は本発明の一実施例を示す断面
図および裏面図である。
1A and 1B are a sectional view and a rear view showing an embodiment of the present invention.

【図2】従来の第1の例を示す斜視図である。FIG. 2 is a perspective view showing a first conventional example.

【図3】(a),(b)は従来の第2の例を示す上面図
および裏面図である。
3A and 3B are a top view and a back view showing a second conventional example.

【符号の説明】[Explanation of symbols]

1 集積回路 2 コネクタ 3 メモリーカード 4 記憶素子 5 基板 1 integrated circuit 2 connector 3 memory card 4 storage element 5 substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 集積回路を表面に実装したパッケージ
と、記憶素子を複数個実装するメモリーカードと、前記
集積回路のパッケージの裏に前記メモリーカードと前記
パッケージとを接続させる高さの異なる複数種類のコネ
クタとを含むことを特徴とするメモリーパッケージ。
1. A package having an integrated circuit mounted on the surface, a memory card having a plurality of storage elements mounted thereon, and a plurality of types having different heights for connecting the memory card and the package to the back of the package of the integrated circuit. A memory package characterized by including a connector.
JP3239083A 1991-09-19 1991-09-19 Memory package Pending JPH0581499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3239083A JPH0581499A (en) 1991-09-19 1991-09-19 Memory package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3239083A JPH0581499A (en) 1991-09-19 1991-09-19 Memory package

Publications (1)

Publication Number Publication Date
JPH0581499A true JPH0581499A (en) 1993-04-02

Family

ID=17039577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3239083A Pending JPH0581499A (en) 1991-09-19 1991-09-19 Memory package

Country Status (1)

Country Link
JP (1) JPH0581499A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010160647A (en) * 2009-01-07 2010-07-22 Toshiba Corp Semiconductor memory card

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010160647A (en) * 2009-01-07 2010-07-22 Toshiba Corp Semiconductor memory card
US8379393B2 (en) 2009-01-07 2013-02-19 Kabushiki Kaisha Toshiba Semiconductor memory card with controller chip

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