JPH056971A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor memory device with high integration and large capacity, which enables miniaturization of a transistor without deterioration of breakdown voltage between a source and a drain. A first conductivity type semiconductor substrate has a first conductivity type well surrounded by side surfaces and a bottom surface with a second conductivity type well, and a memory cell or an external input circuit is provided on the first conductivity type well. One of them is arranged and the other is provided outside the second conductivity type well region. A predetermined power supply voltage is applied to the second conductivity type well, and a ground level voltage is applied to the first conductivity type well. With this configuration, carriers injected from the external input circuit are absorbed by the second conductivity type well. As a result, carriers are prevented from reaching the memory cell, and data destruction is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which is highly integrated by preventing electron injection.

[0002]

2. Description of the Related Art An example of a conventional semiconductor memory device will be described below.
It will be described with reference to FIG. In FIG. 11, the n channel M
OS (Metal Oxide Semiconductor)
tor) field effect transistor and p-channel MOS
Using a field effect transistor, C (Complement
nary: DRAM (Dy) composed of complementary type MOS
natural Random Access Memor
The structure of y) is shown. In this DRAM, an n well 2 and a p well 3 are formed on a p type semiconductor substrate 1. The n well 2 is fixed to the power supply voltage level V _cc applied in the n type impurity region 4 therein, and the p well 3 is fixed to the substrate voltage level V _BB applied in the p type impurity region 5 therein. There is. A p-channel MOS field effect transistor (hereinafter referred to as “pMOSF”) is formed on the surface of the n-well 2.
6) is formed, and on the surface of the p well 3,
Two n-channel MOS field effect transistors (hereinafter referred to as "nMOSFET") 7a and 7b are formed.

The pMOSFET 6 includes a p-type impurity diffusion region 8 serving as a source / drain region and a gate electrode 10 formed on a channel region sandwiched by the p-type impurity diffusion region 8 via a gate oxide film 9. Composed. The nMOSFETs 7a and 7b are formed on the n-type impurity diffusion regions 11a and 11b serving as source / drain regions and the channel regions sandwiched by the n-type impurity diffusion regions 11a and 11b, respectively, with the gate oxide films 12a and 12b interposed therebetween. It is composed of the gate electrodes 13a and 13b formed as described above.

A general CMOS circuit configured in this way
Then, the source electrode S of the pMOSFET 6₁Is the power supply voltage
Level V_ccIt is connected to the terminal and the source voltage of the nMOSFET.
Pole S ₂Is connected to the ground terminal and is at the ground level potential V
_ssIt is fixed to. There are many nMOSFETs 7b.
One of the memory cells, and its gate electrode 13b
Becomes a word line (WL) and diffuses the two n-type impurities
Regions 11b are storages that are charge storage electrodes.
Node (SN), read / write electrode bit line
(BL). This memory cell has another cross section
Is shown in Fig. 13 (a), which is equivalent to
The circuit is as shown in FIG. Semiconductor
The thick oxide film 14 selectively formed on the substrate 1 allows diffusion.
Areas are being separated.

Next, the operation of the semiconductor memory device configured as described above will be described. Generally, the substrate potential V _BB
For example, a negative potential of about -3V is applied. The reason is as follows. When an input signal from the outside is input to the n-type impurity diffusion region 11a formed in the p-well 3, an undershoot when the signal changes from the "H" level to the "L" level or the input The potential V _BB of the p well 3 may be higher than the potential of the n-type impurity diffusion region 11a because a negative potential is applied as the "L" level. Here, undershoot means that when an external signal is input to the terminal and changes from 5V to 0V, for example, as shown in FIG.
This is a phenomenon in which the voltage becomes a negative level for a moment, as indicated by the arrow A in the figure. Therefore, when V _BB is 0V, electrons are injected because the pn junction between the n-type impurity diffusion region 11a and the p well 3 is in the forward direction. This is electronic injection. By this injection, electrons are injected from the n-type impurity diffusion region 11a toward the p-well, the injected electrons reach the memory cell, and the data in the memory cell is destroyed. In order to prevent such electron injection, V _BB is given a negative potential.

[0006]

However, due to the miniaturization of elements accompanying the increase in capacity of memory, the gate electrodes 10 and 1 are
As the miniaturization of 3a and 13b progresses, there arises a problem that the withstand voltage between the source / drain of the transistor is lowered by giving a negative potential to the substrate potential. That is, p well 3
By applying a negative voltage to the nMOSFET7
The threshold voltage of a and 7b becomes high. If the concentration of the p-type impurity in the channel is lowered in order to suppress the increase in the threshold voltage, the depletion layer easily spreads in the channel,
Punch-through between the source / drain occurs, and the breakdown voltage between the source / drain decreases. Therefore, there is a problem that it is difficult to miniaturize the transistor if the substrate potential is kept negative.

In view of the above conventional problems, the present invention prevents the phenomenon that the data stored in the memory cell is destroyed by the injection of carriers without preventing the breakdown voltage between the source and the drain from occurring. It is an object to provide a highly integrated and large capacity semiconductor memory device.

[0008]

In order to solve the above problems, a semiconductor memory device of the present invention includes a first conductivity type well formed in a semiconductor substrate of the first conductivity type, and the first conductivity type well. A second conductivity type well formed adjacent to the well in the semiconductor substrate, and a second first conductivity type well formed in the second conductivity type well with the bottom surface and the peripheral side surface surrounded by the second conductivity type well. It has a conductive type well and a memory cell formed on the second first conductive type well. Second
A potential of a power supply voltage level of a predetermined polarity is applied to the conductivity type well, and a ground level potential is applied to the first first conductivity type well and the second first conductivity type well.

In another aspect, the semiconductor memory device of the present invention has a second conductivity type well and a first conductivity type well formed therein on a first conductivity type semiconductor substrate. An external input circuit is provided in the well region of the first conductivity type, and the memory cell is arranged outside the well region of the second conductivity type.

According to still another aspect of the semiconductor device of the present invention, two first-conductivity-type wells in which an external input circuit and a memory cell are respectively formed, and bottom surfaces and peripheries of these first-conductivity-type wells, respectively. And a second conductivity type well surrounding the side surface. A potential of a predetermined power supply voltage level is applied to the external input circuit, and a ground level potential is applied to the memory cell. A ground level potential or a predetermined substrate potential is applied to the second conductivity type well.

[0011]

According to the semiconductor memory device of the present invention, the second conductivity type well is formed so as to surround the second first conductivity type well in which the memory cell is formed, and the second conductivity type well has a power source of a predetermined polarity. Since the potential of the voltage level is applied to the first well of the first conductivity type and the well of the second conductivity type of the ground level, the well of the first conductivity type and the well of the second conductivity type are joined. A reverse bias voltage can be applied to the pn junction formed by. Therefore, the carriers injected into the first conductivity type wells or the semiconductor substrate may be replaced with the second carriers.
The conductivity is absorbed by the well, and the insulation at the pn junction prevents carriers from reaching the memory cell. As a result, the data stored in the memory cell is prevented from being destroyed.

Further, in another aspect of the present invention, the external input circuit is provided on the first conductivity type well surrounded by the second conductivity type well, and the memory cell is provided with the second voltage supplied with the potential of the power supply voltage level. By providing the region outside the conductivity type well, carriers injected from the external input circuit into the first conductivity type well are absorbed by the second conductivity type well, and are prevented from reaching the memory cell.

In still another aspect of the present invention, the second conductivity type well surrounds the bottom surface and the peripheral side surface of the two first conductive wells respectively forming the external input circuit and the memory cell, so that the injected carriers can be formed. Reaching the memory cell is prevented.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.
And it demonstrates based on FIG. FIG. 1 shows an embodiment in which the present invention is applied to a DRAM including CMOS.
Referring to FIG. 1, the semiconductor memory device of the present embodiment has a first n-well 2a formed on a p-type semiconductor substrate 1 of the first conductivity type.
And a first p-well 3a, a second n-well 2b and a second p-well 3b surrounded by the same. Both the first n-well 2a and the second n-well 2b have n
Positive power supply voltage level V _cc via the impurity diffusion region 4
Is being applied.

An nMOSFE is formed on the first p-well 3a.
T7a has a pMOSFET 6 on the first n-well 2a.
Are formed, and the nMOSFET 7a and the pMOSFET 6 form a CMOS as a peripheral circuit of the DRAM of this embodiment. The pMOSFET 6 is mainly a source /
A p-type impurity diffusion region 8 serving as a drain region and a source /
The gate electrode 10 is formed on the channel region between the drains via the gate insulating film. Also,
The nMOSFET 7a serves as a source / drain region n
The type impurity diffusion region 11a and the gate electrode 13a formed on the channel region between the source / drain regions with the gate insulating film 12a interposed therebetween.

On the second p-well 3b surrounded by the second n-well 2b, nM constituting a memory cell of DRAM is formed.
The OSFET 7b is formed. This nMOSFET
7b is mainly composed of an n-type impurity diffusion region 11b serving as a source / drain region, and a gate electrode 13b formed on a channel region between the source / drain regions via a gate insulating film 12b.

The first n-well 2a and the second n-well 2
b is a positive power supply voltage via the impurity diffusion region 4.
Level V_ccIs being applied. Also, the first p-well 3
a and the second p-well 3b are both p-type impurity diffusion regions.
Ground level V via zone 5 _ssIs being applied. Each element
The child is separated and insulated by the oxide film 14.

According to this embodiment, since it has the above structure, the second p-well 3b fixed at the ground level V _ss is used.
And the second n-well 2 fixed to the power supply voltage level V _cc
A reverse bias has already been applied to the pn junction formed at the boundary with b. Therefore, for example, the second p
The potential of the n-type impurity diffusion region 11b in the well 3b is undershooted when the input signal changes from “H” to “L”, or a negative potential is given as an input “L” level, so that a negative potential is given. Potential, which is lower than the ground level V _ss . As a result, the n-type impurity diffusion region 1
Even if injection of electrons from the 1b to the p-well 3b occurs, the injected electrons are absorbed by the second n-well 2b fixed at V _cc , as shown in FIG. Further, since the electrons are prevented from reaching the memory cell due to the insulation by the pn junction, it is possible to prevent the data stored in the memory cell from being destroyed.

Further, since the potentials of the first p-well 3a and the second p-well 3b are fixed to the ground level V _ss , the nMOS is as if a negative potential was applied.
The threshold voltage of the FET 7b does not increase, and therefore it is not necessary to reduce the p-type impurity concentration in the channel region. As a result, miniaturization is possible while maintaining the source / drain breakdown voltage of the nMOSFETs 7a and 7b.

In the above embodiment, the nMOSFET 7b is formed on the second p well 3b surrounded by the n type well.
Although the case of forming a memory cell including is described, even when all of these conductivity types are reversed, the polarity of V _cc is reversed, and the injected carriers only change from electrons to holes. ， The effects are common.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 to 10, the same or corresponding elements as those shown in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

In the first embodiment, the nMOSFET 7b forming the memory cell is provided in the region of the second p-well 3b formed inside the second n-well 2b, so that the second n-well 2b is formed. While preventing the destruction of the data in the memory cell due to the injection of electrons from outside,
In the second embodiment, nM which constitutes an external input circuit
By providing the OSFET in a region within the second p-well 3b formed inside the second n-well 2b, the second by the injection of electrons from this external input circuit,
Of the n-well 2b outside the memory cell (nMOS
The destruction of the data of the FET 7b) is prevented.

Of the second embodiment, first, in the structure shown in FIG. 3, pMOSFET 6, nMOSFET 7a,
7b has the same arrangement as that of the conventional example shown in FIG.
By pre-isolating only the MOSFET 7c, the influence on the memory cell is eliminated.

Referring to FIG. 4, the nMOSFET 7c is
N-type impurity diffusion region 11c to be a source / drain region
And a gate electrode 13c formed on the channel region sandwiched by the n-type impurity diffusion regions 11c with a gate oxide film 12c interposed therebetween. The external input circuit actually includes a plurality of nMOSFETs, but in FIG.
Only c is shown as a representative. The source terminal s ₃ , drain terminal d ₃ and gate terminal g _{3 of the} nMOSFET 7c
Among them, the source terminal s ₃ is electrically connected to an external input terminal (not shown).

Next, the operation of the structure shown in FIG. 3 of this embodiment will be described. Second p with nMOSFET 7c
The well 3b is fixed to the ground level V _ss or a predetermined negative substrate potential V _BB . The second p-well 3b is V _ss
If the potential of the n-type impurity diffusion region 11c in the second p-well 3b is fixed, the undershoot at the time when the input signal changes from "H" to "L" or the input signal L By applying a negative potential as the level, the potential becomes lower than the ground level V _ss , and even if electrons are injected from the n-type impurity diffusion region 11c into the second p well 3b, the second p well 3b
The second n-well 2b surrounding the power supply potential Vcc
Is fixed to the second n
It is absorbed in the well 2b. Therefore, the injected electrons do not reach the nMOSFET 7b forming the memory cell, and the stored data is not destroyed. When the second p-well 3b is fixed to a predetermined negative substrate potential V _BB , even if a negative potential whose absolute value is smaller than V _BB is applied as an external input, the pn junction is forward-directed. Since no bias is applied, the electron injection is suppressed. Even if injection occurs, it does not reach the memory cell because it is surrounded by the n well 2b fixed to V _CC .

In addition, the first p-well 3a and the second p-well 3a
Since the well 3b is fixed to the ground level V _ss , there is no problem as in the case of applying a negative potential as in the conventional example. Therefore, nMOSFET 7a,
While maintaining the source / drain breakdown voltage of 7b and 7c, miniaturization for high integration becomes possible.

In the case of the present embodiment as well, even when the conductivity types are all reversed, the polarity of V _cc is reversed and the injected carriers only change from electrons to holes. The effect is similar to that of the first embodiment.

In the above structure shown in FIG. 3,
Both nMOSFETs 7a and 7b are the first p-well 3a
Is formed in the nMOSFETs 7a, 7
Either or both of b, for example, FIGS.
Also, as shown in FIG. 6, by directly forming the well on the p-type semiconductor substrate 1 in a region where no well is formed, the same effect as the structure of FIG. 3 can be obtained. In the structure shown in FIG. 4, the nMOSFET 7b (memory cell) is directly formed in a region on the p-type semiconductor substrate 1 in which a well is not formed, and the rest is the same as in FIG. In the structure shown in FIG. 5, the nMOSFET 7a is directly formed in the region on the p-type semiconductor substrate 1 in which the well is not formed, and the rest is the same as in FIG. In the structure shown in FIG. 6, both of the nMOSFETs 7a and 7b are directly formed on the region of the p-type semiconductor substrate 1 in which no well is formed, and the others are the same as in FIG.

Further, in the structure shown in FIGS. 3 to 6, the first n-well region 2a and the second n-well region 2b are formed separately, but the external input circuit is formed as shown in FIG. 10 to 10, it may be formed on the second p-type well 3b formed inside the first n-well 2, and depending on their structure, the structure shown in FIGS. The same effect can be obtained. 7 to 10
In the structure shown in FIG. 3, the second p-well 3b provided with the nMOSFET 7c is formed in the first n-well 2, but the other structures are shown in FIGS.
It is similar to the structure shown in.

Next, a third embodiment of the present invention will be described with reference to FIG. In the embodiment shown in FIG.
A memory cell 7b is formed on the first p-well 3a, and an external input circuit 7c is formed on the second p-well 3b. Each bottom surface and peripheral side surfaces of the first p-well 3a and the second p-well 3b are It is surrounded by the first n-well 2a and the second n-well 2b. The ground level V _SS or a predetermined negative substrate potential V _BB is applied to the second p well 3b through the p type impurity region 5.

According to the structure of this embodiment, as in the case of the second embodiment, even if the injection of electrons from the external input circuit 7c into the second p-well 3b occurs,
Since the electrons are absorbed in the second n-well 2b, the electrons do not reach the memory cell 7b. Therefore, destruction of data in the memory cell 7b is prevented.

[0032]

As described above, according to the present invention, the double-well structure in which the first conductivity type well forming the memory cell is surrounded by the second conductivity type well, and the second conductivity type well is Applying a power supply voltage level potential, applying a ground level potential to the first conductivity type well, and applying a reverse bias voltage to the pn junction formed by the first conductivity type well and the second conductivity type well. As a result, even if carrier injection occurs outside the second conductivity type well,
The carriers are absorbed in the second conductivity type well and do not enter the first conductivity type well. Therefore, the phenomenon that the data stored in the memory cell is destroyed by the injection of carriers can be prevented without applying a high potential to the second conductivity type well. Therefore, the transistor can be miniaturized without deterioration of the withstand voltage between the source / drain, and a semiconductor memory device with high integration and large capacity can be provided.

Further, the second conductive film is formed on the first conductive type semiconductor substrate.
A first conductivity type well is formed inside the conductivity type well, and an external input circuit is arranged on the first conductivity type well.
By providing the memory cell outside the region of the second conductivity type well, it is possible to prevent the injected carriers from reaching the memory cell, and it is possible to provide a semiconductor memory device having the same effect as described above.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a DRAM according to a first embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view showing another cross section in the vicinity of the memory cell of the DRAM shown in FIG.

FIG. 3 shows a semiconductor device according to a second embodiment of the present invention,
It is sectional drawing which shows a 1st aspect.

FIG. 4 shows a semiconductor device according to a second embodiment of the present invention,
It is sectional drawing which shows a 2nd aspect.

FIG. 5 shows a semiconductor device according to a second embodiment of the present invention,
It is sectional drawing which shows the 3rd aspect.

FIG. 6 shows a semiconductor device according to a second embodiment of the present invention,
It is sectional drawing which shows the 4th aspect.

FIG. 7 shows a semiconductor device according to a second embodiment of the present invention,
It is sectional drawing which shows the 5th aspect.

FIG. 8 shows a semiconductor device according to a second embodiment of the present invention,
It is sectional drawing which shows the 6th aspect.

FIG. 9 shows a semiconductor device according to a second embodiment of the present invention,
It is sectional drawing which shows a 7th aspect.

FIG. 10 is a sectional view showing an eighth mode of a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the structure of a conventional DRAM.

FIG. 12 is a diagram for explaining a phenomenon of undershoot.

13A is a view showing another cross section in the vicinity of the memory cell of the conventional DRAM shown in FIG. 3, and FIG.
FIG. 4 is an equivalent circuit diagram of the memory cell shown in (a).

FIG. 14 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention.

[Description of Reference Signs] 1 semiconductor substrate 2a first n-well 2b second n-well (first conductivity type well) 3a first p-well (first second conductivity type well) 3b second p-well ( Second second-conductivity-type well) 7b nMOSFET (memory cell) In the drawings, parts denoted by the same reference numerals indicate the same or corresponding elements.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shigeru Kikuta             4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric             LSI Research Institute Co., Ltd. (72) Inventor Hiroshi Miyamoto             4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric             LSI Research Institute Co., Ltd. (72) Inventor, Koichi Morooka             4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric             LSI Research Institute Co., Ltd.

Claims (3)

[Claims] 1. A first first conductivity type well formed in a first conductivity type semiconductor substrate, and a second conductivity formed in the semiconductor substrate adjacent to the first first conductivity type well. -Type well, a second first-conductivity-type well formed in the second-conductivity-type well by surrounding the bottom surface and the peripheral side surface of the second-conductivity-type well, and the second first-conductivity-type well A memory cell formed on the second conductivity type well, a potential of a power supply voltage level having a predetermined polarity is applied to the second conductivity type well, and the first first conductivity type well and the second first type well are provided.
A semiconductor memory device in which a conductivity type well is supplied with a ground level potential. 2. A semiconductor memory device comprising a semiconductor substrate of a first conductivity type and a memory cell and an external input circuit formed on a main surface of the semiconductor substrate, the semiconductor memory device being near a surface of the semiconductor substrate. Has a second-conductivity-type well and a first-conductivity-type well formed inside the second-conductivity-type well, and the external input circuit is provided on the region of the first-conductivity-type well. The memory cell is provided outside the region of the well of the second conductivity type, the potential of a predetermined power supply voltage level is applied to the well of the second conductivity type, and the well of the second conductivity type is applied to the well of the first conductivity type. Is a semiconductor memory device to which a ground level potential or a predetermined substrate potential is applied. 3. A first first conductivity type well formed in a first conductivity type semiconductor substrate, and a second first conductivity type well formed in the vicinity of the first first conductivity type well. Formed on the first first conductivity type well, and a second conductivity type well surrounding the bottom surface and the peripheral side surface of each of the first first conductivity type well and the second first conductivity type well. An external input circuit and a memory cell formed on the second first conductivity type well are provided, and a potential of a predetermined power supply voltage level is applied to the second conductivity type well, and the second first conductivity type well is provided.
A semiconductor memory device in which a conductivity type well is supplied with a ground level potential, and the first first conductivity type well is supplied with a ground level potential or a predetermined substrate potential.