JPH056409A - Logic circuit generation device and logic circuit generation method - Google Patents

Abstract

(57) [Summary] [Purpose] To enable automatic generation of logic circuits with sufficiently high testability and with little increase in cost due to test circuits. [Structure] A logic synthesizing means 1 for synthesizing a logic circuit satisfying a given function based on an input function description, and a logic circuit synthesized by the logic synthesizing means 1 are analyzed to generate a test vector for fault detection. The logic level test vector generating means 2 for generating the fault detection rate and the testability analysis result of the generated test vector, and whether or not the fault detection rate output by the logic level test vector generating means 2 is sufficiently high. And the synthesizing means based on the testability analysis result output from the logic level test vector generating means 2 when the failure detecting rate is found to be insufficient by the deciding means 3. And circuit conversion means 4 for transforming the logic circuit synthesized by 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic logic synthesis technique for automating the design of a logic circuit, and more particularly to a logic circuit generation device and a logic circuit generation method for generating a testable logic circuit.

[0002]

2. Description of the Related Art In a typical conventional logic circuit generator,
The testability of the generated logic circuit is usually not particularly considered. Therefore, the testability is often insufficient as it is, and it is necessary to modify the circuit after the logic design is completed.

FIG. 22 shows a process flow chart of a typical test design. The test design follows the logic design.
In the figure, reference numeral 41 denotes a step of inserting a test circuit into a logic circuit generated by a logic circuit generation device or manually designed. A typical example is the insertion of a scan path. This step may be performed manually or may be automatically performed by a computer. 42 is a step of analyzing the logic circuit in which the test circuit is inserted and creating a test vector.
This step may be manually executed based on the test vector for logic verification, or may be automatically executed on the computer. Reference numeral 43 is a step of evaluating a fault coverage by performing a fault simulation on the logic circuit in which the test circuit is inserted using the test vector.
Step 44 is a step of judging whether or not the failure detection rate is sufficiently high. If the judgment result shows that the fault coverage is sufficiently high, the test design is finished. If it is found that the fault coverage is insufficient, the process returns to the test vector creating step 42 to add a test vector again, or the process returns to the test circuit inserting step 41 to modify the logic circuit.

FIG. 23 shows a block diagram of a first example of a conventional logic circuit generation device in consideration of testability. In the figure, 51 is a logic synthesizing means for synthesizing a logic circuit satisfying a given function based on the input function description, 52
Is a scan path inserting means for inserting a test scan path into the logic circuit synthesized by the logic synthesizing means 51, and 53 is a circuit optimizing means for removing redundancy of the logic circuit generated by inserting the scan path.

The scan path inserting means 52 replaces the flip-flops included in the logic circuit with scan path flip-flops having a shift register function, and connects them in order to form one scan path. Also, a scan data input / output port and a scan clock input port are inserted. It is known that the logic circuit having the scan path inserted therein can be easily tested by setting or reading data in the flip-flop through the scan path during the test.

FIG. 24 shows a block diagram of a second example of a conventional logic circuit generation device in consideration of testability. In the figure, reference numeral 61 is a function level testability analysis means for analyzing the testability of the circuit at the function level based on the input function description, and 62 is based on the obtained analysis result.
If necessary, a function level scan path inserting means for modifying the original function description to include the scan path, and 63 is a logic synthesizing means for synthesizing a logic circuit from the function description to which the scan path is added in this way.

Since the logic circuit generated by the logic circuit generating device of the second conventional example (FIG. 24) includes the scan path as in the first conventional example (FIG. 23), the test is easy. Is. Furthermore, since the scan path is inserted only when necessary based on the testability analysis result at the functional level, the cost required for the test circuit is less than that of the first conventional example. There is also.

[0008]

When using a conventional logic circuit generator which does not consider testability,
It is necessary for the designer to consider testability at the stage of creating the functional description of the input. However, since it is difficult to know the testability of the circuit generated from it at the functional level, there is no guarantee that a high fault coverage will be obtained with this device.

Further, according to the method of inserting the test circuit into the generated logic circuit according to the typical test design flow shown in FIG. 22, it is difficult for the designer to correct the automatically generated logic circuit. Also, when a test circuit is automatically inserted by a computer, mechanical replacement that considers only testability may cause redundancy in the converted logic circuit, or design constraints that were satisfied before conversion. There was a problem that was not satisfied.

Further, in the first conventional example of the logic circuit generation device considering the testability shown in FIG. 23, the testability of the synthesized logic circuit is not analyzed.
All the flip-flops must be replaced with scan-path flip-flops, which causes a problem that the cost of the generated logic circuit increases significantly.

Further, in the second conventional example of the logic circuit generation device considering the testability shown in FIG. 24, the testability is evaluated not at the logic level but at the function level, but the logic generated at the function level is generated. Since it is difficult to accurately analyze the testability of the circuit, there are problems that a sufficiently high fault coverage cannot be obtained, and the cost increase associated with the test circuit becomes too large.

In view of the above points, the present invention has an object to enable automatic generation of a logic circuit having a sufficiently high testability and having a small increase in cost due to a test circuit.

[0013]

In order to achieve the above-mentioned object, the logic circuit generating device of the invention of claim 1 has a function given based on an inputted function description as shown in FIG. The logic synthesizing means 1 for synthesizing the logic circuits to be satisfied and the logic circuit synthesized by the logic synthesizing means 1 are analyzed to generate a test vector for fault detection, and the fault detection rate and testability analysis of the generated test vector are performed. The logic level test vector generating means 2 for outputting the result, the judging means 3 for judging whether or not the fault detection rate output by the logic level test vector generating means 2 is sufficiently high, and the fault detecting rate is judged by the judging means 3. If it is found to be insufficient, the logic synthesized by the logic synthesizing means 1 based on the testability analysis result output by the logic level test vector generating means 2. It is obtained by a circuit converting means 4 for deforming the road.

Further, as shown in FIG. 2, the logic circuit generation device according to the second aspect of the present invention includes logic synthesizing means 1 for synthesizing a logic circuit satisfying a given function based on the input function description. A functional level test vector generating means 5 for generating a test vector for fault detection from the input functional description, and a logic circuit synthesized by the logic synthesizing means 1 using the test vector generated by the functional level test vector generating means 5. A failure simulation is performed for the test vector, and the failure simulation unit 6 that outputs the failure detection rate of the test vector and the testability analysis result, and the determination that determines whether or not the failure detection rate that the failure simulation unit 6 outputs is sufficiently high If the failure detection rate is found to be insufficient by the means 3 and the determination means 3, the failure simulation is performed. In which the based on testability analysis results stage 6 has an output logic synthesis unit 1 and a circuit converting means 4 for modifying the logic circuit synthesis.

Further, as shown in FIG. 3, the logic circuit generation device according to the third aspect of the present invention includes logic synthesizing means 1 for synthesizing a logic circuit satisfying a given function based on the input function description. Functional level test vector generation means 5 for generating a first test vector for fault detection from the input functional description.
And the first test vector generated by the functional level test vector generating means 5 is used to perform a failure simulation on the logic circuit synthesized by the logic synthesizing means 1 to obtain a first fault relating to the first test vector. Fault simulation means 6 for outputting a detection rate and an undetected fault list
And a determination means 3 for determining whether or not the failure detection rate is sufficiently high, and when it is determined by the determination means 3 that the first failure detection rate output by the failure simulation means 6 is insufficient. The logic circuit synthesized by the logic synthesizing unit 1 is analyzed based on the undetected fault list output by the fault simulating unit 6 to generate a second test vector for fault detection, and the generated second test vector is generated. Logic level test vector generation means 2 for outputting a second fault coverage and testability analysis result in the case of combining the test vector and the first test vector, and the logic level test vector generation by the judgment means 3. When it is found that the second fault coverage output by the means 2 is insufficient, the test output by the logic level test vector generating means 2 is output. The Tabiriti analysis results in which the based logic synthesis unit 1 and a circuit converting means 4 for modifying the logic circuit synthesis.

Further, as shown in FIG. 4, the logic circuit generating method of the invention of claim 4 comprises a logic synthesizing step 132 for synthesizing a logic circuit satisfying a given function based on the input function description. A logic level test vector generating step 133 for analyzing the logic circuit synthesized in the logic synthesizing step 132 to generate a test vector for fault detection and outputting a fault coverage and a testability analysis result of the generated test vector. , A judgment step 134 for judging whether or not the failure detection rate output in the logic level test vector generation step 133 is sufficiently high, and if it is found in this judgment step 134 that the failure detection rate is insufficient, , The logic circuit synthesized in the logic synthesis step 132 is output in the logic level test vector generation step 133 Restricted to the part that causes the test difficulty obtained from the testability analysis result, it is modified for testability, and circuit optimization for eliminating redundant parts and circuit adjustment for satisfying design constraints are performed. And a circuit conversion step 136 to be performed.

According to a fifth aspect of the logic circuit generating method of the present invention, as shown in FIG. 5, a logic synthesizing step 132 for synthesizing a logic circuit satisfying a given function based on the input functional description, A function level test vector generation step 138 for generating a test vector for fault detection from the input function description, and a synthesis in the logic synthesis step 132 using the test vector generated in the function level test vector generation step 138 A failure simulation is performed on the logic circuit, and a failure simulation step 139 for outputting the failure detection rate of the test vector and a testability analysis result and whether or not the failure detection rate output in the failure simulation step 139 is sufficiently high. Judgment step 134 and the failure detection in this judgment step 134. If it is found that the ratio is insufficient, the logic circuit synthesized in the logic synthesis step 132 is limited to a portion that causes a test difficulty obtained from the testability analysis result output in the failure simulation step 139. Then, the circuit conversion step 136 is performed, which is modified for testability, and which performs circuit optimization for eliminating redundant parts and circuit adjustment for satisfying design constraints.

Further, as shown in FIG. 6, the logic circuit generating method according to the invention of claim 6 comprises a logic synthesizing step 132 for synthesizing a logic circuit satisfying a given function based on the input function description. A functional level test vector generation step 138 for generating a first test vector for fault detection from the input functional description, and the logic synthesis using the first test vector generated in the functional level test vector generation step 138. A failure simulation is performed on the logic circuit synthesized in step 132, and a failure simulation step 139 of outputting a first failure detection rate and an undetected failure list for the first test vector, and an output of this failure simulation step 139. First determination step 13 for determining whether the detected first failure detection rate is sufficiently high And a, the first determination step 13
If it is found that the first fault coverage is insufficient in 4a, the logic circuit synthesized in the logic synthesis step 132 is determined based on the undetected fault list output in the fault simulation step 139. A second test vector for failure detection is analyzed to generate a second failure detection rate and a testability analysis result regarding the case where the generated second test vector and the first test vector are combined. A logic level test vector generation step 133 for outputting, a second determination step 134b for determining whether or not the second failure detection rate output in this logic level test vector generation step 133 is sufficiently high, and a second determination step 134b If it is found in the judgment step 134b that the second failure detection rate is insufficient, it is combined in the logic combining step 132. The limited logic circuit is limited to a portion that causes a test difficulty obtained from the testability analysis result output in the logic level test vector generation step 133, and is modified for test facilitation, and the redundant portion is deleted. And circuit conversion step 136 for performing circuit optimization and circuit adjustment for satisfying design constraints.

[0019]

As a result, in the logic circuit generating apparatus according to the first aspect of the present invention, the logic synthesizing means 1 uses the input functional description.
The logic circuit thus synthesized is analyzed by the logic level test vector generation means 2 to evaluate the fault coverage. Then, the judging means 3 judges whether or not the fault detection rate is sufficiently high, and if it is sufficiently high, the logic circuit synthesized by the logic synthesizing means 1 is output as it is together with the test vector generated by the logic level test vector generating means 2. To do. If the fault coverage is insufficient, the circuit converting means 4 is applied to the logic circuit synthesized by the logic synthesizing means 1 based on the testability analysis result output by the logic level test vector generating means 2. Since circuit conversion is performed to improve testability, a testable logic circuit can be generated.

Further, in the logic circuit generating device of the present invention, the logic circuit synthesized by the logic synthesizing means 1 from the input function description, the function level test vector generating means 5 from the input function description. Fault simulation using the test vector generated by
The fault coverage is evaluated. Then, the judging means 3 judges whether or not the failure detection rate is sufficiently high, and if it is sufficiently high, the logic circuit synthesized by the logic synthesizing means 1 is used as it is along with the test vector generated by the function level test vector generating means 5. Output. If the fault coverage is insufficient, the circuit conversion unit 4 determines the testability of the logic circuit synthesized by the logic synthesis unit 1 based on the testability analysis result output by the fault simulation unit 6. Since the circuit conversion for improvement is performed, it becomes possible to generate a logic circuit that is easy to test.

Further, in the logic circuit generating apparatus according to the third aspect of the present invention, the logic circuit synthesized by the logic synthesizing means 1 from the input function description is converted into the function level test vector generating means 5 from the input function description. A fault simulation is performed using the first test vector generated by, and the first fault coverage is evaluated. Then, the judging means 3 judges whether or not the first failure detection rate is sufficiently high, and if it is sufficiently high, the functional level test vector generating means 5 generates the logic circuit synthesized by the logic synthesizing means 1 as it is. Output with test vector. If the first fault coverage is insufficient, the logic level test vector generation means 2 based on the undetected fault list output by the fault simulation means 6 causes the logic synthesized by the logic synthesis means 1 to be combined. A circuit is analyzed to generate a second test vector that complements the first test vector, and a second fault coverage is evaluated when the first test vector and the second test vector are combined. To be done. Then, the judging means 3 judges whether or not the second fault detection rate is sufficiently high. If the second failure detection rate is sufficiently high, the logic circuit synthesized by the logic synthesizing means 1 is used as it is together with the first and second test vectors. Output. If,
If the second failure detection rate is insufficient, the circuit conversion means for the logic circuit synthesized by the logic synthesis means 1 based on the testability analysis result output by the logic level test vector generation means 2. Since 4 performs circuit conversion for improving testability, a testable logic circuit can be generated.

Further, in the logic circuit generating method according to the present invention, the logic circuit synthesized from the input functional description in the logic synthesizing step 132 is analyzed in the logic level test vector generating step 133, and the fault detection rate is detected. Is evaluated. Then, in the judgment step 134, it is judged whether or not the fault detection rate is sufficiently high. If the failure detection rate is sufficiently high, the logic circuit synthesized in the logic synthesis step 132 is used as it is together with the test vector generated in the logic level test vector generation step 133. Output. If the fault coverage is insufficient, the logic circuit synthesized in the logic synthesizing step 132 causes a test difficulty obtained from the testability analysis result output in the logic level test vector generating step 133. In the circuit conversion step 136, the circuit conversion step 136 is modified for testability, and circuit optimization for eliminating redundant parts and circuit adjustment for satisfying design constraints are performed. However, it is possible to generate a logic circuit that is not redundant and that satisfies the design constraint.

Further, in the logic circuit generating method according to the present invention, the logic circuit synthesized in the logic synthesizing step 132 from the input functional description is generated from the input functional description in the function level test vector generating step 138. A fault simulation is performed by using the test vector generated in (1), and the fault coverage is evaluated. And determination step 1
At 34, it is judged whether or not this fault detection rate is sufficiently high. If it is sufficiently high, the logic circuit synthesized at the logic synthesis step 132 is output as it is together with the test vector generated at the function level test vector generation step 138. If the fault coverage is insufficient, the logic circuit synthesized in the logic synthesizing step 132 is limited to a portion which causes a test difficulty obtained from the testability analysis result output in the fault simulating step 139. Then, in the circuit conversion step 136, the circuit is modified for testability, and the circuit optimization for eliminating the redundant portion and the circuit adjustment for satisfying the design constraint are performed.
It is possible to generate a logic circuit that has sufficiently high testability, is not redundant, and satisfies the design constraint.

Further, in the logic circuit generating method of the present invention, the logic circuit synthesized in the logic synthesizing step 132 from the input functional description is generated from the input functional description in the functional level test vector generating step 138. A fault simulation is performed using the first test vector generated in step S1 to evaluate the first fault coverage. Then, in a first determination step 134a, it is determined whether or not this first failure detection rate is sufficiently high. If it is sufficiently high, the logic circuit synthesized in the logic synthesis step 132 is left as it is, and the functional level test vector generation step 138. Output with the test vector generated in. If the first fault coverage is insufficient, it is synthesized in the logic synthesis step 132 in the logic level test vector generation step 133 based on the undetected fault list output in the fault simulation step 139. The logic circuit is analyzed to generate a second test vector that complements the first test vector, and a second failure detection rate is obtained when the first test vector and the second test vector are combined. To be evaluated. Then, in a second determination step 134b, it is determined whether or not the second fault detection rate is sufficiently high. If it is sufficiently high, the logic circuit synthesized in the logic synthesis step 132 is left as it is, and the first and second tests are performed. Output with vector. If the second fault coverage is insufficient, the reason why the logic circuit synthesized in the logic synthesizing step 132 is the test difficulty obtained from the testability analysis result output in the logic level test vector generating step 133 is caused. In the circuit conversion step 136,
While transforming for testability, it performs circuit optimization for eliminating redundant parts and circuit adjustment for satisfying design constraints, so while having sufficiently high testability,
It is possible to generate a logic circuit that is not redundant and that satisfies the design constraint.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Three embodiments will be sequentially described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of a logic circuit generating apparatus according to the first aspect of the present invention. In the figure, 1 is a logic synthesizing means for synthesizing a logic circuit satisfying a given function based on the input function description, and 2 is a test for detecting a failure by analyzing the logic circuit synthesized by the logic synthesizing means 1. A logic level test vector generating means for generating a vector and outputting a fault detection rate of the generated test vector and an undetected fault list as a testability analysis result, 3 is a fault output by the logic level test vector generating means 2. The judging means 4 for judging whether or not the detection rate is sufficiently high, the undetected failure list outputted by the logic level test vector generating means 2 when the judging means 3 finds that the failure detection rate is insufficient. It is a circuit conversion means for modifying the logic circuit synthesized by the logic generation means 1 based on the above.

Reference numeral 10 is the logic synthesizing means 1, the logic level test vector generating means 2, the judging means 3 and the circuit converting means 4.
A program execution unit that stores a logic circuit generation program for realizing each function of the program and executes the program as necessary, 11 supports the creation of the function description, and the created function description is executed by the program execution unit 10 Input section to pass to, 1
Reference numeral 2 denotes an output unit that converts the logic circuit generated by the program execution unit 10 into a usable form such as a logic diagram or netlist and outputs the output. Reference numeral 13 temporarily stores intermediate data generated by the program execution unit 10. Working storage for, 14
Is a knowledge storage unit for storing the logic synthesis knowledge referred to by the logic synthesis means 1 and the circuit conversion knowledge referred to by the circuit conversion means 4.

The operation of this embodiment configured as described above will be described below. First, the logic circuit synthesized by the logic synthesizing means 1 from the input functional description and design constraint is analyzed by the logic level test vector generating means 2 to evaluate the fault coverage. And the judging means 3
Judges whether the fault detection rate is sufficiently high. If it is sufficiently high, the logic circuit synthesized by the logic synthesizing means 1 is output as it is together with the test vector generated by the logic level test vector generating means 2. If the failure detection rate is insufficient as a result of the determination by the determination means 3, the logic synthesis means is based on the undetected failure list as the testability analysis result output by the logic level test vector generation means 2. The circuit converting means 4 performs circuit conversion for improving the testability on the logic circuit synthesized by 1 to generate a testable logic circuit.

The testable logic circuit is analyzed again by the logic level test vector generating means 2 to evaluate the fault coverage. Is it possible to obtain a sufficiently high fault coverage?
The above processing is repeated until the number of repetitions exceeds the maximum value. Further, as a result of the circuit conversion, when the given design constraint cannot be satisfied, the parameters related to the logic synthesis are changed, the process returns to the logic synthesis means 1 again, and the logic circuit is set to the new parameter. It can also be re-synthesized under.

FIG. 4 shows the processing flow of the above embodiment. This figure also shows the configuration of an embodiment of the logic circuit generating method according to the invention of claim 4.

Now, the respective processes of the logic synthesis, the logic level test vector generation, the judgment and the circuit conversion of this embodiment will be described in more detail in order below.

(Logic Synthesizing Process) FIG. 7 shows an example of a function description in a hardware description language which is an input to the logic circuit generator of this embodiment. With a hardware description language,
The behavior of a logic circuit can be described using a high-level language-like syntax of software. In the description example of FIG. 7, when the 2-bit signal a is 0, 0 is substituted for the signal r, and when the signal a is 1, the value of the signal d is substituted for the signal r, and the signal a is 2
In the case of, the operation of the circuit that substitutes the value of the signal e into the signal r is expressed.

FIG. 8 shows a processing flow chart of the logic synthesizing means 1 in this embodiment. In the figure, 71 is a parsing step for parsing a functional description depending on a language and converting it into a parse tree corresponding to the description, and 72 is an abstract logic level circuit independent of technology from the obtained parse tree. A logic level circuit generation step 73 for generating is a technology mapping step for converting a logic level circuit into a logic circuit satisfying the constraint of a specific technology.

FIG. 9 is a logic diagram showing a logic circuit generated by the logic synthesizing means 1 of this embodiment, using the example of the function description of FIG. 7 as an input. Here, the logic circuit is represented by interconnecting cells included in a specific cell library.

In the logic synthesizing means 1 of this embodiment, the hardware description language is adopted as the function description as described above, but other than that, the function description by the logical expression, truth table, functional diagram, etc. Is also possible.

(Logic Level Test Vector Generating Process) The logic circuit synthesized by the logic synthesizing means 1 is next inputted to the logic level test vector generating means 2 to evaluate the fault coverage.

The test vector generation at the logic level is to assume an stuck-at fault on a logic circuit and obtain an input for detecting it. The logic level test vector generating means 2 in this embodiment employs an algorithm based on path activation. This method seeks a path for propagating a difference between a signal value assuming a failure and a normal value to an output.

FIG. 10 shows a processing flow chart of the logic level test vector generating means 2 in this embodiment. In the figure, 81 is a fault selection step for selecting one fault from the fault set, and 82 is a fault basic D-cube for the selected fault, and D is an input value satisfying it.
A setting operation step, 83 is an implication operation step for obtaining the value of a signal line determined by the value of a certain signal line being determined, 84 is a D drive operation step for propagating the failed basic D cube in the output direction, and 85 is given. It is a matching operation step for setting the value on the input side so as not to contradict the value of the signal line. Here, the failure basic D-cube is a state of the signal line indicating that the value is different when the failure exists and when the failure does not exist. In this embodiment, by repeating the D drive operation step 84 and the implication operation step 83,
Propagate this failed basic D-cube to either output,
Then, in the matching operation step 85, an input pattern that realizes such propagation is obtained. The obtained input pattern is the test vector for the selected fault.

For example, consider a circuit as shown in FIG.
In order to detect a c / 0 fault (a stuck-at fault in which c is fixed to 0), an input in which c is 1 is required, and y must be 0. If a state where 1 is normal and 0 when a failure occurs is written as D, x must be set to 0 in order to set f to D. Next, u must be set to 1 in order to set i to D. Finally, j must be 0 in order for z to be D, which requires v to be 1. After all x
It can be seen that when y = 0 and u = v = 1, z becomes D, and the output value is 1 under normal conditions, whereas the output value becomes 0 when there is a c / 0 failure. This is x = y = 0,
This means that u = v = 1 is the test vector for the fault c / 0.

On the other hand, if a contradiction occurs in the implication operation step 83 or the coincidence operation step 85, a backtrack occurs, and another D drive or D setting is attempted. If the number of times exceeds the set value, the generation of the test vector for the fault is aborted and it is considered as an undetected fault. Then, the ratio of detectable faults to all faults in the logic circuit is reported as a fault coverage.

As the logic level test vector generating method, various methods other than the method described here can be considered, and can be considered as another embodiment of the present invention. Also,
Since it is difficult in terms of processing time to generate a test vector at the logic level by using a purely algorithmic method, failure simulation is often used together. The logic level test vector generating means 2 of the present invention naturally includes those using such a mixed method.

FIG. 12 shows an example of a list of test vectors generated by the logic level test vector generating means 2 in this embodiment.

Further, a failure in which the test vector generation has failed is reported as an undetected failure, and at the same time, information regarding the processing that has actually failed is also reported and these are output as the testability analysis result. In this embodiment, the undetected failure list is sent to the circuit conversion means 4 as the testability analysis result by the logic level test vector generation means 2. However, this is not necessarily the undetected failure list, and for example, it is difficult to observe. It may be like a list of locations or difficult-to-control locations.

(Determination Processing) The fault detection rate evaluated by the logic level test vector generation means 2 is input to the determination means 3.

FIG. 13 shows a processing flow chart of the judging means 3 in this embodiment. In this embodiment, the input failure detection rate is a preset threshold value (here, 95).
%), And if it is larger than the threshold value, it is judged to be sufficient, and if it is smaller than the threshold value, it is judged to be insufficient. In this embodiment, 95% is adopted as the threshold value, but it can be set to any value. Normal LSI design has a failure detection rate of 9
0% or more is often required. The higher the threshold value, the higher the testability of the synthesized circuit, but the cost and delay tend to increase. Also, by setting the threshold value to 100%, the circuit conversion can always be executed regardless of the input fault coverage, but this is substantially the same as not making a determination. It corresponds to the case where the means 3 is not provided.

In this embodiment, the judgment is made using only the fault coverage, but the judgment is also made using other information such as the testability analysis result, the cost and delay of the logic circuit, and the processing time. Can be performed and can be considered as another embodiment of the present invention.

(Circuit conversion process) If the result of the judgment by the judging means 3 is that the failure detection rate is insufficient, the logic level test vector generating means 2 outputs the logic based on the testability analysis result. The circuit converting means 4 performs circuit conversion on the logic circuit synthesized by the synthesizing means 1 in order to improve testability, and generates a logic circuit that is easy to test.

FIG. 14 is a circuit conversion means 4 in this embodiment.
The processing flow chart of is shown. In the figure, reference numeral 111 denotes a test circuit inserting step for inserting a test circuit into the input logic circuit based on the input testability analysis result,
Reference numeral 112 denotes a circuit optimizing step for performing circuit conversion for eliminating redundancy generated in the circuit as a result of test circuit insertion, 113
Is a cost / delay evaluation step of evaluating the cost and delay of the circuit in which the test circuit is inserted, and determining whether or not it meets given design constraints, 114 is the result of the cost / delay evaluation step, This is a circuit adjustment step for converting a circuit so as to satisfy the design constraint when the constraint is not satisfied.

As an example of the test circuit insertion processing, FIG. 15 shows conversion associated with scan path insertion for flip-flops in the circuit. Reference numeral 121 is a flip-flop which receives and stores the value of the data input d in synchronization with the rising edge of the clock signal clk. After conversion, flip-flop 1
A select circuit 122 is inserted immediately before 21 to switch the input of the flip-flop 121 between the original data input d and the scan input sin according to the value of the select signal sel. The scan input sin is connected to the output Q of the flip-flop of the preceding stage forming the scan path, whereby the data input d is input to the flip-flop 121 during the normal operation and the scan input sin is input to the flip-flop 121 during the scan operation. At the time of scan operation, the flip-flops forming the scan path as a whole act like one shift register, and values can be set in the flip-flops in order bit by bit from the outside.

By inserting the scan path in this way, it becomes possible to freely set the value to the flip-flop in the circuit and to read the value of the flip-flop freely, which makes it difficult for the sequential circuit as it is. Testing can be facilitated down to the level of combinatorial circuits.

FIG. 16 shows, as another example of the test circuit insertion processing, circuit conversion accompanying the reconvergence removal processing. The biggest factor in the difficulty of testing a combinational circuit is the reconvergence contained in the circuit. Reconvergence is a state in which a certain signal in the circuit is input to the same gate through a plurality of paths, and referring to FIG. 16, G1 → G2 → G4 → G6 and G
The output of G1 is reconverged at G6 through two routes of 1 → G3 → G5 → G6.

When reconvergence exists in the circuit, inconsistency often occurs in the implication operation 83 after the D setting operation 82 and the D drive operation 84 in the logic level test vector generation processing, and the test vector generation fails. There is. Therefore,
If there is such a difficult reconvergence test,
By inserting an EXOR gate in either of the paths forming the reconvergence and cutting the reconvergence, it is possible to convert the circuit into a substantially non-reconvergent circuit.

In the example of FIG. 16, EX is placed between G3 and G5.
By inserting the OR gate G7, when D propagates to a, D can always propagate to d. The value of a is 0
However, even if it is 1, the value of c can be set to 0 or 1 by appropriately determining the value of b. Therefore, it is possible to easily generate the test vector without generating backtrack when the logic level test vector is generated.

FIG. 17 shows an example of the circuit optimization processing. In the test circuit insertion process, the test circuit is mechanically inserted when necessary without considering the surrounding circuit configuration,
A combination of the inserted test circuit and the original circuit is often redundant. This redundancy cannot be removed by the conventional logic circuit generation device that does not consider testability, but such redundancy can be removed by the circuit optimization processing of FIG. 17 after the test circuit insertion processing. You can do it.

The example of FIG. 17 shows optimization of the circuit around the flip-flop after the scan path insertion processing. An AND gate G1 is connected to the D input of the original flip-flop, and a select circuit including a composite gate G2 and two inverters G3 and G4 is inserted by the scan path insertion process.

In the optimized circuit, the AND gate G1 is absorbed by the composite gate G2 to become a new composite gate G5, and the inverter G3 is absorbed by the flip-flop. Further, the inverter G4 is deleted, and instead, the signal line ~ sel having the same function (~ means signal inversion).
Are connected. It can be seen that the circuit after optimization has reduced area and delay compared to the circuit before optimization.

However, even after the optimization, it is apparent that both the area and the delay are increased as compared with the original circuit before the test circuit is inserted. Further, there is no guarantee that the design constraints regarding the area, delay, etc., which the original circuit satisfied, are still satisfied. Therefore, after performing circuit optimization, the cost and delay of the circuit are evaluated and it is checked whether the design constraints are satisfied. As a result, if it is found that the condition is not satisfied, it is necessary to perform circuit adjustment processing so as to satisfy the constraint.

For example, when the scan path is inserted, the select circuit is inserted immediately before the flip-flop, so that the delay of the D input of the flip-flop becomes large, and the setup time is restricted (a time longer than a change in the clock signal). The constraint that the D input signal must be determined as soon as possible may not be satisfied, and it may be necessary to shorten the delay of the D input.

FIG. 18 shows an example of circuit conversion that is often used to reduce the delay. Both reduce the delay between the input A and the output X. In the example of a), the inverter existing in the path is deleted by changing the output polarity of the gate. In b), the number of gate stages in the path is reduced by converting the logically equivalent signals A and F. In c), the gates are overlapped to form a composite gate.

In the circuit conversion means of this embodiment, the test circuit insertion process to the circuit adjustment process are executed in sequence, but this is not necessarily the case. For example, design constraints are evaluated while evaluating cost, delay, etc. A test circuit may be inserted within a range that satisfies the above condition, or an optimum circuit conversion may be performed in consideration of a trade-off with an increase in cost and an increase in delay, which is considered as another embodiment of the present invention. You can

Further, in the circuit conversion means of the present embodiment, only the cost and delay of the circuit are taken into consideration as the design constraint, but in some cases it is necessary to take into account the power consumption and the like. Can be considered as another embodiment of the invention.

Further, in the present embodiment, the scan path insertion and the reconvergence removal are shown as an example of the test circuit insertion processing of the circuit conversion means, but other than that, for example, addition of a reset function to the flip-flop, control observation is difficult. It is also possible to add control observation input / output ports for points and scan flip-flops.

As described above, in the first embodiment,
The logic level test vector generation means 2 evaluates the testability of the logic circuit at the logic level, and if there is a portion where the testability is insufficient as a result, the circuit conversion means 4 converts it at the logic level so that the test becomes easy. For this reason, the testability analysis result is more accurate than the conventional method. Moreover, in the conventional logic circuit generation device considering testability, it is true that it is necessary compared to the fact that the test circuit is inserted even in unnecessary places and vice versa. Since the circuit conversion for test facilitation is performed only in such a portion, the increase in circuit cost due to the test facilitation can be reduced. This is an extremely important point in this embodiment.

[Second Embodiment] FIG. 2 is a block diagram showing the configuration of an embodiment of a logic circuit generator according to the present invention. In the figure, reference numeral 1 is a logic synthesizing means for synthesizing a logic circuit satisfying a given function based on the inputted function description, and 5 is a function level test for generating a test vector for fault detection from the inputted function description. Vector generation means,
Reference numeral 6 performs a failure simulation on the logic circuit synthesized by the logic synthesizing means 1 using the test vector generated by the function level test vector generating means 5, and determines whether the test vector has a failure detection rate and a testability analysis result. The failure simulation means for outputting the detected failure list, 3 is a judgment means for judging whether or not the failure detection rate output by the failure simulation means 6 is sufficiently high, and 4 is an insufficient failure detection rate by the judgment means 3. If it is found, the circuit converting means is for transforming the logic circuit synthesized by the logic synthesizing means 1 based on the undetected fault list output by the fault simulating means 6.

The operation of this embodiment configured as described above will be described below. First, the logic circuit synthesized by the logic synthesizing means 1 from the input functional description and design constraint is subjected to a fault simulation using the test vector generated by the functional level test vector generating means 5 from the input functional description, The fault coverage is evaluated. Then, the judging means 3 judges whether or not the failure detection rate is sufficiently high, and if it is sufficiently high, the logic circuit synthesized by the logic synthesizing means 1 is used as it is along with the test vector generated by the function level test vector generating means 5. Output. If the failure detection rate is sufficient as a result of the judgment of the judging means 3, the circuit is compared with the logic circuit synthesized by the logic synthesizing means 1 based on the undetected fault list output by the fault simulating means 6. The conversion means 4 performs circuit conversion for improving the testability and generates a testable logic circuit.

Further, as a result of the circuit conversion, if the given design constraint cannot be satisfied by any means,
It is also possible to change the parameters related to the logic synthesis, return to the logic synthesis means 1 again, and synthesize the logic circuit again under the new parameters.

FIG. 5 shows the processing flow of this embodiment. This figure also shows the configuration of an embodiment of the logic circuit generating method according to the invention of claim 5.

The respective processes of logic synthesis, judgment and circuit change are the same as those in the first embodiment. Therefore, in the following, only the functional level test vector generation processing and the failure simulation processing of this embodiment will be sequentially described in more detail.

(Function Level Test Vector Generation Processing) In the function level test vector generation, a failure is assumed on the function level circuit or the function description, and an input for detecting the failure is obtained. The function level test vector generating means 5 in this embodiment realizes on a computer manual test vector generation which has been conventionally performed by a circuit designer. In this method, the empirical knowledge possessed by the circuit designer plays an important role.

FIG. 19 shows a processing flow of the function level test vector generating means 5 in this embodiment. In the figure, 101 is a test target functional block selecting step for selecting a functional block (a constituent element of a functional level circuit such as an adder or a register) to be tested from a functional level circuit, and 102 is the selection from an external input of the circuit. An input setting sequence determining step for propagating a signal to the input of the functional block and determining a procedure for setting the input data of the functional block; 103 propagates the signal from the output of the functional block to the external output of the circuit. , An output propagation sequence determining step for determining a procedure for outputting the output data of the functional block to the outside, 104 is test data for determining a set of combinations of the input data of the functional block required to obtain a sufficiently high fault coverage. The determining step, 105 is the determined test sequence (input setting sequence Scan and an output propagation sequence) a set of test vector as an input of the circuit from a set of combinations of the test data is a test vector synthesizing step of synthesizing.

Consider, for example, a circuit having a function level as shown in FIG. Here, 91, 92 and 93 are registers, and 94
Is an adder. Considering the adder 94 as a functional block to be tested, test data must be propagated from the external input to the input of the adder 94 in order to test it. In this example, the input of the adder 94 is connected to the register 91 and the register 92, and these registers are connected to the common external input IN. Therefore adder 9
In order to propagate the test data to the 4th input, one test data is first set to the external input IN and the clock C
At the timing of 1, write to the register 91, then set the other test data to the external input IN and clock C
It must be written to the register 92 at the timing of 2.

When the test data has been propagated to the input of the adder 94, the calculation result must be propagated to the external output. In this example, the output of adder 94 is register 93
Is connected to the external output OUT via. Therefore, in order to propagate the calculation result to the external output, it is necessary to write the calculation result to the register 93 at the timing of the clock C3.

Thus, the adder 94 can be tested by comparing the operation result appearing at the external output with the correct expected value. In order to perform a reliable test, it is necessary to test with more test data, and it is necessary to change the input data and repeat the above-mentioned test sequence. It has a great influence.

When the bit width of the input of the functional block is relatively small, all the data that can be expressed by the bit width can be used as the test data, which makes it possible to perform a highly reliable test. it can. For example adder 9
If the bit width of 4 is 3, there are 8 types of data that can be represented by 3 bits, from 0 to 7. Therefore, the number of combinations of two input data is 64 (8 × 8). However, since the number of combinations increases exponentially with respect to the bit width, it becomes impossible to test all data when the bit width of the data becomes large, and test data that can be executed using some method such as a random number method. We need to find the set of.

When the test sequence and the test data are obtained as described above, the test vector for realizing the test sequence is obtained for each test data,
If you collect it for all test data, adder 94
The test vector for is obtained. By repeating the processing described above for all the functional blocks included in the circuit and collecting the obtained test vectors, a complete test vector set for the circuit can be obtained.

In the present embodiment, the method of determining the test sequence and the test data for a single functional block in the circuit is used, but a method of simultaneously considering a plurality of functional blocks is also conceivable. It can be considered as another embodiment of the invention. Considering the circuit of FIG.
It is also a test for 1, 92, 93, and it is not necessary to newly generate a test vector for a register.

Since the fault detection rate of the test vector generated by the function level test vector generation means 5 in this way is not evaluated at the logic level, it is necessary to evaluate the failure detection rate by the failure simulation means 6. There is.

(Fault Simulation Processing) In the fault simulation, contrary to the test vector generation for obtaining a test vector for detecting an assumed fault, a fault detectable by a given test vector is obtained. That is, if the result of performing a normal logic simulation by inputting a certain test vector is different from the result of performing a simulation assuming a failure, the failure can be detected by the input test vector.

For example, consider the circuit of FIG. The normal output value z by the test vector (u, v, x, y) = (1, 0, 0, 1) is 1. Now, assuming j / 0 failure, n
Changes to 0, and as a result, the output value z changes from 1 to 0.
Therefore, the j / 0 fault can be detected by this test vector. On the other hand, assuming an h / 1 fault, m changes to 1, k changes to 0, and n changes to 0, but as a result, the output value z remains 1. Therefore, the h / 1 fault cannot be detected by this test vector.

The failure simulation in this embodiment is executed by the procedure shown below. First, one test vector is selected and a logic simulation is performed to determine the values of all signal lines in the circuit. For example, test vectors (u, v,
x, y) = (1, 0, 0, 1), the internal signal lines are (a, b, c, d, e, f, g, h, i, j, k, l,
m, n, p) = (1,0,1,0,0,0,0,0,0,1,1,
0,0,1,1), and it can be seen that the value of the output z is 1.

Next, the detectable fault set is propagated to the output side in order from the gate connected to the external input. Focusing on one gate, a detectable fault is a fault (detectable fault) that causes the output value of the gate to be in the state opposite to the normal value among the faults whose values are opposite to the normal signal value of the gate. Obtained by selecting.

Focusing on the AND gate G5, for example, since the input a is 1 and l is 0, the output m is 0. Therefore, the candidates of detectable failure are a / 0, l / 1,
It is m / 1. Among these failures, l / 1 and m / 1 change the output m from 0 to 1, but at a / 0, m remains 0. Therefore, the detectable faults are l / 1 and m / 1. These detectable faults are propagated to the gate G7 connected to the output of the gate G5 and included in the candidates for the detectable fault of the gate G7. For this gate G7, the detectability is checked for these propagated faults plus the input / output faults of the gate G7 itself.

The fault finally propagated to the output z as described above is the test vector (u, v, x, y) = (1,
It becomes a set of detectable failures due to 0, 0, 1). A fault that is not included in the detectable fault set obtained for all the given test vectors is an undetected fault. The ratio of detectable faults to all faults is reported as the fault coverage.

As described above, in the second embodiment,
The function level test vector generation means 5 and the failure simulation means 6 evaluate the testability of the logic circuit at the logic level, and if there is a portion where the testability is insufficient as a result, the circuit conversion means 4 facilitates the test. Convert by level. Therefore, as in the case of the first embodiment, the testability analysis is more accurate than the conventional method, and the circuit conversion for test facilitation is performed only at a truly necessary portion. The increase in circuit cost due to simplification can be reduced.

Further, according to the second embodiment, the testability analysis by the combination of the function level test vector generation and the failure simulation has a circuit scale larger than that of the logic level test vector generation which is an algorithmic method. It has the advantage that it can be processed at high speed when it becomes large. This is an extremely important point in this embodiment.

Various failure simulation methods other than the method shown in this embodiment can be considered, and can be considered as another embodiment of the present invention. Further, in the present embodiment, the undetected failure list is sent to the circuit conversion means 4 as the testability analysis result by the failure simulation means 6, but this does not necessarily have to be the undetected failure list. Or a list of difficult-to-control points.

[Third Embodiment] FIG. 3 is a block diagram showing the structure of an embodiment of a logic circuit generator according to the present invention. In the figure, 1 is a logic synthesizing means for synthesizing a logic circuit satisfying a given function based on the inputted function description, and 5 is a first for detecting a failure from the inputted function description.
Function level test vector generating means for generating a test vector, and 6 performs a failure simulation on the logic circuit synthesized by the logic synthesizing means 1 using the first test vector generated by the function level test vector generating means 5. ,
Fault simulation means for outputting a first fault coverage and a first undetected fault list for the first test vector, 3 is a determination means for determining whether the fault coverage is sufficiently high, and 2 is this determination means. When it is determined by 3 that the first failure detection rate output by the failure simulation means 6 is insufficient, the logic synthesis is performed based on the first undetected failure list output by the failure simulation means 6. The second fault relating to the case where the second test vector for fault detection is generated by analyzing the logic circuit synthesized by the means 1 and the generated second test vector and the first test vector are combined The logic level test vector generation means 4 for outputting the detection rate and the second undetected failure list as the testability analysis result are judged by the judgment means 3 by the judgment means 3. When it is found that the second fault detection rate output by the level test vector generating means 2 is insufficient, the above-mentioned second undetected fault list output by the logic level test vector generating means 2 is used as the basis. It is a circuit conversion means for modifying the logic circuit synthesized by the logic generation means 1.

The operation of the present embodiment configured as above will be described below. First, the logic circuit synthesized by the logic synthesizing unit 1 from the input functional description and design constraint fails using the first test vector generated by the functional level test vector generating unit 5 from the input functional description. The simulation is performed and the first fault coverage is evaluated. Then, the judging means 3 judges whether or not the first failure detection rate is sufficiently high, and if it is sufficiently high, the functional level test vector generating means 5 generates the logic circuit synthesized by the logic synthesizing means 1 as it is. Output with test vector. If the result of the judgment by the judging means 3 is that the first failure detection rate is insufficient, the logic level test vector generating means 2 determines whether the first failure detection means outputs the first undetected failure list. ,
The logic circuit synthesized by the logic synthesizer 1 is analyzed to generate a second test vector that complements the first test vector, and the first test vector and the second test vector are combined. The second fault coverage in the case is evaluated. The judging means 3 also judges whether or not the second fault detection rate is sufficiently high. If the second failure detection rate is sufficiently high, the logic circuit synthesized by the logic synthesizing means 1 is used as it is,
It is output together with the first and second test vectors. If the result of the determination by the determination means 3 is that the second fault coverage is insufficient, the logic synthesis is performed based on the second undetected fault list output by the logic level test vector generation means 2. The circuit converting means 4 performs circuit conversion on the logic circuit synthesized by the means 1 to improve the testability, and generates a logic circuit that is easy to test.

The test-facilitated logic circuit is analyzed again by the logic level test vector generation means 2 to evaluate the fault coverage. Is it possible to obtain a sufficiently high fault coverage?
The above processing is repeated until the number of repetitions exceeds the maximum value. Further, as a result of the circuit conversion, when the given design constraint cannot be satisfied, the parameters related to the logic synthesis are changed, the process returns to the logic synthesis means 1 again, and the logic circuit is set to the new parameter. It can also be re-synthesized under.

FIG. 6 shows the processing flow of this embodiment. This figure also shows the configuration of an embodiment of the logic circuit generation method according to the invention of claim 6.

Logic synthesis, logic level test vector generation,
The respective processes of judgment and circuit change are the same as those in the first embodiment, and the respective processes of functional level test vector generation and failure simulation are the same as those in the second embodiment. Therefore, detailed description of each of these processes is omitted.

In the third embodiment, after the functional level test vector generating means 5 and the fault simulating means 6 evaluate the general testability of the logic circuit, the logic level test vector generating means 2 evaluates the logic circuit. The more accurate testability is evaluated, and if there is a portion where the testability is insufficient as a result, the circuit conversion means 4 performs conversion at the logic level so as to facilitate the test. Therefore, as in the case of the first embodiment, the testability analysis is more accurate than the conventional method, and the circuit conversion for test facilitation is performed only at a truly necessary portion. The increase in circuit cost due to simplification can be reduced. Further, as in the case of the second embodiment, the testability analysis by the combination of the functional level test vector generation and the fault simulation is compared with the logical level test vector generation which is an algorithmic method.
It has the advantage that it can be processed at high speed when the circuit scale becomes large.

Further, according to the third embodiment, since the final testability evaluation is performed by the logic level test vector generation, it is different from the second embodiment in which only the function level test vector generation and the fault simulation are performed. Compared to this, a more accurate evaluation of testability is possible. This is an important point of this embodiment.

Although the logic level test vector generation and the circuit conversion are performed only once in this embodiment, it is effective to repeat it several times in some cases, which is considered as another embodiment of the present invention. You can In the present embodiment, the undetected failure list is sent to the circuit conversion means 4 as the testability analysis result by the logic level test vector generation means 2. However, this is not necessarily the undetected failure list. It may be a list of difficult-to-observe points or difficult-to-control points.

[0095]

As described above, according to the first to sixth aspects of the invention, accurate testability analysis is performed at the logic level, and based on the result, testability is limited to difficult test points. Therefore, a logic circuit that is easy to test can be automatically generated without significantly adversely affecting the cost and the delay time as compared with the related art. Therefore, at present, as the circuit scale of LSI increases,
There is a strong demand for improved testability, and its practical effect is extremely large.

However, in order to analyze the testability at the logic level, the logic level test vector generation processing is adopted in claims 1 and 4, but in this case, the processing time increases when the circuit scale becomes large. There is a problem that it does.

Therefore, in claims 2 and 5, a test vector is directly generated from the functional description by the functional level test vector generating process, and the test vector is used to perform a failure simulation to analyze the testability at the logic level. .

However, this has the advantage that the processing time is shorter than in the cases of claims 1 and 4, but on the other hand, the analysis of the testability becomes weaker than in the cases of claims 1 and 4, and as a result, There is a problem that it causes an increase in cost.

Therefore, in claims 3 and 6, the logic level test vector is generated only for the faults reported as undetected faults by the fault simulation, and the faults that are truly difficult to detect are narrowed down. Both time and accuracy of testability analysis are compatible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a logic circuit generation device according to the invention of claim 1;

FIG. 2 is a block diagram showing an embodiment of a logic circuit generation device according to the invention of claim 2;

FIG. 3 is a block diagram showing an embodiment of a logic circuit generation device according to the invention of claim 3;

FIG. 4 is a process flow chart showing an embodiment of a logic circuit generation method according to the invention of claim 4 and showing the operation of the logic circuit generation device of FIG. 1;

5 is a process flow chart showing an embodiment of the logic circuit generation method according to the invention of claim 5, and showing the operation of the logic circuit generation device of FIG. 2. FIG.

6 is a process flow chart showing an embodiment of a logic circuit generation method according to the invention of claim 6 and showing the operation of the logic circuit generation device of FIG. 3;

7 is an example of a functional description in a hardware description language that is an input to the logic synthesizing means in FIG.

8 is a processing flowchart of the logic synthesizing means in FIG. 1. FIG.

9 is a diagram showing an example of a logic diagram representing a logic circuit output by the logic synthesizing means in FIG. 1. FIG.

FIG. 10 is a processing flow chart of a logic level test vector generating means in FIG.

FIG. 11 is a diagram showing an example of a logic circuit for explaining the processing in the logic level test vector generating means in FIG.

FIG. 12 is a diagram showing an example of a list of test vectors output by the logic level test vector generating means in FIG.

FIG. 13 is a processing flow chart of the determination means in FIG.

FIG. 14 is a process flow diagram of the circuit conversion means in FIG.

FIG. 15 is an explanatory diagram of scan path insertion processing in the circuit conversion unit in FIG. 1.

16 is an explanatory diagram of reconvergence removal processing in the circuit conversion unit in FIG.

FIG. 17 is an explanatory diagram of a circuit optimizing process in the circuit converting means in FIG.

18 is an explanatory diagram of a delay reduction process which is an example of a circuit adjustment process in the circuit conversion unit in FIG. 1, in which a) is a gate output polarity changing process, b) is an input signal conversion process, and FIG.
In c), the delay between the input A and the output X is shortened by the gate duplication process.

FIG. 19 is a process flow chart of the function level test vector generating means in FIG.

FIG. 20 is a diagram showing an example of a functional level circuit for explaining the processing in the functional level test vector generating means in FIG.

FIG. 21 is a diagram showing an example of a logic circuit for explaining processing in the failure simulation means in FIG.

FIG. 22 is a process flow diagram of a conventional typical test design.

FIG. 23 is a block diagram of a first example of a conventional logic circuit generation device considering testability.

FIG. 24 is a block diagram of a second example of a conventional logic circuit generation device considering testability.

[Explanation of symbols]

1 Logic synthesis means 2 Logic level test vector generation means 3 Judgment means 4 circuit conversion means 5 Functional level test vector generation means 6 Failure simulation means 132 Logic Synthesis Step 133 Logic level test vector generation step 134 Judgment step 134a First determination step 134b Second determination step 136 Circuit conversion step 138 Functional Level Test Vector Generation Step 139 Failure simulation step

Claims (6)

[Claims] 1. A logic circuit generation device for automatically generating a logic circuit from a functional description, comprising logic synthesizing means for synthesizing a logic circuit satisfying a given function based on an input functional description, A logic level test vector generating means for analyzing a logic circuit synthesized by the logic synthesizing means to generate a test vector for fault detection and outputting a fault coverage and a testability analysis result of the generated test vector; Determination means for determining whether or not the fault coverage detected by the level test vector generation means is sufficiently high,
When it is determined by the determination means that the fault coverage is insufficient, the logic circuit synthesized by the logic synthesis means is modified based on the testability analysis result output by the logic level test vector generation means. A logic circuit generation device comprising: circuit conversion means. 2. A logic circuit generation device for automatically generating a logic circuit from a functional description, comprising logic synthesizing means for synthesizing a logic circuit satisfying a given function based on the input functional description, and an input. A function level test vector generation means for generating a test vector for fault detection from the specified function description,
Fault simulation means for performing fault simulation on the logic circuit synthesized by the logic synthesis means using the test vector generated by the functional level test vector generation means, and outputting the fault detection rate and testability analysis result of the test vector. And a determination means for determining whether or not the failure detection rate output by the failure simulation means is sufficiently high, and the failure simulation means when the determination means determines that the failure detection rate is insufficient. A logic circuit generation device comprising: a circuit conversion unit that transforms the logic circuit synthesized by the logic synthesis unit based on the output testability analysis result. 3. A logic circuit generation device for automatically generating a logic circuit from a function description, comprising logic synthesizing means for synthesizing a logic circuit satisfying a given function based on the input function description, and an input. The function synthesizing means synthesizes the function level test vector generating means for generating a first test vector for fault detection from the generated function description and the first test vector generated by the function level test vector generating means. Failure simulation means for performing a failure simulation on the logic circuit and outputting a first failure detection rate and an undetected failure list for the first test vector;
The determination means for determining whether or not the failure detection rate is sufficiently high, and the failure simulation means if the determination means determines that the first failure detection rate output by the failure simulation means is insufficient. Analyzing the logic circuit synthesized by the logic synthesizing unit on the basis of the undetected fault list outputted by the above, and generating the second test vector for fault detection, and the generated second test vector and the first test vector. Logic level test vector generation means for outputting a second fault coverage and testability analysis result in the case of combining with the test vector, and the second means output by the logic level test vector generation means by the determination means.
If the failure detection rate of is found to be insufficient,
A logic circuit generation device comprising: circuit conversion means for transforming a logic circuit synthesized by the logic synthesis means based on a testability analysis result outputted by the logic level test vector generation means. 4. A logic circuit generation method for automatically generating a logic circuit from a function description, comprising a logic synthesis step of synthesizing a logic circuit satisfying a given function based on an input function description, A logic level test vector generation step that analyzes the logic circuit synthesized in the logic synthesis step to generate a test vector for fault detection, and outputs the fault coverage and testability analysis result of the generated test vector, and the logic level test vector generation step. A determination step for determining whether or not the fault coverage output in the level test vector generation step is sufficiently high, and if the fault coverage is found to be insufficient in this determination step, the logic synthesis step is performed. A test for the synthesized logic circuit from the testability analysis result output in the logic level test vector generation step. Limited to the places that cause difficulty,
A method for generating a logic circuit, characterized by comprising a circuit conversion step which is modified for testability and which performs circuit optimization for eliminating redundant parts and circuit adjustment for satisfying design constraints. 5. A logic circuit generation method for automatically generating a logic circuit from a function description, comprising: a logic synthesis step of synthesizing a logic circuit satisfying a given function based on the input function description; A function level test vector generation step of generating a test vector for fault detection from the generated function description, and a logic circuit synthesized in the logic synthesis step using the test vector generated in this function level test vector generation step. A fault simulation step of outputting a fault detection rate and a testability analysis result of the test vector,
A determination step of determining whether the failure detection rate output in this failure simulation step is sufficiently high,
If it is found that the fault coverage is insufficient in this determination step, the logic circuit synthesized in the logic synthesis step is considered to be the cause of the test difficulty obtained from the testability analysis result output in the fault simulation step. It is characterized in that it is provided with a circuit conversion step for performing circuit optimization for eliminating the redundant part and circuit adjustment for satisfying the design constraint while limiting the number of parts to Logic circuit generation method. 6. A logic circuit generation method for automatically generating a logic circuit from a function description, comprising: a logic synthesis step of synthesizing a logic circuit satisfying a given function based on the input function description; A functional level test vector generation step of generating a first test vector for fault detection from the generated functional description, and a synthesis in the logic synthesis step using the first test vector generated in the functional level test vector generation step Failure simulation is performed on the generated logic circuit and the first test vector related to the first test vector
Failure detection step for outputting the failure detection rate and the undetected failure list of the first failure detection step, a first determination step for determining whether or not the first failure detection rate output in the failure simulation step is sufficiently high, and the first determination step If the first failure detection rate is found to be insufficient in the determination step, the logic circuit synthesized in the logic synthesis step based on the undetected failure list output in the failure simulation step is used. The second failure detection rate and the testability analysis result regarding the case where the second test vector for failure detection is analyzed to generate the second test vector and the first test vector are analyzed. Output logic level test vector generation step,
A second determination is made as to whether or not the second failure detection rate output in this logic level test vector generation step is sufficiently high.
And the second failure detection rate is found to be insufficient in the second determination step, the logic circuit synthesized in the logic synthesis step is processed in the logic level test vector generation step. Limiting to the part that causes the test difficulty obtained from the output testability analysis result, transforming it for testability, circuit optimization to eliminate redundant parts, and circuit adjustment to meet design constraints. And a circuit conversion step for performing the following.