JPH0555255A - Method of manufacturing thin film semiconductor device - Google Patents

Abstract

(57) [Abstract] [Objective] To manufacture a thin film semiconductor device having an LDD structure by a simple process capable of miniaturization. [Structure] An LDDTFT is formed by implanting impurity ions through gate insulating films having two different film thicknesses. [Effect] A good TFT having a small leakage current can be miniaturized and easily manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film semiconductor device such as an active matrix liquid crystal display, an image sensor and a three-dimensional LSI device, which is formed on an insulating material.

[0002]

2. Description of the Related Art In recent years, with the increase in screen size and resolution of liquid crystal displays, the drive system has changed from a simple matrix system to an active matrix system, and it is becoming possible to display a large amount of information. The active matrix system can be used for a liquid crystal display having several hundreds of thousands of pixels, and a switching transistor is formed for each pixel.

For these switching elements, a thin film transistor (hereinafter abbreviated as TFT) formed on an insulating material is usually used. Amorphous silicon or polycrystalline silicon is used as the active layer of the TFT. However, when the driving circuit is integrated with the TFT or when the pixel is formed with high density and high definition, the operation speed is high. Crystalline silicon is preferred. When such a TFT using polycrystalline silicon is used as a pixel switching element,
In the ON state of a so-called transistor that inputs a signal to a pixel, an ON current higher than that of an amorphous silicon TFT by one digit or more can be obtained.

On the other hand, in the OFF state of the transistor that holds the input signal, the TFT using polycrystalline silicon causes a large amount of leakage current I _{OFF as} compared with the amorphous silicon TFT, which causes the deterioration of image quality. It is causing it.

Conventionally, in order to reduce the leakage current I _OFF , a light-doped / drain method (LDD method) is adopted in which the concentration of impurities serving as donors or acceptors added to the source / drain regions in a polycrystalline silicon TFT is changed. (K. NAKAZAWA et al S1
D90digest 311'90). That is, in the source region and the drain region, the leakage current I _OFF is reduced by forming a TFT having a structure in which the impurity concentration is increased in the region on the extraction electrode side and lowered in the region on the channel side.

A method of manufacturing the TFT having the LDD structure according to the prior art will be described with reference to FIG. First, source / drain regions 202 to which impurities are added at a high concentration are formed on an insulating substrate 201. This is, for example, a low pressure vapor phase chemical vapor deposition method (LPCVD method) for a polycrystalline silicon film to which phosphorus is added.
And so on. (FIG. 2a) Next, the intrinsic silicon film 203
Then, a gate insulating film 204 is further deposited, and then a gate electrode 205 is formed. (FIG. 2b) Then the gate electrode 205
Using the mask as a mask, the impurity 206 is implanted at about 1 × 10 ¹⁵ l / cm ² or less and the LDD region 208 and the channel portion 20.
Form 7. (FIG. 2c) After that, an interlayer insulating film 209 is deposited if necessary, contact holes are opened in the source / drain regions where impurities are added at a high concentration, and source / drain extraction electrodes 210 are formed to complete the TFT. To do.

[0007]

However, there are some problems in the LDD fabrication according to the above-mentioned conventional technique. First of all, since the source / drain regions 202 to which impurities are added at a high concentration are formed first, the existence of the TFTs depends on their existence.
It becomes difficult to miniaturize. As a result, the TFT in the pixel section
The area that can be covered becomes large, the aperture ratio becomes low and it becomes a liquid crystal display with a dark screen, and the number of pixels cannot be increased because it cannot be miniaturized, and the problem that a high-definition screen cannot be provided appears. To do. In addition, since the process is long, there are problems that the yield cannot be reduced and the product price cannot be reduced. Further, the distance of the LDD region 208 is as large as 4 to 5 μm due to the alignment of the alignment. Therefore, if the amount added to the LDD region is too small, parasitic resistance is generated in the TFT, and the on-current value is lowered, or the on-current value is decreased. If it passes, LDD does not occur, and there is a problem that the off-leakage current increases and the device ends up.

Therefore, the present invention aims to solve such various problems, and the purpose thereof is to simplify the process and then to perform TF.
An object of the present invention is to provide a method of manufacturing a TFT having an LDD structure, which can promote the miniaturization of T.

[0009]

According to the present invention, there is provided a source comprising a semiconductor layer containing at least two kinds of impurities serving as donors or acceptors in different concentrations on at least one surface of a substrate whose surface is an insulating material. And a drain region,
In a thin film semiconductor device that constitutes a MIS field effect transistor in which a semiconductor layer to be a channel region connecting the source region and the drain region and a gate insulating layer and a gate electrode are formed on these semiconductor layers, A step of partially changing the film thickness, a step of forming a gate electrode,
A method for manufacturing a thin film semiconductor device, comprising the steps of implanting impurities serving as donors or acceptors after these steps are completed by using the gate electrode as a mask to form the source region and the drain region in a self-aligned manner.

[0010]

EXAMPLES The method for manufacturing a TFT according to the present invention will be described in detail below based on examples, but the present invention is not limited to the following examples.

1A to 1D are LDDs according to the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of a TFT for forming a MIS field effect transistor having a structure. First, a silicon film 101 is formed on a substrate whose surface is an insulating material. This film thickness is preferably about 1500 Å or less, but is not particularly limited. In this embodiment, the film is deposited to a film thickness of 500Å. Next, the gate insulating film 102 is deposited. Here, a silicon dioxide (SiO ₂ ) film is selected as a gate insulating film material, and an electron cyclotron resonance plasma CVD method (ECR-
PECVD method is used to deposit a film thickness of 1250Å. In addition to this, the gate insulating film can be formed by an atmospheric pressure CVD method (APCVD method), a sputtering method, or the like. Then the gate electrode 1
Form 03. In this embodiment, 3 is used as the gate electrode material.
A phosphorus-doped polycrystalline silicon film having a film thickness of 000Å was used, but other than this, a metal material or the like is also possible. After the gate electrode material is deposited, patterning is performed to form the gate electrode 103.
Are formed (FIG. 1A). Next, etch the gate insulating film on the region where you want to add impurities in high concentration to the required length,
The gate insulating film on the region is thinned (104). In this embodiment, the thin gate insulating film 104 has a thickness of zero. That is, the gate insulating film was completely removed from above the region where impurities were to be added at a high concentration to expose the silicon surface.
However, the thickness of the thin gate insulating film 104 can be arbitrarily changed according to the film thickness of the gate insulating film 102, the impurity ion species, the implantation energy, and the concentration of addition. Next, the ion species 105 to be added is implanted into the substrate (FIG. 1).
(B)). In this embodiment, phosphorus is selected as the impurity ion ⁺
Implant P ³¹ at 60 KeV and 1 × 10 ¹⁶ l / cm ² . In this case, the LSS theory (J. Lindhard et a
l. Mat. Fys. Medd. Dan. Vid. Se
lsk 33 , No 14, 1, 1963)

[Chemical 1] When the effective addition amount is calculated according to, the projection range R _{P in} silicon is 0.073 μm, and the projection range dispersion ΔR _P =
Projected range R _P = 0.0 in SiO ₂ at 0.0298 μm
Since the projection range dispersion ΔR _P = 0.0216 μm, the area is 7.
LDD equivalent to 8 × 10 ¹⁵ l / cm ²
In the region 106, the implantation is equivalent to 1.1 × 10 ¹³ l / cm ² (FIG. 1 (c)). After ion implantation, 5 on the substrate
Heat treatment is performed at 00 ° C. for about 2 hours to activate the added ions. This activation may be performed by heat as in this embodiment, or may be performed by laser light irradiation, rapid thermal annealing method, or the like. Further, when the impurity element is added from the hydride as a raw material by an ion implantation device without a mass spectrometer, the activation heat treatment is performed at 350 ° C. 2
It does not matter if it is about time. For example, when phosphorus addition is attempted, a mixed gas of phosphine (PH ₃ ) and hydrogen is used as a source gas, and PH _X ⁺ (X = 0, 1, 2, 3) or H is obtained by an ion implantation device without a mass spectrometer. ^By implanting ⁺ and H ₂ ⁺ at the same time, the activation heat treatment temperature can be kept low at about 350 ° C. or lower, and the heat treatment time can be shortened to about 2 hours or less. After the activation of the impurity ions, the interlayer insulating film 10
8 is deposited as needed, a contact hole is opened, and wiring 109 is made of aluminum or the like to complete a TFT having an LDD structure (FIG. 1D). The transistor characteristics may be improved by implanting an appropriate amount of hydrogen (H ⁺ , H ₂ ⁺ ) with an ion implanter having no mass spectrometer before opening the contact hole. In the present embodiment, hydrogen of 5 × 10 ¹⁵ l / cm ² with an energy of 80 KeV is used.
I typed it in.

FIG. 33-a shows an example I _ds -V _gs curve of the TFT characteristics manufactured by the above-described process. In this embodiment, the transistor size is L = W = 10 μm, and the length of the region 107 in which impurities are added at a high concentration is 10 μm.
The length of the LDD region 106 was 2 μm. Figure 33-b
For comparison, an electrical characteristic diagram of a self-aligned TFT manufactured by the conventional technique is shown. According to FIG.
It is known that in the DD structure TFT, almost no decrease in on-current is observed, and the leakage current I _OFF is significantly reduced.

In the present embodiment, the thickness of the thin gate insulating film 104 is set to zero, but the film thickness, film thickness, implantation ion species and its amount, implantation energy,
Also, it can be changed according to the concentration ratio of the region 107 in which impurities are added at a high concentration and the LDD region 106, and it is not necessary to make it zero. In this embodiment, the normal gate insulating film 102 is used.
Since the film quality of the interlayer insulating film 108 is different from that of the interlayer insulating film 108, when the wiring 109 is formed in the source / drain regions, first, the interlayer insulating film 10 is formed.
Open a contact hole in 8 and then gate insulating film 1
02, there are two opening operations such as wiring after opening a contact hole, and in this embodiment, one of them was also used for forming the thin gate insulating film 104. By adopting such a method, a stable LDD structure TFT can be manufactured by a simple process without adding an extra process.

[0014]

As described above, according to the present invention, L
By forming two or more different types of gate insulating films for a TFT having a DD structure and then implanting impurity ions, a TFT having an LDD structure with good electrical characteristics can be created, and the TFT can be miniaturized. And Depending on this,
It has a great effect of realizing high performance and low price of the active matrix liquid crystal display, such as increasing the aperture ratio of the liquid crystal display and providing high-definition pixels.

[Brief description of drawings]

1A to 1D are cross-sectional views of elements in respective steps of manufacturing a thin film semiconductor device showing an embodiment of the present invention.

2A to 2D are cross-sectional views of elements in respective steps of manufacturing a thin film semiconductor device according to a conventional technique.

FIG. 3 is a diagram showing an effect of the present invention.

[Description of Reference Signs] 101 Silicon film 102 Gate insulating film 103 Gate electrode 104 Thin gate insulating film 105 Impurity ion species implantation 106 LDD region 107 Highly doped region 108 Interlayer insulating film 109 Wiring 201 Insulating substrate 202 High impurity Source / drain region 203 added to the concentration 203 True silicon film 204 Gate insulating film 205 Gate electrode 206 Impurity ion species implantation 207 Channel part 208 LDD region 209 Interlayer insulating film 210 Source / drain extraction electrode

Claims (1)

[Claims] 1. A source and drain region comprising a semiconductor layer containing at least two kinds of impurities serving as donors or acceptors at different concentrations on at least one surface of a substrate whose surface is an insulating material, and the source. Region, which is a channel region connecting the drain region and the drain region, and a MIS in which a gate insulating layer and a gate electrode are formed on these semiconductor layers
In a thin film semiconductor device that constitutes a field effect transistor, a step of partially changing the film thickness of a gate insulating layer, a step of forming a gate electrode, and an impurity that becomes a donor or an acceptor after these steps are completed And a step of forming a source region and a drain region in a self-aligned manner by using as a mask, the method for manufacturing a thin film semiconductor device.