JPH0555534A - Production of laminated semiconductor device - Google Patents
Production of laminated semiconductor deviceInfo
- Publication number
- JPH0555534A JPH0555534A JP21105591A JP21105591A JPH0555534A JP H0555534 A JPH0555534 A JP H0555534A JP 21105591 A JP21105591 A JP 21105591A JP 21105591 A JP21105591 A JP 21105591A JP H0555534 A JPH0555534 A JP H0555534A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- device layer
- soi substrate
- adhesive
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、機能素子層をはり合
わせた積層型半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated semiconductor device in which functional element layers are laminated together.
【０００２】[0002]
【従来の技術】従来の半導体装置は、基板の表面あるい
は表面のごく近傍に素子を形成するという、いわゆる一
層型のデバイスであった。2. Description of the Related Art A conventional semiconductor device is a so-called single-layer device in which elements are formed on the surface of a substrate or in the vicinity of the surface.
【０００３】[0003]
【発明が解決しようとする課題】このような装置では、
一つのデバイスを構成するために、大きな面積を必要と
し、多機能なデバイスを限られたチップ面積に組み込む
ことが困難となってきた。SUMMARY OF THE INVENTION In such a device,
A large area is required to configure one device, and it has become difficult to incorporate a multifunctional device into a limited chip area.
【０００４】[0004]
【課題を解決するための手段】本発明は、このような従
来デバイスのもつ課題を解決するためのものであり、第
１のＳＯＩ基板に第１のデバイス層を形成した後、デバ
イス層にコンタクトとして、凸型の導電層を選択的に形
成する。第２のＳＯＩ基板に第２のデバイス層を形成
し、その上に接着剤を堆積させ、この接着剤を第１のデ
バイス層のコンタクト部分に対応するように選択的にエ
ッチングし凹部を形成した後、第１のデバイス層と、第
２のデバイス層をはり合わせることにより、デバイス層
間のコンタクトがとれた積層型半導体の製造を行う。SUMMARY OF THE INVENTION The present invention is intended to solve the problems of such conventional devices. After the first device layer is formed on the first SOI substrate, the device layer is contacted. As a result, a convex conductive layer is selectively formed. A second device layer is formed on a second SOI substrate, an adhesive is deposited on the second device layer, and the adhesive is selectively etched so as to correspond to the contact portion of the first device layer to form a recess. Then, by laminating the first device layer and the second device layer, a stacked semiconductor in which contacts between the device layers are made is manufactured.
【０００５】[0005]
【作用】上記のように、半導体装置を形成することによ
って、多機能なデバイスを形成することができ、チップ
面積を有効に使うことができる。By forming the semiconductor device as described above, a multifunctional device can be formed and the chip area can be effectively used.
【０００６】[0006]
【実施例】以下に、本発明の一実施例を図面に基づいて
説明する。図１は、本発明に係わる積層型半導体装置の
製造方法を示すものである。第１のＳＯＩ基板（Silico
n On Insulator）１の表面に第１のデバイス層２を形成
した後、ポリシリコンを堆積させ、選択的にエッチング
することにより、選択的にコンタクト部となる導電層３
を形成する。そして、第２のＳＯＩ基板４に第２のデバ
イス層５を形成し、その上に、第１のデバイス層との接
着剤となるＳＯＧ（SpinOn Glass）膜６を回転塗布した
あと、第１のデバイス層２のコンタクト部となる導電膜
３と対応する所に、選択的にエッチングしてコンタクト
部７を形成する。その後、第１のデバイス層と第２のデ
バイス層５をＳＯＧ膜６を介して、熱圧着させることに
より、第１のデバイス層１と第２のデバイス層５の間の
コンタクトを取った積層型半導体装置の製造を行う。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a method of manufacturing a stacked semiconductor device according to the present invention. First SOI substrate (Silico
After the first device layer 2 is formed on the surface of the n On Insulator 1), polysilicon is deposited and selectively etched to form a conductive layer 3 that becomes a contact portion selectively.
To form. Then, a second device layer 5 is formed on the second SOI substrate 4, and an SOG (Spin On Glass) film 6 serving as an adhesive with the first device layer is spin-coated thereon, and then the first device layer 5 is formed. A contact portion 7 is formed by selectively etching a portion of the device layer 2 corresponding to the conductive film 3 that will be the contact portion. Then, the first device layer and the second device layer 5 are thermocompression-bonded via the SOG film 6 to make a contact between the first device layer 1 and the second device layer 5 to form a stacked type. Manufacture of semiconductor devices.
【０００７】[0007]
【発明の効果】この結果、従来Ｓｉ基板上に二次元的に
しか構成できなかったデバイスを、三次元的に構成で
き、従来方式に比べて多機能なデバイスを構成すること
ができる。また、ＳＯＩ基板を用いることにより、消費
電力の小さいデバイスを形成できる。また接着剤として
用いたＳＯＧ膜は平坦化しやすく、比較的低温で加熱処
理して接着が可能であるので、第１のデバイスと第２の
デバイスを平行度よく接着させ、又熱によるデバイス層
への悪影響を少なくすることができる。As a result, it is possible to construct a device that can be constructed only two-dimensionally on a Si substrate in the past three-dimensionally, and to construct a multi-functional device as compared with the conventional system. Further, by using the SOI substrate, a device with low power consumption can be formed. Further, since the SOG film used as an adhesive is easy to flatten and can be heat-treated and bonded at a relatively low temperature, the first device and the second device can be bonded in parallel with each other, and the device layer can be thermally bonded to the device layer. The adverse effect of can be reduced.
【図１】（ａ）〜（ｄ）は本発明に係わる積層型半導体
装置の製造方法を示すものである。1A to 1D show a method for manufacturing a stacked semiconductor device according to the present invention.
１ 第１のＳＯＩ基板 ２ 第１のデバイス層 ３ コンタクト部となる導電層 ４ 第２のＳＯＩ基板 ５ 第２のデバイス層 ６ 接着剤 ７ コンタクト部 DESCRIPTION OF SYMBOLS 1 1st SOI substrate 2 1st device layer 3 Conductive layer used as a contact part 4 2nd SOI substrate 5 2nd device layer 6 Adhesive 7 Contact part
Claims (1)
形成する工程と、前記デバイス層の上に、選択的に導電
膜でできた凸部を形成する工程と、第２のＳＯＩ基板に
第２のデバイス層を形成する工程と、前記デバイス層に
接着剤を堆積させる工程と、前記接着剤を選択的にエッ
チングし、凹部を設ける工程と、前記凸部と凹部をはめ
合わせ前記接着剤を介して第１のデバイス層と、第２の
デバイス層をはり合わせることにより、デバイス層間の
コンタクトをとる工程とからなる積層型半導体装置の製
造方法。1. A step of forming a first device layer on a first SOI substrate, a step of selectively forming a convex portion made of a conductive film on the device layer, and a second SOI substrate. Forming a second device layer on the substrate, depositing an adhesive on the device layer, selectively etching the adhesive to form a recess, and fitting the protrusion and the recess to each other A method for manufacturing a stacked semiconductor device, comprising the steps of making a contact between device layers by laminating a first device layer and a second device layer with an agent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21105591A JPH0555534A (en) | 1991-08-22 | 1991-08-22 | Production of laminated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21105591A JPH0555534A (en) | 1991-08-22 | 1991-08-22 | Production of laminated semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555534A true JPH0555534A (en) | 1993-03-05 |
Family
ID=16599647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21105591A Pending JPH0555534A (en) | 1991-08-22 | 1991-08-22 | Production of laminated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555534A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225154B1 (en) | 1993-07-27 | 2001-05-01 | Hyundai Electronics America | Bonding of silicon wafers |
| JP2005311065A (en) * | 2004-04-21 | 2005-11-04 | Oki Electric Ind Co Ltd | Manufacturing method of mems (microelectronic mechanical system) device and bonding substrate for manufacturing mems device |
| JP2006522461A (en) * | 2002-12-20 | 2006-09-28 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Manufacturing method of three-dimensional device |
| WO2005095461A3 (en) * | 2004-03-31 | 2006-12-14 | Canon Kk | Gold-binding protein and use thereof |
-
1991
- 1991-08-22 JP JP21105591A patent/JPH0555534A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225154B1 (en) | 1993-07-27 | 2001-05-01 | Hyundai Electronics America | Bonding of silicon wafers |
| US6570221B1 (en) | 1993-07-27 | 2003-05-27 | Hyundai Electronics America | Bonding of silicon wafers |
| JP2006522461A (en) * | 2002-12-20 | 2006-09-28 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Manufacturing method of three-dimensional device |
| WO2005095461A3 (en) * | 2004-03-31 | 2006-12-14 | Canon Kk | Gold-binding protein and use thereof |
| US7807391B2 (en) | 2004-03-31 | 2010-10-05 | Canon Kabushiki Kaisha | Gold-binding protein and use thereof |
| US7833731B2 (en) | 2004-03-31 | 2010-11-16 | Canon Kabushiki Kaisha | Gold-binding protein and use thereof |
| EP2267034A2 (en) | 2004-03-31 | 2010-12-29 | Canon Kabushiki Kaisha | Gold-binding protein and use thereof |
| EP2267033A2 (en) | 2004-03-31 | 2010-12-29 | Canon Kabushiki Kaisha | Gold-binding protein and use thereof |
| US7871614B2 (en) | 2004-03-31 | 2011-01-18 | Canon Kabushiki Kaisha | Gold-binding protein and use thereof |
| JP2005311065A (en) * | 2004-04-21 | 2005-11-04 | Oki Electric Ind Co Ltd | Manufacturing method of mems (microelectronic mechanical system) device and bonding substrate for manufacturing mems device |
| US7323354B2 (en) | 2004-04-21 | 2008-01-29 | Oki Electric Industry Co., Ltd. | Method of manufacturing MEMS device |
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