JPH0547704A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH0547704A JPH0547704A JP19808391A JP19808391A JPH0547704A JP H0547704 A JPH0547704 A JP H0547704A JP 19808391 A JP19808391 A JP 19808391A JP 19808391 A JP19808391 A JP 19808391A JP H0547704 A JPH0547704 A JP H0547704A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- contact
- layer
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims 2
- 238000005121 nitriding Methods 0.000 claims 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910021529 ammonia Inorganic materials 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 3
- 229910008479 TiSi2 Inorganic materials 0.000 abstract 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 23
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 229910008484 TiSi Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、コンタクトホールをタ
ングステン（Ｗ）で埋め込む構造の半導体素子のそのコ
ンタクトホール部を中心にした製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor element having a structure in which a contact hole is filled with tungsten (W), centering on the contact hole portion.
【０００２】[0002]
【従来の技術】従来、半導体素子に製法おけるＣＶＤ法
によるタングステンの埋め込みコンタクトプロセスは、
例えば１９９０ＩＥＥＥ，Ｊｕｎｅ１２−１３，１９９
０ＶＭＩＣ Ｃｏｎｆｅｒｅｎｃｅ（１９９０）（米）
Ｐ．１１３−１１９に見られるように、まず下層のゲー
ト電極等を絶縁するために、フロー性の良い絶縁膜、た
とえばＢＰＳＧ膜を堆積し、下層膜や拡散層と導通をと
りたい箇所だけ、通常のホトリソグラフィー技術及びド
ライエッチング技術でコンタクトホールを形成した後
に、絶縁膜とタングステンの密着性を良くする為に、密
着層としてチタン系の膜をスパッタ法で堆積し、ステッ
プカバレッジの良いＣＶＤ法のタングステン膜を全面に
堆積する。その後に、絶縁膜上のタングステンが完全に
なくなるまでエッチバック処理を施し、コンタクトホー
ル内だけにタングステンを残す方法をとっている。特に
密着層として用いるチタン系の膜は、ＴｉとＴｉＮの２
層構造の層を使っていて、ＴｉＮは、Ｎ2 雰囲気中でＴ
ｉをスパッタする反応性スパッタリングで形成してい
た。またＴｉＮ膜の下層のＴｉ膜は、コンタクトホール
底部の拡散層（シリコンに不純物ＡｓやＢＦ2 等をドー
プした層）とオーミックコンタクトを得るために用いて
いて、これは、Ａｒ雰囲気中でスパッタして形成してい
た。さらにこのＴｉＮ／Ｔｉの２層膜を形成した後に、
Ｎ2 雰囲気で６００〜９００℃の温度で熱処理し、下層
膜であるＴｉと拡散層のＳｉとを反応させ、チタンシリ
サイド（ＴｉＳｉ2 ）を形成し、より低い接触抵抗が得
られるオーミックコンタクトを形成して、タングステン
膜の密着層として利用していた。2. Description of the Related Art Conventionally, a buried contact process of tungsten by a CVD method in a semiconductor device is
For example, 1990 IEEE, June 12-13, 199
0VMIC Conference (1990) (US)
P. As shown in 113-119, first, in order to insulate the lower gate electrode and the like, an insulating film having a good flow property, for example, a BPSG film is deposited, and only an ordinary portion is desired to be electrically connected to the lower film and the diffusion layer. After forming contact holes by photolithography technology and dry etching technology, in order to improve the adhesion between the insulating film and tungsten, a titanium-based film is deposited as an adhesion layer by sputtering, and CVD method tungsten with good step coverage is used. Deposit the film over the entire surface. After that, an etch back process is performed until the tungsten on the insulating film is completely removed, and the tungsten is left only in the contact holes. In particular, the titanium-based film used as the adhesion layer is composed of Ti and TiN.
Optionally with the layer of the layer structure, TiN is, T in an N 2 atmosphere
It was formed by reactive sputtering in which i is sputtered. The Ti film under the TiN film is used to obtain ohmic contact with the diffusion layer at the bottom of the contact hole (a layer in which impurities As, BF 2, etc. are doped in silicon), and this is formed by sputtering in an Ar atmosphere. Was formed. After forming this TiN / Ti two-layer film,
Heat treatment is performed in an N 2 atmosphere at a temperature of 600 to 900 ° C. to react Ti, which is the lower layer film, with Si, which is the diffusion layer, to form titanium silicide (TiSi 2 ), thereby forming an ohmic contact with which a lower contact resistance can be obtained. Then, it was used as an adhesion layer of the tungsten film.
【０００３】また、密着層の膜厚は、コンタクトホール
の形状を逆テーパーにしないという制約から約１０００
Å以下の膜厚でしか堆積することができず、Ｔｉ膜を５
００Å、ＴｉＮ膜を５００Åとするのが一般的であっ
た。この時の、アスペクト比が２以上になるコンタクト
ホールの底部のＴｉ膜は、５０Å以下になり、低い接触
抵抗を得るには、不十分な膜厚であった。The thickness of the adhesion layer is about 1000 because of the restriction that the shape of the contact hole is not inversely tapered.
The Ti film can be deposited only with a film thickness of Å or less,
It was general that the film thickness of 00Å and the TiN film was 500Å. At this time, the Ti film at the bottom of the contact hole having an aspect ratio of 2 or more was 50 Å or less, which was insufficient to obtain a low contact resistance.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、以上述
べたタングステン膜による埋め込みコンタクトプロセス
における二層構造（ＴｉＮ／Ｔｉ）の密着層では、ステ
ップカバレッジの悪いスパッタ法で形成しており、コン
タクトホールのアスペクト比が大きくなればなるほど、
オーミックコンタクトを得るために必要なＴｉ膜がコン
タクトホール底部で十分な厚さのものが得られなくなる
という問題点があった。However, the contact layer having the double-layer structure (TiN / Ti) in the buried contact process using the tungsten film described above is formed by the sputtering method with poor step coverage, and the aspect ratio of the contact hole is large. The larger the ratio,
There has been a problem that a Ti film necessary for obtaining ohmic contact cannot have a sufficient thickness at the bottom of the contact hole.
【０００５】この発明は、以上述べたコンタクトホール
底部で十分な膜厚のＴｉ膜が得られないという問題点を
除去するために、密着層の形成方法を改良し、アスペク
ト比の高いコンタクトホールでも、低い接触抵抗のオー
ミックコンタクトを有するタングステン膜による埋め込
みコンタクトを提供することを目的とする。In order to eliminate the above-mentioned problem that a Ti film having a sufficient film thickness cannot be obtained at the bottom of a contact hole, the present invention improves the method of forming an adhesion layer and even in a contact hole having a high aspect ratio. , A buried contact made of a tungsten film having an ohmic contact with a low contact resistance is provided.
【０００６】[0006]
【課題を解決するための手段】前述の目的のためにこの
発明は、密着層の形成方法において、従来のＴｉＮ／Ｔ
ｉのトータル膜厚に相当するＴｉをスパッタ法で形成
し、その後、ランプアニール装置を用いて、窒素または
アンモニアで熱処理を施し、絶縁膜上のＴｉはＴｉＮ
に、拡散素上のＴｉはＴｉＳｉ2 になるようにしたもの
である。To achieve the above object, the present invention provides a conventional TiN / T method in a method of forming an adhesion layer.
Ti corresponding to the total film thickness of i is formed by the sputtering method, and thereafter, heat treatment is performed with nitrogen or ammonia using a lamp annealing apparatus.
In addition, Ti on the diffusive element is TiSi 2 .
【０００７】[0007]
【作用】本発明は前述したように、Ｗ膜の密着層にＴｉ
を窒化したＴｉＮを用いたので、コンタクトホール底部
には、十分な膜厚のＴｉＳｉ2 を形成することができ、
低い接触抵抗を持つオーミックコンタクトが形成でき
る。In the present invention, as described above, the adhesion layer of the W film is made of Ti.
Since TiN which is nitrided is used, TiSi 2 having a sufficient film thickness can be formed at the bottom of the contact hole.
An ohmic contact with low contact resistance can be formed.
【０００８】[0008]
【実施例】図１は、この発明の実施例を示す工程断面図
であり、以下に詳細に説明する。1 is a process sectional view showing an embodiment of the present invention, which will be described in detail below.
【０００９】まず、（ａ）図に示すように、シリコン基
板１にＡｓやＢＦ2等の不純物をイオン注入し拡散層２
を形成し、ＢＰＳＧ膜等の絶縁膜３を約２μｍ堆積さ
せ、拡散層２上に１μｍ以下の直径を有するコンタクト
ホール９をドライエッチング技術により開孔し、スパッ
タリング技術によりＴｉ４を約１０００Å堆積させる。
この時のＴｉはスパッタリング技術で形成するために、
段差被覆性が悪くアスペクト比の高いコンタクトホール
９では、ホール底部には、平坦部の１０％以下の膜厚し
か堆積させることができない。また、Ｔｉを厚く堆積し
すぎると、段差被覆性が悪いために、Ｔｉがホール段差
部でオーバーハング状になってしまい、コンタクトホー
ル９の形状が逆テーパー状となり、後のタングステン膜
の埋め込みが十分にできなくなる。そのために、Ｔｉの
堆積膜厚を、約１０００Å以上にすることはできない。
次に（ｂ）図に示すように、Ｔｉ膜４をランプアニール
装置を用いて、窒素またはアンモニア雰囲気中で、７０
０〜９００℃、１０〜４０秒の熱処理を施し、絶縁膜３
上のＴｉ４はＴｉＮ５に、拡散層２上のＴｉ４はＴｉＳ
ｉ2 ６にする。その後、ＣＶＤ法によりＷ膜７を約１μ
ｍ堆積させ、コンタクトホール９を完全に埋め込む。Ｗ
膜７を形成条件の１例としては、温度４００℃、圧力３
０ｔｏｒｒ、反応ガスＷＦ6 ４００ｓｃｃｍ、Ｈ2 ５０
００ｓｃｃｍである。最後に（ｃ）図に示すように、Ｗ
膜７とＴｉＮ膜５を全面エッチングして、絶縁膜３が露
出したところでストップし、コンタクトホール９内にＷ
膜７を残し、その後に、配線としてアルミニウム８を約
５０００Å形成する。First, as shown in FIG. 1A, impurities such as As and BF 2 are ion-implanted into the silicon substrate 1 to diffuse the diffusion layer 2.
Then, an insulating film 3 such as a BPSG film is deposited by about 2 μm, a contact hole 9 having a diameter of 1 μm or less is formed on the diffusion layer 2 by a dry etching technique, and Ti 4 is deposited by about 1000 Å by a sputtering technique.
Since Ti at this time is formed by the sputtering technique,
In the contact hole 9 having a poor step coverage and a high aspect ratio, only a film thickness of 10% or less of the flat portion can be deposited on the bottom of the hole. On the other hand, if Ti is deposited too thickly, the step coverage is poor, so that the Ti becomes overhanging at the hole step portion, the contact hole 9 has an inversely tapered shape, and the tungsten film is not embedded later. I can't do enough. Therefore, the deposited Ti film thickness cannot be about 1000 Å or more.
Next, as shown in FIG. 2B, the Ti film 4 is removed by a lamp annealing apparatus in a nitrogen or ammonia atmosphere to 70
Insulating film 3 after heat treatment at 0-900 ° C for 10-40 seconds
Ti4 on the top is TiN5, Ti4 on the diffusion layer 2 is TiS
to i 2 6. After that, the W film 7 is deposited to about 1 μm by the CVD method.
Then, the contact hole 9 is completely buried. W
An example of the conditions for forming the film 7 is a temperature of 400 ° C. and a pressure of 3.
0 torr, reaction gas WF 6 400 sccm, H 2 50
It is 00 sccm. Finally, as shown in FIG.
The film 7 and the TiN film 5 are entirely etched to stop when the insulating film 3 is exposed, and the W in the contact hole 9 is stopped.
After leaving the film 7, aluminum 5000 is formed as a wiring by about 5000 Å.
【００１０】[0010]
【発明の効果】以上、詳細に説明したように、この発明
によれば、Ｗ膜の密着層に、Ｔｉを窒化したＴｉＮを用
いたのでコンタクトホール底部には、十分な膜厚のＴｉ
Ｓｉ2 を形成することができ、低い接触抵抗を持つオー
ミックコンタクトが形成可能である。As described above in detail, according to the present invention, since TiN in which Ti is nitrided is used for the adhesion layer of the W film, a Ti film having a sufficient thickness is formed at the bottom of the contact hole.
Si 2 can be formed, and an ohmic contact having low contact resistance can be formed.
【図１】本発明の実施例の工程断面図。FIG. 1 is a process sectional view of an example of the present invention.
１ シリコン基板 ２ 拡散層 ３ 絶縁膜 ４ Ｔｉ ５ ＴｉＮ ６ ＴｉＳｉ ７ Ｗ膜 ８ アルミニウム ９ コンタクトホール 1 Silicon Substrate 2 Diffusion Layer 3 Insulation Film 4 Ti 5 TiN 6 TiSi 7 W Film 8 Aluminum 9 Contact Hole
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/90 Ｄ 7353−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 21/90 D 7353-4M
Claims (1)
で埋め込む構造の半導体素子の製造に当たって、 （ａ）半導体基板に拡散層を形成し、該基板上に絶縁膜
を堆積させ、前記拡散層上にコンタクトホールを開孔す
る工程と、 （ｂ）次いで、Ｔｉをスパッタ法で堆積させる工程と、 （ｃ）そのＴｉを熱処理して窒化する工程と、 （ｄ）その後Ｗ膜を形成する工程とを含むことを特徴と
する半導体素子の製造方法。1. The contact hole is made of tungsten (W).
(A) a step of forming a diffusion layer on a semiconductor substrate, depositing an insulating film on the substrate, and opening a contact hole on the diffusion layer; and (b) , A step of depositing Ti by a sputtering method, (c) a step of heat-treating the Ti and nitriding it, and (d) a step of forming a W film after that, a method of manufacturing a semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19808391A JPH0547704A (en) | 1991-08-07 | 1991-08-07 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19808391A JPH0547704A (en) | 1991-08-07 | 1991-08-07 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547704A true JPH0547704A (en) | 1993-02-26 |
Family
ID=16385232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19808391A Pending JPH0547704A (en) | 1991-08-07 | 1991-08-07 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547704A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6686288B1 (en) | 1996-02-21 | 2004-02-03 | Micron Technology, Inc. | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture |
-
1991
- 1991-08-07 JP JP19808391A patent/JPH0547704A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6686288B1 (en) | 1996-02-21 | 2004-02-03 | Micron Technology, Inc. | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture |
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