JPH0540646A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To use only a 8-bit standard RAM instead of two conventional RAMs used for data and flags respectively and to reduce the cost of an error correcting circuit by storing the flags into a part of the RAM which stores the data. CONSTITUTION:A flag buffer 7 is provided to get together the 1-bit flags every 8 bits together with a bus arbiter 15 which contains a function to receive the data bus request signals from the buffer 7, and a flag processing circuit 13 which processes the 8-bit flag read out of a RAM 6 and calculates a data error position. Then an exclusive address area which stores the flag data is provided in a buffer RAM which gets together the received flags every prescribed number of bits into the flag data of the same byte unit as the input data and stores these input data. Therefore two conventional RAMs needed for data and flags can be turned avaliable into only a single RAPT. Otherwise an 8-bit standard RAM is instead of 8 9-bit special RAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data error correction circuit, and more particularly to a CD-ROM error correction circuit.

[0002]

2. Description of the Related Art A data processing circuit of a CD-ROM reproducing device is roughly divided into two blocks.
One is a data processing circuit for CD-DA (Digital Audio), and the other is a data processing circuit for CD-ROM.

The CD-DA data processing circuit is a CD-DA
The CD-ROM data processing circuit receives the output of the CD-DA data processing circuit and corrects the data that could not be corrected by the CD-DA error correction processing according to the standard. To process.

There are two types of methods for error correction processing according to the CD-ROM standard. One is a method called syndrome correction, which finds the position of error data and an error pattern only by calculating data, and the other is a method called erasure correction, which is also found by calculating error data.

Comparing the two correction methods, one byte in one codeword (44 bytes) can be corrected by the syndrome correction, while two bytes can be corrected by the erasure correction.

To perform conventional erasure correction,
As shown in FIG. 3, the flag RAM 14 divided into pages exactly like the data RAM 6 or 9bi for storing the data and the flag at the same address in the same RAM
It was common to use t-width RAM.

[0007]

In this conventional erasure correction circuit, since 8-bit data and 1-bit flag are stored at the same address, a RAM having a total width of 9 bits is required. As a realization means, 2 RAM
There is a problem in that the cost mounting area becomes larger than that of the syndrome correction because it is used individually or a special RAM having a width of 9 bits is used.

An object of the present invention is to use two RAMs or
It is to provide an error correction circuit that does not use a special 9-bit width RAM.

[0009]

In order to solve the above problems, the error correction circuit of the present invention receives a data buffer request signal from a flag buffer 7 that collects 1-bit flags in 8-bit units. A Bus Arbiter 15 having a function and a flag processing circuit 13 for processing an 8-bit configuration flag read from the RAM 6 to calculate an error position of data are provided.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an error correction circuit according to an embodiment of the present invention. The flag input processing circuit 2 receives a clock synchronized with the byte unit of data from the byte clock input terminal 10, and the flag input terminal 11 inputs a flag in 1-bit units in synchronization with the byte clock.

The output from the flag input processing circuit 2 is input to the flag buffer 7, where it is held at 8 bits.
When 8 bits of data are available, the flag buffer 7
The data bus request signal is output to the BusArbiter 15.

The BusArbiter 15 gives the data bus use permission signal to the flag buffer 7 and controls the address generator 4 if there is no other request signal having a high priority, and the address of the RAM 6 is shown in FIG.
Switch to the flag area of the RAM shown in. The flag area has data of 2430 bytes and a flag of 2341 bits (≈2
The total of 2633 bytes (93 bytes) is allocated to one part in the divided block. The divided blocks are used for input processing, correction processing, and output processing, respectively.

Since data transfer between blocks is performed by changing the upper address of the block in a ring shape, if the data and the flag are put in the same block as in this embodiment, the data can be dealt with in each process. The flag that has been removed can be easily extruded. The read flag is processed by the flag processing circuit 13, and the ECC circuit 12 is notified of which data is incorrect.

[0014]

As described above, according to the present invention, since the flag is stored by using a part of the RAM for storing the data, two RAs are required for the data and the flag.
It has an effect that only one M is required. Or 9 bits
8bit standard RAM instead of special width RAM
Since it can be used, it has an effect of reducing the cost.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an area of a RAM shown in FIG.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Data Input Processing Circuit 2 Flag Input Processing Circuit 3 BusArbiter 4 Address Generator 5 Data Bus 6 RAM 7 Flag Buffer 8 Bit Clock Input Terminal 9 Data Input Terminal 10 Byte Clock Input Terminal 11 Flag Input Terminal 12 Correction Processing Circuit 13 Flag Processing Circuit 14 Flag RAM 15 BusArbiter

Claims (2)

[Claims] 1. An error correction circuit that receives a flag indicating the presence or absence of an error in the data in synchronization with input data, and corrects the error in the data designated by the flag. An error correction circuit characterized in that a flag data in the same byte unit as that of the input data is put together, and a dedicated address area for storing the flag data is provided on a buffer RAM for storing the input data. 2. The error correction circuit according to claim 1, wherein the predetermined bits are 8 bits.