JPH0536341A - Manufacture of chip type fuse - Google Patents
Manufacture of chip type fuseInfo
- Publication number
- JPH0536341A JPH0536341A JP18869191A JP18869191A JPH0536341A JP H0536341 A JPH0536341 A JP H0536341A JP 18869191 A JP18869191 A JP 18869191A JP 18869191 A JP18869191 A JP 18869191A JP H0536341 A JPH0536341 A JP H0536341A
- Authority
- JP
- Japan
- Prior art keywords
- conductor circuit
- chip
- type fuse
- ceramic substrate
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000919 ceramic Substances 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 238000007788 roughening Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 230000007257 malfunction Effects 0.000 abstract description 3
- 230000004927 fusion Effects 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 13
- 238000000576 coating method Methods 0.000 description 13
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 12
- 238000007747 plating Methods 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000005406 washing Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- 241001050985 Disco Species 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Fuses (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップ型ヒューズの製
造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip type fuse.
【０００２】[0002]
【従来の技術】従来、電子機器の誤動作、短絡等の故障
により生じた過電流による電子機器の発熱、火災等の事
故を防止するために、ガラス管の端子間に金属の可溶材
料を接続した管ヒューズが用いられていた。しかし、電
子機器が小型化になるにつれ、前記のような管ヒューズ
では大き過ぎる、量産性に劣る、配線板に表面実装しに
くい等の問題がある。2. Description of the Related Art Conventionally, a metal fusible material is connected between terminals of a glass tube in order to prevent accidents such as heat generation and fire of electronic equipment due to overcurrent caused by malfunction of electronic equipment, failure such as short circuit. A tube fuse was used. However, as electronic devices become smaller, there are problems that the above-mentioned tube fuse is too large, mass productivity is poor, and surface mounting is difficult on a wiring board.
【０００３】上記のような問題点を解決するために、特
開昭６２−１７２６２６号公報に示されるように、セラ
ミック基板の両端部に電極を設け、電極間にヒユーズ用
ワイヤ（可溶体）をボンディングしたチップ型ヒュー
ズ、セラミック基板の上面に厚膜法、めっき法等で電極
や導体回路（可溶体）を形成したチップ型ヒューズなど
が提案された。In order to solve the above problems, as disclosed in Japanese Patent Laid-Open No. 172626/1987, electrodes are provided at both ends of a ceramic substrate and a fuse wire (fusible body) is provided between the electrodes. Bonded chip fuses, chip fuses in which electrodes and conductor circuits (fusible bodies) are formed on the upper surface of a ceramic substrate by a thick film method, a plating method, and the like have been proposed.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記に示
すようなチップ型ヒューズは、ワイヤ、導体回路等の可
溶体の断面積が一定なため、発熱量が均一である。この
ため過電流が流れたときの溶断時間が長くなるという欠
点がある。However, in the chip type fuse as described above, the heat generation amount is uniform because the cross-sectional area of the fusible body such as the wire and the conductor circuit is constant. For this reason, there is a drawback that the fusing time becomes long when an overcurrent flows.
【０００５】本発明は上記のような欠点のないチップ型
ヒューズの製造法を提供することを目的とするものであ
る。An object of the present invention is to provide a method of manufacturing a chip type fuse which does not have the above-mentioned drawbacks.
【０００６】[0006]
【課題を解決するための手段】本発明はセラミック基板
の表面を粗化した後、該セラミック基板の表面に金属被
膜を形成し、ついで金属被膜の上面にレジスト膜を形成
し、しかる後露光、現像、エッチング、レジスト膜を剥
離し、金属被膜の必要な部分のみを残して導体回路を形
成し、導体回路の上面及びセラミック基板の上部露出面
に保護膜を形成後、チップ状に成形してチップ型ヒュー
ズを製造する方法において、上記導体回路の３ケ所に切
り欠き部を設けて幅の狭い部分を形成し、このうち中央
部分の導体回路の幅を左右の導体回路の幅より狭くする
チップ型ヒューズの製造法に関する。According to the present invention, after roughening the surface of a ceramic substrate, a metal coating is formed on the surface of the ceramic substrate, and then a resist film is formed on the upper surface of the metal coating. Develop, etch, peel off the resist film, form a conductor circuit leaving only the necessary part of the metal film, form a protective film on the upper surface of the conductor circuit and the upper exposed surface of the ceramic substrate, and then mold it into chips. In a method of manufacturing a chip-type fuse, a notch is provided in three places of the conductor circuit to form a narrow portion, and the width of the conductor circuit in the central portion is narrower than the width of the left and right conductor circuits. Type fuse manufacturing method.
【０００７】本発明で用いるセラミック基板は特に制限
はないが、アルミナ基板を用いることが好ましい。また
セラミック基板の表面を粗化する方法についても特に制
限はないが、ＮａＯＨ、ＫＯＨ等のアルカリ溶融塩（粗
化液）を用いて粗化することが好ましい。The ceramic substrate used in the present invention is not particularly limited, but an alumina substrate is preferably used. The method of roughening the surface of the ceramic substrate is also not particularly limited, but it is preferable to roughen it using an alkali molten salt (roughening liquid) such as NaOH or KOH.
【０００８】金属被膜の形成方法については特に制限は
ないが、めっき法で形成することが好ましい。金属被膜
としては、可溶体の金属であれば特に制限はないが、Ｃ
ｕ、Ｚｎ、Ｓｎ等の低融点金属を用いることが好まし
い。一方電極を形成する金属被膜としては、半田付けが
容易なＣｕ、Ａｕ、Ｚｎ、Ｓｎ等の金属を用いることが
好ましい。さらに保護膜については、難燃性が必要とさ
れるため、シリコーン樹脂を用いることが好ましい。The method for forming the metal coating is not particularly limited, but it is preferably formed by a plating method. The metal coating is not particularly limited as long as it is a soluble metal, but C
It is preferable to use a low melting point metal such as u, Zn or Sn. On the other hand, it is preferable to use a metal such as Cu, Au, Zn, or Sn, which is easy to solder, as the metal film forming the electrode. Further, the protective film is required to be flame-retardant, so that it is preferable to use a silicone resin.
【０００９】切り欠き部を形成した後の中央部分の導体
回路の幅は左右の切り欠き部を形成した後の導体回路の
幅より狭くすることが必要とされ、この条件以外では溶
断時間が長くなるという欠点が生じる。また切り欠き部
を形成した後の中央部分の導体回路の幅については特に
制限はないが、２０〜５０μｍの範囲とすれば、溶断時
間をさらに短くすることができるので好ましい。The width of the conductor circuit in the central portion after forming the cutout portion needs to be narrower than the width of the conductor circuit after forming the left and right cutout portions, and otherwise the fusing time is long. There is a drawback that The width of the conductor circuit in the central portion after forming the notch is not particularly limited, but it is preferable to set it in the range of 20 to 50 μm because the fusing time can be further shortened.
【００１０】導体回路中に形成する切り欠き部は３ケ所
とされ、２ケ所以下では切り欠き部で発生した熱は、電
極を伝わって逃げてしまうという欠点が生じ、４ケ所以
上であると溶断時間は短くなるが、導体回路を形成する
際にパターンのばらつき（抵抗値のばらつき）が大きく
なり、歩留りが低下するという欠点が生じる。There are three cutouts formed in the conductor circuit, and the heat generated in the cutouts at two or less places has a drawback of escaping through the electrodes, and when there are four or more cutouts. Although the time is shortened, there is a drawback that the pattern variation (variation in resistance value) becomes large when forming the conductor circuit and the yield decreases.
【００１１】[0011]
【実施例】以下本発明の実施例を説明する。
実施例１
両端に直径が０．８ｍｍ（φ）スルーホールを形成した
アルミナセラミック基板（日立化成工業製、商品名ハロ
ックス５５２、寸法３．２×１．６×厚さ０．６３５ｍ
ｍ）を脱脂液（日立化成工業製、商品名ＨＣＲ−２０
１）で洗浄し、乾燥後３５０℃に加熱したＮａＯＨ融液
中に１０分間浸漬して粗化を行い、図３の（ａ）に示す
ようなアルミナセラミツク基板２を得た。粗化後、濃度
１０重量％のＨ2ＳＯ4溶液中に５分間浸漬し、アルミナ
セラミック基板２の表面を中和し、ついで水洗後無電解
銅めっきを２時間行い図３の（ｂ）に示すように厚さ４
μｍの銅の被膜６を形成した。なお無電解銅めっき液
は、日立化成工業製の商品名Ｌ−５９を用いた。EXAMPLES Examples of the present invention will be described below. Example 1 Alumina ceramic substrate (both made by Hitachi Chemical Co., Ltd., trade name Harox 552, size 3.2 × 1.6 × thickness 0.635 m) having 0.8 mm (φ) through holes formed at both ends.
m) degreasing liquid (Hitachi Chemical Co., Ltd., trade name HCR-20
It was washed in 1), dried, and immersed in a NaOH melt heated at 350 ° C. for 10 minutes for roughening to obtain an alumina ceramic substrate 2 as shown in FIG. After roughening, the surface of the alumina ceramic substrate 2 is neutralized by immersing in a H 2 SO 4 solution having a concentration of 10% by weight for 5 minutes, followed by washing with water and electroless copper plating for 2 hours, as shown in FIG. Thickness 4 as shown
A μm copper coating 6 was formed. The electroless copper plating solution used was trade name L-59 manufactured by Hitachi Chemical.
【００１２】銅めっき後、感光性レジストフィルム（日
立化成工業製、商品名ＰＨＴ−８６２ＡＦ−２５）（図
示せず）を前記銅の被膜６の全表面に貼付し、さらにそ
の上面に、得られる導体回路と同形状に透明な部分を形
成したネガフィルム（図示せず）を貼付し、露光してネ
ガフィルムの透明な部分の下面に配設した感光性レジス
トフィルムを硬化させた。ついでネガフィルムを取り除
き、さらに現像して硬化していない部分、詳しくは露光
していない部分の感光性レジストフィルムを除去して図
３の（ｃ）に示すようなレジスト膜１０を形成した。し
かる後濃度２５重量％の過硫酸アンモニウムの溶液でエ
ッチングを行い、図３の（ｄ）に示すように導体回路と
して不必要な部分の銅の被膜６を除去した。この後濃度
５重量％のＮａＯＨ溶液で硬化している感光性レジスト
フィルムを剥離し、図３の（ｅ）に示すように導体回路
（可溶体部）３及び電極４を形成したセラミック配線板
を得た。After copper plating, a photosensitive resist film (PHT-862AF-25, trade name, manufactured by Hitachi Chemical Co., Ltd.) (not shown) is attached to the entire surface of the copper coating 6, and the upper surface thereof is obtained. A negative film (not shown) having a transparent portion formed in the same shape as the conductor circuit was attached and exposed to light to cure the photosensitive resist film provided on the lower surface of the transparent portion of the negative film. Then, the negative film was removed, and the photosensitive resist film in the unhardened portion, more specifically, the unexposed portion was removed by further development to form a resist film 10 as shown in FIG. 3 (c). After that, etching was performed with a solution of ammonium persulfate having a concentration of 25% by weight to remove the copper coating film 6 which is unnecessary for the conductor circuit as shown in FIG. Thereafter, the photosensitive resist film cured with a NaOH solution having a concentration of 5% by weight was peeled off, and a ceramic wiring board having a conductor circuit (fusible body portion) 3 and an electrode 4 formed thereon was formed as shown in FIG. Obtained.
【００１３】次に該セラミック配線板を水洗、乾燥後印
刷法で導体回路３の上面及びアルミナセラミック基板２
の上部露出面にシリコーン樹脂（東レ・ダウ・コーニン
グ製、商品名ＳＥ−１７００）を６０μｍの厚さに塗布
し、オーブン中で１３０℃で１５分間硬化させ、図３の
（ｆ）に示すようにシリコーン保護膜９を形成した。つ
いで脱脂液（日立化成工業製、商品名ＨＣＲ−２０１）
で洗浄し、水洗後濃度１０重量％のＨ2ＳＯ4溶液中に１
分間浸漬し、再水洗後、従来公知の方法で無電解ニッケ
ルめっき及び金めっきを施し、図３の（ｇ）に示すよう
にそれぞれ２．０μｍ及び０．１μｍのニッケルの被膜
７及び金の被膜８を形成したチップ型ヒューズ基板を得
た。なお無電解ニッケルめっき液は、日本カニゼン製の
商品名Ｓ−６８０を用い、浴温７０℃で１０分間めっき
を行い、無電解金めっき液は、ＥＥＪＡ製の商品名レク
トロレスプレップを用い、浴温９０℃で１０分間めっき
を行った。このようにして得られたチップ型ヒューズ基
板をスライングマシーン（ディスコ製、商品名ＤＡＤ−
２Ｈ−６）を用いて両端部を切断し、図１及び図２に示
すように３ヶ所に切り欠き部１１を形成したチップ型ヒ
ューズ１を得た。なお図１及び図２においては５はスル
ーホールである。得られたチップ型ヒューズの化溶体部
分である導体回路３の形状を図４に示す。なお導体回路
３の厚さは４μｍ、切り欠き部１１を形成した後の中央
部分の導体回路Ａの幅は３０μｍ、左右の導体回路Ｂの
幅は１００μｍ及び導体抵抗は０．２Ωになるよう調整
した。Next, the ceramic wiring board is washed with water, dried, and then printed to print the upper surface of the conductor circuit 3 and the alumina ceramic substrate 2.
A silicone resin (trade name SE-1700, manufactured by Dow Corning Toray Co., Ltd.) is applied to the upper exposed surface of the to a thickness of 60 μm and cured in an oven at 130 ° C. for 15 minutes, as shown in (f) of FIG. A silicone protective film 9 was formed on. Degreasing liquid (Hitachi Chemical Co., Ltd., trade name HCR-201)
After washing with water and washing with water, 1% in H 2 SO 4 solution with a concentration of 10% by weight
After immersion for a minute and rewashing with water, electroless nickel plating and gold plating were performed by a conventionally known method, and as shown in FIG. 3 (g), a nickel coating 7 and a gold coating of 2.0 μm and 0.1 μm, respectively. A chip type fuse substrate having No. 8 formed was obtained. The electroless nickel plating solution used was a product name S-680 manufactured by Kanigen Japan, and plating was performed at a bath temperature of 70 ° C. for 10 minutes. Plating was performed at a temperature of 90 ° C. for 10 minutes. A chip-type fuse substrate obtained in this manner is used as a slashing machine (manufactured by DISCO, trade name DAD-
2H-6) was used to cut both ends to obtain a chip-type fuse 1 having notches 11 formed at three positions as shown in FIGS. 1 and 2, 5 is a through hole. FIG. 4 shows the shape of the conductor circuit 3 which is the solution of the obtained chip-type fuse. The thickness of the conductor circuit 3 is 4 μm, the width of the conductor circuit A in the central portion after the notch 11 is formed is 30 μm, the widths of the left and right conductor circuits B are 100 μm, and the conductor resistance is adjusted to 0.2Ω. did.
【００１４】実施例２
実施例１と同様のアルミナセラミック基板を実施例１と
同様の方法で粗化し、以下実施例１と同様の工程を経て
チップ型ヒューズを得た。得られたチップ型ヒューズの
導体回路の形状は図４に示したものと同形状とした。な
お導体回路３の厚さは４μｍ、切り欠き部１１を形成し
た後の中央部分の導体回路Ａの幅は５５μｍ、左右の導
体回路の幅は１００μｍ及び導体抵抗は０．２Ωになる
よう調整した。Example 2 An alumina ceramic substrate similar to that in Example 1 was roughened in the same manner as in Example 1, and the same steps as those in Example 1 were performed to obtain a chip-type fuse. The shape of the conductor circuit of the obtained chip-type fuse was the same as that shown in FIG. The thickness of the conductor circuit 3 was 4 μm, the width of the conductor circuit A in the central portion after forming the notch 11 was 55 μm, the width of the left and right conductor circuits was 100 μm, and the conductor resistance was adjusted to 0.2Ω. .
【００１５】比較例１
実施例１と同様のアルミナセラミック基板を実施例１と
同様の方法で粗化し、以下実施例１と同様の工程を経て
導体回路が図５に示す形状のチップ型ヒューズを得た。
なお導体回路３の厚さは４μｍ、切り欠き部１１を形成
した後の中央部分の導体回路Ｃの幅は１００μｍ、左右
の導体回路Ｄの幅は３０μｍ及び導体抵抗は０．２Ωに
なるよう調整した。Comparative Example 1 An alumina ceramic substrate similar to that of Example 1 was roughened by the same method as that of Example 1, and the same steps as those of Example 1 were followed to obtain a chip type fuse having a conductor circuit shown in FIG. Obtained.
The thickness of the conductor circuit 3 is 4 μm, the width of the conductor circuit C in the central portion after the notch 11 is formed is 100 μm, the width of the left and right conductor circuits D is 30 μm, and the conductor resistance is adjusted to 0.2Ω. did.
【００１６】比較例２
実施例１と同様のアルミナセラミック基板を実施例１と
同様の方法で粗化し、以下実施例１と同様の工程を経て
導体回路が図６に示す形状（切り欠き部無し）のチップ
型ヒューズを得た。なお導体回路３の厚さは４μｍ及び
導体抵抗は０．２Ωになるように調整した。Comparative Example 2 An alumina ceramic substrate similar to that of Example 1 was roughened by the same method as that of Example 1, and the conductor circuit was shaped as shown in FIG. ) Chip type fuse was obtained. The thickness of the conductor circuit 3 was adjusted to 4 μm and the conductor resistance was adjusted to 0.2Ω.
【００１７】比較例３
実施例１と同様のアルミナセラミック基板を実施例１と
同様の方法で粗化し、以下実施例１と同様の工程を経て
導体回路が図７に示す形状（切り欠き部１ヶ所）のチッ
プ型ヒューズを得た。なお導体回路３の厚さは４μｍ、
切り欠き部１１を形成した後の導体回路Ｅの幅は３０μ
ｍ及び導体抵抗は０．２Ωになるよう調整した。Comparative Example 3 An alumina ceramic substrate similar to that of Example 1 was roughened by the same method as that of Example 1, and the conductor circuit having the shape shown in FIG. To obtain chip fuses. The thickness of the conductor circuit 3 is 4 μm,
The width of the conductor circuit E after forming the notch 11 is 30 μm.
m and the conductor resistance were adjusted to be 0.2Ω.
【００１８】次に各実施例及び各比較例で得られたチッ
プ型ヒューズ２５ヶ用い、導体回路に３Ａの電流を流
し、そのときの溶断時間を求めた。その結果を表１に示
す。Next, using the 25 chip-type fuses obtained in each example and each comparative example, a current of 3 A was passed through the conductor circuit, and the fusing time at that time was obtained. The results are shown in Table 1.
【００１９】[0019]
【表１】 [Table 1]
【００２０】表１から明らかなように本発明の実施例に
なるチップ型ヒューズは、比較例のチップ型ヒューズに
比較して速断性に優れ、溶断時間のばらつきの小さいこ
とがわかる。As is apparent from Table 1, the chip-type fuse according to the embodiment of the present invention is superior to the chip-type fuse of the comparative example in quick disconnection property and has less variation in fusing time.
【００２１】[0021]
【発明の効果】本発明によれば電子機器の誤動作、短絡
等の故障により生じた過電流による電子機器の発熱、火
災等の事故を防止するためのチップ型ヒューズにおい
て、量産性を維持したまま速断性を向上させ、特性の安
定性も向上させた電子機器保護用として好適なチップ型
ヒューズを提供することができる。According to the present invention, in a chip-type fuse for preventing an accident such as a heat generation or a fire of an electronic device due to an overcurrent caused by a malfunction of the electronic device or a failure such as a short circuit, the mass productivity is maintained. It is possible to provide a chip-type fuse having improved fast-acting property and improved stability of characteristics, which is suitable for protecting electronic devices.
【図１】本発明の実施例になるチップ型ヒューズの傾斜
図である。FIG. 1 is a perspective view of a chip-type fuse according to an embodiment of the present invention.
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】本発明の実施例になるチップ型ヒューズを得る
ための製造作業状態を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing operation state for obtaining a chip type fuse according to an embodiment of the present invention.
【図４】実施例１及び実施例２で得られたチップ型ヒュ
ーズの導体回路を示す平面図である。FIG. 4 is a plan view showing a conductor circuit of the chip-type fuse obtained in Examples 1 and 2.
【図５】比較例１で得られたチップ型ヒューズの導体回
路を示す平面図である。5 is a plan view showing a conductor circuit of a chip-type fuse obtained in Comparative Example 1. FIG.
【図６】比較例２で得られたチップ型ヒューズの導体回
路を示す平面図である。6 is a plan view showing a conductor circuit of a chip-type fuse obtained in Comparative Example 2. FIG.
【図７】比較例３で得られたチップ型ヒューズの導体回
路を示す平面図である。7 is a plan view showing a conductor circuit of a chip-type fuse obtained in Comparative Example 3. FIG.
１ チップ型ヒューズ ２ アルミナセラミック基板 ３ 導体回路 ４ 電極 ５ スルーホール ６ 銅の被膜 ７ ニッケルの被膜 ８ 金の被膜 ９ シリコーン保護膜 １０ レジスト膜 １１ 切り欠き部 1 chip type fuse 2 Alumina ceramic substrate 3 conductor circuit 4 electrodes 5 through holes 6 Copper coating 7 Nickel coating 8 gold coating 9 Silicone protective film 10 Resist film 11 Notch
【手続補正書】[Procedure amendment]
【提出日】平成３年８月２９日[Submission date] August 29, 1991
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１１[Correction target item name] 0011
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１１】[0011]
【実施例】以下本発明の実施例を説明する。
実施例１
両端に直径が０．８ｍｍ（φ）のスルーホールを形成し
たアルミナセラミック基板（日立化成工業製、商品名ハ
ロックス５５２、寸法８０×８０×厚さ０．６３５ｍ
ｍ）を脱指液（日立化成工業製、商品名ＨＣＲ−２０
１）で洗浄し、乾燥後３５０℃に加熱したＮａＯＨ融液
中に１０分間浸漬して粗化を行い、図３の（ａ）に示す
ようなアルミナセラミック基板２を得た。粗化後、濃度
１０重量％のＨ2ＳＯ4溶液中に５分間浸漬し、アルミナ
セラミック基板２の表面を中和し、ついで水洗後無電解
銅めっきを２時間行い図３の（ｂ）に示すように厚さ４
μｍの銅の被膜６を形成した。なお無電解銅めっき液
は、日立化成工業製の商品名Ｌ−５９を用いた。EXAMPLES Examples of the present invention will be described below. Example 1 An alumina ceramic substrate (both made by Hitachi Chemical Co., Ltd., trade name Harox 552, size 80 × 80 × thickness 0.635 m) having through holes with a diameter of 0.8 mm (φ) formed at both ends.
m) is a finger removal liquid (Hitachi Chemical Co., Ltd., trade name HCR-20
It was washed in 1), dried, and immersed in a NaOH melt heated to 350 ° C. for 10 minutes for roughening to obtain an alumina ceramic substrate 2 as shown in FIG. After roughening, the surface of the alumina ceramic substrate 2 is neutralized by immersing in a H 2 SO 4 solution having a concentration of 10% by weight for 5 minutes, followed by washing with water and electroless copper plating for 2 hours, as shown in FIG. Thickness 4 as shown
A μm copper coating 6 was formed. The electroless copper plating solution used was trade name L-59 manufactured by Hitachi Chemical.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 池田 正義 茨城県下館市大字小川1500番地 日立化成 工業株式会社下館第二工場内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Masayoshi Ikeda Hitachi Chemical, 1500 Ogawa, Shimodate City, Ibaraki Prefecture Shimodate Second Factory, Kogyo Co., Ltd.
Claims (2)
セラミック基板の表面に金属被膜を形成し、ついで金属
被膜の上面にレジスト膜を形成し、しかる後露光、現
像、エッチング、レジスト膜を剥離し、金属被膜の必要
な部分のみを残して導体回路を形成し、導体回路の上面
及びセラミック基板の上部露出面に保護膜を形成後、チ
ップ状に成形してチップ型ヒューズを製造する方法にお
いて、上記導体回路の３ケ所に切り欠き部を設けて幅の
狭い部分を形成し、このうち中央部分の導体回路の幅を
左右の導体回路の幅より狭くすることを特徴とするチッ
プ型ヒューズの製造法。1. After roughening the surface of a ceramic substrate, a metal film is formed on the surface of the ceramic substrate, and then a resist film is formed on the upper surface of the metal film, followed by exposure, development, etching and resist film formation. A method for manufacturing a chip-type fuse by peeling and forming a conductor circuit leaving only a necessary portion of a metal film, forming a protective film on the upper surface of the conductor circuit and an upper exposed surface of a ceramic substrate, and then molding the chip-like shape In the chip type fuse, notches are provided at three positions of the conductor circuit to form a narrow portion, and the width of the conductor circuit in the central portion is narrower than the width of the left and right conductor circuits. Manufacturing method.
ｍである請求項１記載のチップ型ヒューズの製造法。2. The width of the conductor circuit in the central portion is 20 to 50 μm.
The method for manufacturing a chip-type fuse according to claim 1, wherein m is m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188691A JP2581348B2 (en) | 1991-07-29 | 1991-07-29 | Manufacturing method of chip type fuse |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188691A JP2581348B2 (en) | 1991-07-29 | 1991-07-29 | Manufacturing method of chip type fuse |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0536341A true JPH0536341A (en) | 1993-02-12 |
| JP2581348B2 JP2581348B2 (en) | 1997-02-12 |
Family
ID=16228142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3188691A Expired - Lifetime JP2581348B2 (en) | 1991-07-29 | 1991-07-29 | Manufacturing method of chip type fuse |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2581348B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997026665A1 (en) * | 1996-01-22 | 1997-07-24 | Surgx Corporation | Over-voltage protection device and method for making same |
| US6064094A (en) * | 1998-03-10 | 2000-05-16 | Oryx Technology Corporation | Over-voltage protection system for integrated circuits using the bonding pads and passivation layer |
| US6130459A (en) * | 1998-03-10 | 2000-10-10 | Oryx Technology Corporation | Over-voltage protection device for integrated circuits |
| JP2001525600A (en) * | 1997-12-02 | 2001-12-11 | リッテルフューズ インコーポレイテッド | Printed circuit board assembly with integrated fusible link |
| US6373719B1 (en) | 2000-04-13 | 2002-04-16 | Surgx Corporation | Over-voltage protection for electronic circuits |
| JP2022100474A (en) * | 2020-12-24 | 2022-07-06 | 三菱電機株式会社 | Power conversion device and shutdown mechanism |
| JP2022100475A (en) * | 2020-12-24 | 2022-07-06 | 三菱電機株式会社 | Power conversion device and shutdown mechanism |
-
1991
- 1991-07-29 JP JP3188691A patent/JP2581348B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997026665A1 (en) * | 1996-01-22 | 1997-07-24 | Surgx Corporation | Over-voltage protection device and method for making same |
| JP2001525600A (en) * | 1997-12-02 | 2001-12-11 | リッテルフューズ インコーポレイテッド | Printed circuit board assembly with integrated fusible link |
| US6064094A (en) * | 1998-03-10 | 2000-05-16 | Oryx Technology Corporation | Over-voltage protection system for integrated circuits using the bonding pads and passivation layer |
| US6130459A (en) * | 1998-03-10 | 2000-10-10 | Oryx Technology Corporation | Over-voltage protection device for integrated circuits |
| US6373719B1 (en) | 2000-04-13 | 2002-04-16 | Surgx Corporation | Over-voltage protection for electronic circuits |
| JP2022100474A (en) * | 2020-12-24 | 2022-07-06 | 三菱電機株式会社 | Power conversion device and shutdown mechanism |
| JP2022100475A (en) * | 2020-12-24 | 2022-07-06 | 三菱電機株式会社 | Power conversion device and shutdown mechanism |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2581348B2 (en) | 1997-02-12 |
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