JPH053132A - Chip type multilayer ceramic capacitors - Google Patents
Chip type multilayer ceramic capacitorsInfo
- Publication number
- JPH053132A JPH053132A JP3153214A JP15321491A JPH053132A JP H053132 A JPH053132 A JP H053132A JP 3153214 A JP3153214 A JP 3153214A JP 15321491 A JP15321491 A JP 15321491A JP H053132 A JPH053132 A JP H053132A
- Authority
- JP
- Japan
- Prior art keywords
- terminal electrode
- glass
- capacitor
- multilayer ceramic
- type multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】
【目的】 機械的、熱的応力が加えられた場合でも、コ
ンデンサ性能の低下がない、高信頼性、高性能、低コス
トの面実装用チップ型積層セラミックスコンデンサを提
供する。
【構成】 端子電極５は金属成分と無機結合材とで構成
され、かつ、内部に空孔７が複数個形成されている。空
孔７の内壁はガラス６で覆われている。
【効果】 端子電極５は空孔７を有するため、外部応力
に応じて変形し、外部応力を緩和する。このため、コン
デンサ本体に加えられる応力が軽減され、耐応力性に優
れる。空孔７の内壁がガラス６で覆われているため、端
子電極５の機械的強度、耐湿性が高い。安価に製造でき
る。
(57) [Abstract] [Purpose] To provide a highly reliable, high-performance, low-cost surface-mount chip-type multilayer ceramic capacitor that does not deteriorate in capacitor performance even when mechanical or thermal stress is applied. .. [Structure] The terminal electrode 5 is composed of a metal component and an inorganic binder, and has a plurality of holes 7 formed therein. The inner wall of the hole 7 is covered with the glass 6. [Effect] Since the terminal electrode 5 has the holes 7, the terminal electrode 5 is deformed in response to external stress and relaxes the external stress. Therefore, the stress applied to the capacitor body is reduced, and the stress resistance is excellent. Since the inner wall of the hole 7 is covered with the glass 6, the mechanical strength and moisture resistance of the terminal electrode 5 are high. It can be manufactured at low cost.
Description
【０００１】[0001]
【産業上の利用分野】本発明はチップ型積層セラミック
スコンデンサに係り、特に、面実装用のチップ型積層セ
ラミックスコンデンサとして、信頼性、コンデンサ性能
に優れ、かつ低コストなチップ型積層セラミックスコン
デンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type monolithic ceramic capacitor, and more particularly to a chip type monolithic ceramic capacitor having excellent reliability and capacitor performance as a surface mounting chip type monolithic ceramic capacitor.
【０００２】[0002]
【従来の技術】チップ型積層セラミックスコンデンサ
は、面実装用部品として広く用いられている。その構造
は、内部電極とセラミックス誘電体とを交互に積層しチ
ップの端面に、内部電極の取り出し部分を設け、その上
を覆うように外部接続用の端子電極が形成されたものと
なっている。この端子電極は、耐湿性を確保するため、
なるべく緻密な構造となるように作製される。2. Description of the Related Art Chip type multilayer ceramic capacitors are widely used as surface mounting parts. The structure is such that internal electrodes and ceramics dielectrics are alternately laminated, an end portion of the chip is provided on the end face of the chip, and a terminal electrode for external connection is formed so as to cover it. .. This terminal electrode, in order to ensure moisture resistance,
It is manufactured so as to have a dense structure as much as possible.
【０００３】[0003]
【発明が解決しようとする課題】チップ型積層セラミッ
クスコンデンサは、端子電極を介して基板に装着されて
使用される。このため、基板の歪みや振動、基板とコン
デンサを構成するセラミックスとの熱膨張差などに起因
する応力は、端子電極を介してコンデンサチップに伝わ
り、コンデンサ内部にクラックを発生させる。これによ
り、コンデンサの実装時や基板の分割時に、容量低下、
絶縁不良等の不良が発生するという問題点があった。特
に、自動車への搭載などの過酷環境での使用時には、信
頼性が著しく低下するという問題があった。A chip type multilayer ceramic capacitor is used by being mounted on a substrate via a terminal electrode. Therefore, the stress caused by the distortion and vibration of the substrate, the difference in thermal expansion between the substrate and the ceramics forming the capacitor is transmitted to the capacitor chip via the terminal electrode, and a crack is generated inside the capacitor. This reduces the capacitance when mounting capacitors and dividing the board.
There has been a problem that defects such as poor insulation occur. In particular, when used in a harsh environment such as mounting on an automobile, there is a problem that reliability is significantly reduced.
【０００４】本発明は、上記従来の問題点を解決し、機
械的、熱的応力が加えられた場合でも、コンデンサ性能
の低下をひき起こすことがない、信頼性に優れた高性能
チップ型積層セラミックスコンデンサを提供することを
目的とする。The present invention solves the above-mentioned problems of the prior art, and does not cause deterioration of capacitor performance even when mechanical or thermal stress is applied, and is a highly reliable high performance chip type laminate. An object is to provide a ceramic capacitor.
【０００５】[0005]
【課題を解決するための手段】本発明のチップ型積層セ
ラミックスコンデンサは、内部電極とセラミックス誘電
体とが交互に積層されてなるコンデンサ本体の端面に、
該内部電極と導通する端子電極が設けられたチップ型積
層セラミックスコンデンサにおいて、該端子電極は金属
成分と、無機結合材とで構成され、かつ、内部に空孔が
複数個形成されたものであって、該空孔の内壁がガラス
で覆われていることを特徴とする。A chip type multilayer ceramic capacitor according to the present invention is provided with an end face of a capacitor body in which internal electrodes and ceramic dielectrics are alternately laminated,
A chip-type multilayer ceramic capacitor provided with a terminal electrode that is electrically connected to the internal electrode, wherein the terminal electrode is composed of a metal component and an inorganic binder and has a plurality of holes formed therein. The inner wall of the hole is covered with glass.
【０００６】以下に本発明を図面を参照して詳細に説明
する。第１図は本発明のチップ型積層セラミックスコン
デンサの一実施例を示す端子電極近傍の断面図であり、
第２図〜第４図は、端子電極形成工程における微細構造
の変化を示す模式的断面図である。The present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of the vicinity of terminal electrodes showing an embodiment of the chip type multilayer ceramic capacitor of the present invention.
2 to 4 are schematic cross-sectional views showing changes in the fine structure in the terminal electrode forming step.
【０００７】第１図に示す如く、実施例のチップ型積層
セラミックスコンデンサ１は、内部電極２とセラミック
ス誘電体３とが交互に積層されてなるコンデンサ本体４
の両端面に内部電極２と導通する端子電極５が形成され
たものである。なお、第１図は、コンデンサ１の一端側
のみを示し、他端側も同様な構成とされている。即ち、
図示の端子電極５は内部電極２ａ，２ｃ，２ｅに導通す
るものであるが、他端側にも内部電極２ｂ，２ｄと導通
する端子電極が設けられている。As shown in FIG. 1, the chip type multilayer ceramic capacitor 1 of the embodiment has a capacitor body 4 in which internal electrodes 2 and ceramic dielectrics 3 are alternately laminated.
The terminal electrodes 5 that are electrically connected to the internal electrodes 2 are formed on both end surfaces of the. Note that FIG. 1 shows only one end side of the capacitor 1, and the other end side has the same configuration. That is,
Although the illustrated terminal electrode 5 is electrically connected to the internal electrodes 2a, 2c, 2e, a terminal electrode electrically connected to the internal electrodes 2b, 2d is also provided on the other end side.
【０００８】本発明において、この端子電極５は金属成
分と無機結合材とで構成され、かつ、内部に、内壁がガ
ラス６で覆われた空孔７が複数個形成されたものであ
る。In the present invention, the terminal electrode 5 is composed of a metal component and an inorganic binder, and has a plurality of holes 7 whose inner wall is covered with glass 6 formed therein.
【０００９】以下に本発明に係る端子電極の形成方法に
ついて説明する。従来、端子電極は、一般に、金属粒子
（銀、パラジウム、金、白金、ニッケルなど）と無機結
合材及び有機ビヒクル（バインダー）からなる端子電極
ペーストを、コンデンサチップの両端に塗布し、空気中
又は窒素中で焼成して形成されている。ここで金属粒子
は内部電極との電気的な接続の目的で用いられ、無機結
合材は、端子電極をセラミックス素地に強固に接着させ
る作用を持ち、通常は無機ガラスが用いられる。このよ
うな方法において、次のようにガラスの軟化温度（用い
るガラス粒子の粒度）を調整することにより、本発明に
係る端子電極構造を実現することができる。The method of forming the terminal electrode according to the present invention will be described below. Conventionally, a terminal electrode is generally prepared by applying a terminal electrode paste composed of metal particles (silver, palladium, gold, platinum, nickel, etc.), an inorganic binder and an organic vehicle (binder) to both ends of a capacitor chip in the air or It is formed by firing in nitrogen. Here, the metal particles are used for the purpose of electrical connection with the internal electrodes, and the inorganic binder has a function of firmly adhering the terminal electrode to the ceramic body, and usually inorganic glass is used. In such a method, the terminal electrode structure according to the present invention can be realized by adjusting the softening temperature of glass (particle size of glass particles used) as follows.
【００１０】無機結合材として添加するガラス粒子は通
常微粉末が用いられるが、本発明では微粉末と共に粗大
な粒子を用いる。この場合微粉末のガラス粒子は従来の
端子電極の無機結合材と同様、セラミックス素地への接
着のために作用する。一方、粗大粒子のガラス粉末は、
その軟化温度を端子電極金属の焼結完了温度以上に設定
する作用を奏する。このように、ガラスの軟化温度を上
げて、ガラス粒子のうちの粗大粒子は、金属粒子の焼結
完了後に溶融するように軟化温度を設定することによ
り、端子電極形成時の焼成工程では、端子電極形成材料
中の各成分は、その焼成温度に応じて以下のように変化
する。Fine particles are usually used as the glass particles added as the inorganic binder, but in the present invention, coarse particles are used together with the fine particles. In this case, the finely-divided glass particles act for adhesion to the ceramic body, similarly to the conventional inorganic binder for terminal electrodes. On the other hand, the glass powder of coarse particles is
The softening temperature is set to be equal to or higher than the sintering completion temperature of the terminal electrode metal. Thus, by increasing the softening temperature of the glass, coarse particles of the glass particles, by setting the softening temperature so as to melt after the completion of the sintering of the metal particles, in the firing step during the formation of the terminal electrode, Each component in the electrode forming material changes as follows according to the firing temperature.
【００１１】[0011]
【表１】 [Table 1]
【００１２】ここで、金属粒子の粒径を適当に設定する
ことにより、焼結完了時に多少の空隙を残存させること
ができ、溶融した粗大ガラス粒子は、その空隙を満た
す。その後、更に温度を上げて焼成することにより、溶
融した粗大ガラス粒子が流動して金属焼結相の隙間に入
り込み、粗大ガラス粒子の存在した部分は空孔となり、
内壁がガラスで覆われた状態の空孔が形成される。[0012] Here, by appropriately setting the particle size of the metal particles, some voids can be left after the completion of sintering, and the fused coarse glass particles fill the voids. After that, by further raising the temperature and firing, the molten coarse glass particles flow into the gaps of the metal sintered phase, and the portions where the coarse glass particles exist become voids,
Voids whose inner wall is covered with glass are formed.
【００１３】即ち、端子電極形成材料をコンデンサチッ
プの端面に塗布した直後、室温では、第２図に示す如
く、有機ビヒクル１１をバインダーとして、金属粒子
（例えば、Ａｇ粒子）１２、微細ガラス粒子１３及び粗
大ガラス粒子１４が分散した状態である。That is, immediately after the terminal electrode forming material is applied to the end surface of the capacitor chip, at room temperature, as shown in FIG. And the coarse glass particles 14 are dispersed.
【００１４】次に、これを６００℃程度の温度で脱バイ
ンダー処理した後は、第３図に示す如く、有機ビヒクル
は既に消失し、焼結初期の金属粒子１５の間に、溶融し
て流動し始めた微細ガラス粒子１６と表面が若干流動状
態となった粗大ガラス粒子１７とが存在する状態とな
る。Next, after the binder removal treatment at a temperature of about 600 ° C., as shown in FIG. 3, the organic vehicle has already disappeared, and it melts and flows between the metal particles 15 in the initial stage of sintering. The fine glass particles 16 that have begun to operate and the coarse glass particles 17 whose surface is in a slightly fluidized state are present.
【００１５】そして、更に焼成温度を上げ、７００〜８
００℃付近で焼結させると、第４図に示す如く、焼結が
完了した金属相１８間に溶融ガラス１９が流動して浸入
し、このガラスの溶融、流動により、粗大ガラス粒子が
存在していた部分に、ガラスが流動後、表面がガラス１
９で覆われた空孔２０が形成される。Then, the firing temperature is further raised to 700 to 8
When sintered at around 00 ° C., as shown in FIG. 4, the molten glass 19 flows and infiltrates between the sintered metal phases 18, and due to the melting and flowing of this glass, coarse glass particles exist. After the glass has flowed to the part where it was, the surface is glass 1.
A hole 20 covered with 9 is formed.
【００１６】なお、ガラスの流動開始温度はその粒径に
依存し、粒径が小さいほど低温で流動を開始する。この
ため、用いるガラス粒子は、粗大粒子も微細粒子もその
組成は同一のものとすることができる。The flow starting temperature of glass depends on the particle size, and the smaller the particle size, the lower the temperature at which the glass starts to flow. Therefore, the glass particles to be used can have the same composition in both coarse particles and fine particles.
【００１７】上記方法において、用いる金属粒子、微細
ガラス粒子及び粗大ガラス粒子の各々の粒径や割合、焼
成温度や焼成時間を適宜設定することにより、所望の空
孔率、空孔径ガラス被覆層厚さの端子電極を形成するこ
とができる。In the above method, the desired porosity and pore diameter glass coating layer thickness can be obtained by appropriately setting the particle size and ratio of the metal particles, fine glass particles and coarse glass particles used, the firing temperature and the firing time. Terminal electrodes can be formed.
【００１８】本発明においては、端子電極内部の空孔の
大きさは、その端子電極の厚み方向で１０〜５０μｍ程
度、端子電極の幅方向で３０〜１００μｍ程度、また、
その空孔率は５〜３０体積％程度、空孔の内壁を覆うガ
ラス層の厚さは０．１〜５μｍ程度であることが好まし
い。即ち、空孔の大きさ及び空孔率が上記範囲よりも小
さいと、本発明による改善効果が十分に得られず、逆に
上記範囲よりも大きいと、端子電極の機械的強度が不足
する。また、ガラス層の厚さが０．１μｍ未満では端子
電極の耐湿性が劣り、１０μｍを超えると本発明に十分
な空孔率、空孔径を確保できない。In the present invention, the size of the holes inside the terminal electrode is about 10 to 50 μm in the thickness direction of the terminal electrode, about 30 to 100 μm in the width direction of the terminal electrode, and
The porosity is preferably about 5 to 30% by volume, and the thickness of the glass layer covering the inner walls of the pores is preferably about 0.1 to 5 μm. That is, when the size and the porosity of the pores are smaller than the above range, the improvement effect of the present invention cannot be sufficiently obtained, and conversely, when it is larger than the above range, the mechanical strength of the terminal electrode becomes insufficient. Further, if the thickness of the glass layer is less than 0.1 μm, the moisture resistance of the terminal electrode is inferior, and if it exceeds 10 μm, the porosity and the pore diameter sufficient for the present invention cannot be secured.
【００１９】なお、本発明のチップ型積層セラミックス
コンデンサは、端子電極を上述の構成とすること以外
は、従来のチップ型積層セラミックスコンデンサと同様
の構成とすることができ、内部電極、セラミックス誘電
体の材質等に特に制限はない。The chip-type multilayer ceramic capacitor of the present invention can have the same structure as the conventional chip-type multilayer ceramic capacitor except that the terminal electrodes have the above-described structure. There is no particular limitation on the material of the.
【００２０】[0020]
【作用】本発明においては、端子電極内に空孔が存在す
るため、そのヤング率が従来の緻密な端子電極に比べて
低いものとなる。このため、外部から機械的、熱的応力
が加えられた場合、この端子電極が柔軟に変形して、外
部からの応力を緩和する。この端子電力による応外緩衝
作用により、コンデンサチップ本体に加えられる応力が
軽減される。In the present invention, since the holes are present in the terminal electrode, the Young's modulus thereof is lower than that of the conventional dense terminal electrode. Therefore, when mechanical or thermal stress is applied from the outside, the terminal electrode is flexibly deformed, and the stress from the outside is relaxed. This external buffering effect by the terminal power reduces the stress applied to the capacitor chip body.
【００２１】なお、空孔の存在は、強度の低下、耐湿性
の低下の原因となるが、本発明のチップ型積層セラミッ
クスコンデンサでは、空孔の内壁がガラスで覆われてい
るため、このガラス被覆層による補強効果及び遮断効果
により、端子電極の機械的強度及び耐湿性は十分に確保
される。The presence of pores causes a decrease in strength and a decrease in moisture resistance. However, in the chip-type multilayer ceramic capacitor of the present invention, the inner walls of the pores are covered with glass, so this glass Due to the reinforcing effect and the blocking effect of the coating layer, the mechanical strength and moisture resistance of the terminal electrode are sufficiently ensured.
【００２２】[0022]
【実施例】以下に実施例及び比較例を挙げて本発明をよ
り具体的に説明する。 実施例１ 下記コンデンサ本体を用い、その両端面に下記端子電極
を形成してチップ型積層セラミックスコンデンサを作製
し、後述の試験を行ない、結果を表２に示した。なお、
端子電極焼付後、電気めっき法によって端子電極表面に
Ｎｉとはんだの２層のめっきを施した。Ｎｉは市販のス
ルファミン酸浴、はんだは市販のスルホン酸浴を使用
し、めっき膜厚はＮｉが１ミクロン、はんだが５ミクロ
ンとした。EXAMPLES The present invention will be described more specifically with reference to Examples and Comparative Examples. Example 1 A chip-type multilayer ceramic capacitor was manufactured by using the following capacitor body and forming the following terminal electrodes on both end faces thereof, and the following test was conducted. The results are shown in Table 2. In addition,
After baking the terminal electrode, two layers of Ni and solder were plated on the surface of the terminal electrode by electroplating. A commercially available sulfamic acid bath was used for Ni, and a commercially available sulfonic acid bath was used for solder, and the plating film thickness was 1 micron for Ni and 5 micron for solder.
【００２３】コンデンサ本体：三菱マテリアル（株）製
「Ｃ３０Ｒ１Ｈ１０４Ｋ」 静電容量＝１０２．０±１．５ｎＦ，ＪＩＳ−Ｒ特性， 定格電圧＝５０Ｖ 端子電極 ：三菱マテリアル（株）製 Ａｇ電極 Ａｇ７５重量％，無機結合材４．５重量％，有機ビヒク
ル残部。無機結合材はＰｂＯ−ＺｎＯ−ＳｉＯ2 −Ｂ2
Ｏ3 系ガラス（バルクの軟化点６１０℃）で、ガラス粒
径３〜１５ミクロンのものを５０％，５０〜７５ミクロ
ンのものを５０％混合して使用した。端子電極は光洋リ
ンドバーグ（株）製ベルト炉を用い、最高温度６６０℃
で保持５分、昇降温は３０分として焼成した。Capacitor body: "C30R1H104K" manufactured by Mitsubishi Materials Corp. Capacitance = 102.0 ± 1.5 nF, JIS-R characteristics, rated voltage = 50V Terminal electrode: Ag electrode Ag 75% by weight manufactured by Mitsubishi Materials Corp. , 4.5% by weight of inorganic binder, balance of organic vehicle. Inorganic binder PbO-ZnO-SiO 2 -B 2
O 3 type glass (bulk softening point 610 ° C.) having a glass particle size of 3 to 15 μm and 50% and 50 to 75 μm were mixed and used. The terminal electrode uses a belt furnace made by Koyo Lindbergh Co., Ltd., and the maximum temperature is 660 ° C.
The temperature was maintained for 5 minutes, and the temperature was raised and lowered for 30 minutes for firing.
【００２４】試験項目及び試験条件 サーマルショック試験：表２に示す各温度の溶融は
んだ（Ｐｂ／Ｓｎ＝３７／６３）に、予熱を行わずにコ
ンデンサを浸漬し、３秒間加熱した後空気中で放冷し
た。その後、顕微鏡による外観検査を行い、クラック発
生の有無を検査した。クラック発生のない試料は絶縁抵
抗を測定し、絶縁不良の有無を検査し、試料１００個中
の不良発生数で示した。 温度サイクル試験 ：アルミナ基板にコンデンサ
を実装し（リフローはんだ付け）、気相式温度衝撃試験
機にて以下の条件で温度サイクル試験を行った。静電容
量の低下、絶縁抵抗劣化を検査し、試料３０個中の不良
発生数で示した。検査は、２５，５０，１００，１５
０，２００サイクル終了後に行った。 −５５℃，３０分■室温３分■１２５℃３０分 限界たわみ試験(n=5) ：ガラスエポキシ基板（厚さ
＝１．６ｍｍ，幅＝４０ｍｍ）にコンデンサを実装し、
強度試験器を用い、スパン９０ｍｍで３点曲げを行い、
容量低下が発生する押し込み量を測定した。結果は、試
料５個の最大、最小、平均値で示した。 Test items and test conditions Thermal shock test: A capacitor was immersed in molten solder (Pb / Sn = 37/63) at each temperature shown in Table 2 without preheating, heated for 3 seconds, and then in air. I let it cool. After that, the appearance was inspected with a microscope to inspect whether cracks were generated. The samples without cracks were measured for insulation resistance and inspected for insulation defects, and the number of defects in 100 samples was shown. Temperature cycle test: A capacitor was mounted on an alumina substrate (reflow soldering), and a temperature cycle test was conducted under the following conditions with a vapor phase temperature shock tester. The decrease of electrostatic capacity and the deterioration of insulation resistance were inspected, and the number of defects in 30 samples was shown. Inspection is 25, 50, 100, 15
It was carried out after completion of 0,200 cycles. -55 ℃, 30 minutes ■ Room temperature 3 minutes ■ 125 ℃ 30 minutes Deflection test (n = 5): Mount a capacitor on a glass epoxy board (thickness = 1.6mm, width = 40mm),
Using a strength tester, perform 3-point bending with a span of 90 mm,
The indentation amount at which the capacity decrease occurs was measured. The results are shown as the maximum, minimum and average values of 5 samples.
【００２５】比較例１ 端子電極の無機結合材として、ガラス粒径が３〜１５ミ
クロンのものを１００％使用したこと以外は同様にして
チップ型積層セラミックスコンデンサを作製して試験を
行ない、結果を表２に示した。Comparative Example 1 A chip-type multilayer ceramic capacitor was prepared and tested in the same manner except that 100% of the inorganic binder for the terminal electrode had a glass particle size of 3 to 15 μm, and the results were obtained. The results are shown in Table 2.
【００２６】[0026]
【表２】 [Table 2]
【００２７】表２より、本発明のチップ型積層セラミッ
クスコンデンサは、従来のものに比べて、著しく優れた
耐熱応力性、耐歪応力性を示すことが明らかである。な
お、実施例１で作製したチップ型積層セラミックスコン
デンサの端子電極の空孔率、空孔径、空孔内壁のガラス
被覆層厚さを調べたところ、次のような値であった。 空孔率：２５体積％ 空孔径：端子電極の厚み方向で２０〜３０μｍ、 端子電極の幅方向で４０〜６０μｍ ガラス被覆層厚さ：１〜２μｍFrom Table 2, it is clear that the chip type multilayer ceramic capacitor of the present invention exhibits remarkably excellent heat stress resistance and strain stress resistance as compared with the conventional ones. The porosity of the terminal electrode of the chip-type multilayer ceramic capacitor manufactured in Example 1, the hole diameter, and the thickness of the glass coating layer on the inner wall of the hole were as follows. Porosity: 25% by volume Porosity: 20 to 30 μm in the thickness direction of the terminal electrode, 40 to 60 μm in the width direction of the terminal electrode Glass coating layer thickness: 1 to 2 μm
【００２８】[0028]
【発明の効果】以上詳述した通り、本発明のチップ型積
層セラミックスコンデンサは、その端子電極により、外
部から加えられる機械的、熱的応力を緩和することがで
き、この結果、外部応力に強い、高信頼性で高性能のコ
ンデンサを提供することが可能とされる。本発明のチッ
プ型積層セラミックスコンデンサは、従来と同様の材料
及び設備を利用して低コストで作製可能であり、その工
業的有用性は極めて大きい。As described in detail above, the chip type multilayer ceramic capacitor of the present invention can relieve mechanical and thermal stress applied from the outside by its terminal electrode, and as a result, it is resistant to external stress. It is possible to provide a highly reliable and high performance capacitor. The chip type multilayer ceramic capacitor of the present invention can be manufactured at low cost by using the same materials and equipment as conventional ones, and its industrial utility is extremely large.
【図１】第１図は本発明の一実施例を示す要部断面図で
ある。FIG. 1 is a sectional view of an essential part showing an embodiment of the present invention.
【図２】第２図は端子電極形成工程における塗布直後の
微細構造を示す模式的断面図である。FIG. 2 is a schematic cross-sectional view showing a fine structure immediately after coating in a terminal electrode forming step.
【図３】第３図は端子電極形成工程における焼成初期の
微細構造を示す模式的断面図である。FIG. 3 is a schematic cross-sectional view showing a fine structure in the initial stage of firing in the step of forming a terminal electrode.
【図４】第４図は端子電極形成工程における焼成後期の
微細構造を示す模式的断面図である。FIG. 4 is a schematic cross-sectional view showing a fine structure in the latter stage of firing in the terminal electrode forming step.
１ チップ型積層セラミックスコンデンサ ２ 内部電極 ３ セラミックス誘電体 ４ コンデンサ本体 ５ 端子電極 ６ ガラス ７ 空孔 1 Chip Type Multilayer Ceramics Capacitor 2 Internal Electrode 3 Ceramics Dielectric 4 Capacitor Body 5 Terminal Electrode 6 Glass 7 Hole
Claims (1)
に積層されてなるコンデンサ本体の端面に、該内部電極
と導通する端子電極が設けられたチップ型積層セラミッ
クスコンデンサにおいて、該端子電極は金属成分と、無
機結合材とで構成され、かつ、内部に空孔が複数個形成
されたものであって、該空孔の内壁がガラスで覆われて
いることを特徴とするチップ型積層セラミックスコンデ
ンサ。Claim: What is claimed is: 1. A chip-type multilayer ceramic capacitor comprising: a capacitor body having internal electrodes and ceramic dielectrics alternately laminated; and a terminal electrode electrically connected to the internal electrodes provided on an end surface of the capacitor body. The terminal electrode is composed of a metal component and an inorganic binder, and has a plurality of holes formed therein, and the inner walls of the holes are covered with glass. Chip type multilayer ceramic capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3153214A JP2867748B2 (en) | 1991-06-25 | 1991-06-25 | Chip type multilayer ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3153214A JP2867748B2 (en) | 1991-06-25 | 1991-06-25 | Chip type multilayer ceramic capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH053132A true JPH053132A (en) | 1993-01-08 |
| JP2867748B2 JP2867748B2 (en) | 1999-03-10 |
Family
ID=15557546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3153214A Expired - Lifetime JP2867748B2 (en) | 1991-06-25 | 1991-06-25 | Chip type multilayer ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2867748B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002015944A (en) * | 2000-06-30 | 2002-01-18 | Kyocera Corp | Ceramic capacitors |
| JP2010073780A (en) * | 2008-09-17 | 2010-04-02 | Murata Mfg Co Ltd | Ceramic electronic component, and method for manufacturing the same |
| JP2015162673A (en) * | 2014-02-27 | 2015-09-07 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Multilayer ceramic capacitor and mounting board for the same |
| US20160196922A1 (en) * | 2013-09-24 | 2016-07-07 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component |
| JP2018157183A (en) * | 2016-09-28 | 2018-10-04 | 株式会社村田製作所 | Electronic components |
| US11488780B2 (en) | 2020-09-19 | 2022-11-01 | Murata Manufacturing Co., Ltd. | Ceramic electronic component |
| CN115938801A (en) * | 2021-10-05 | 2023-04-07 | Tdk株式会社 | Ceramic Electronic Components |
| JP2023157118A (en) * | 2022-04-14 | 2023-10-26 | 株式会社村田製作所 | Multilayer ceramic electronic component |
| WO2024135256A1 (en) | 2022-12-19 | 2024-06-27 | 株式会社村田製作所 | Layered ceramic electronic component |
| WO2024161946A1 (en) * | 2023-01-30 | 2024-08-08 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| US12308171B2 (en) | 2020-09-19 | 2025-05-20 | Murata Manufacturing Co., Ltd. | Method for producing ceramic electronic component |
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| JP7314884B2 (en) * | 2020-08-31 | 2023-07-26 | 株式会社村田製作所 | Laminated ceramic electronic component and manufacturing method thereof |
-
1991
- 1991-06-25 JP JP3153214A patent/JP2867748B2/en not_active Expired - Lifetime
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002015944A (en) * | 2000-06-30 | 2002-01-18 | Kyocera Corp | Ceramic capacitors |
| JP2010073780A (en) * | 2008-09-17 | 2010-04-02 | Murata Mfg Co Ltd | Ceramic electronic component, and method for manufacturing the same |
| US20160196922A1 (en) * | 2013-09-24 | 2016-07-07 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component |
| US9978519B2 (en) * | 2013-09-24 | 2018-05-22 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component |
| JP2015162673A (en) * | 2014-02-27 | 2015-09-07 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Multilayer ceramic capacitor and mounting board for the same |
| US9685272B2 (en) | 2014-02-27 | 2017-06-20 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic capacitor having multilayer external electrodes and board having the same |
| JP2018157183A (en) * | 2016-09-28 | 2018-10-04 | 株式会社村田製作所 | Electronic components |
| US11488780B2 (en) | 2020-09-19 | 2022-11-01 | Murata Manufacturing Co., Ltd. | Ceramic electronic component |
| US12308171B2 (en) | 2020-09-19 | 2025-05-20 | Murata Manufacturing Co., Ltd. | Method for producing ceramic electronic component |
| CN115938801A (en) * | 2021-10-05 | 2023-04-07 | Tdk株式会社 | Ceramic Electronic Components |
| JP2023157118A (en) * | 2022-04-14 | 2023-10-26 | 株式会社村田製作所 | Multilayer ceramic electronic component |
| WO2024135256A1 (en) | 2022-12-19 | 2024-06-27 | 株式会社村田製作所 | Layered ceramic electronic component |
| EP4621819A1 (en) | 2022-12-19 | 2025-09-24 | Murata Manufacturing Co., Ltd. | Layered ceramic electronic component |
| WO2024161946A1 (en) * | 2023-01-30 | 2024-08-08 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2867748B2 (en) | 1999-03-10 |
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