JPH05303892A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To improve the data holding characteristic of a memory cell C1 by raising the cell ratio of the memory cell C1. CONSTITUTION:A constant voltage source circuit C3 supplying a lower voltage than the source voltage applied to the memory cell C1 part is connected to a word line drive circuit driving the word line W of the memory cell C1 and the high level of the word line W becomes low. Then, the power of the NMOS transistor for a transfer gate of the memory cell C1 is lowered and the cell ratio is raised and the data holding characteristic is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit,
In particular, the present invention relates to a circuit configuration for improving the data holding capacity of SRAM using MOS transistors.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional semiconductor memory circuit.

In FIG. 3, this semiconductor memory circuit includes a high resistance load type memory cell C1, a word line driving NOR gate circuit C2, and digit line load p-type MOS transistors M5 and M6, and a power supply voltage VCC. , VEE is applied.

Here, the memory cell C1 includes resistors R1 and R1.
2 and N-type MOS transistors M1 to M4. One end of each of the resistors R1 and R2 is connected to a node (node) N1.
N2. The output of the NOR gate circuit C2 becomes the word line W, and has two digit lines D and D (inverted values) which are vertical lines.

When the memory cell C1 is selected, the control signal Y1 for the digit line load P-type MOS transistors M5 and M6 is selected.
Is at a low level and the word line W is at a high level. Usually, this high level is at the same level as the power supply voltage VCC.
Then, the data holding n-type MOS transistors M3 and M4 forming the flip-flop circuit in the memory cell C1.
When the transistor M3 is off and the transistor M4 is on, the potentials of the nodes N1 and N2, which are the gate potentials of the nodes N1 and N2, are high and low, respectively.

It holds the data of [0] or [1].

[0006]

Generally, a so-called cell ratio is used as an index of data retention characteristics of a memory cell. The cell ratio means the gate length of the n-type MOS transistor M1 in FIG. 3 is L _M1 , the gate width is W _M1 , the gate voltage is V _GM1 , the gate length of _M3 is L _M3 , and the gate width is W _M1 .
_{When M3} , the gate voltage is V _GM3 , and the threshold voltage of the n-type MOS transistor is V _T , it is expressed by the following equation.

Cell ratio = {(W _M3 / L _M3 ) ・ (V _GM3
−V _T ) ² } / {(W _M1 / L _M1 ) · (V _GM1 −
V _T ) ² } Then, the larger this value, the more stable the data retention characteristic of the memory cell. In the conventional circuit, if the cell ratio is to be increased, the data holding n-type MOS transistor M
It is necessary to increase the gate width of No. 3 and the memory cell area increases. On the other hand, when the transistor size is reduced to reduce the memory cell area, the data retention characteristic of the memory cell deteriorates. ..

An object of the present invention is to solve the above problems and provide a semiconductor memory device having a large cell ratio without deteriorating the data retention characteristics of the memory cell.

[0009]

According to the structure of the semiconductor memory circuit of the present invention, the potential at the time of selecting the word line of the memory cell including the flip-flop circuit formed by cross-connecting the input and output terminals of the pair of inverters is A means for lowering the power supply voltage applied to the memory cell is provided.

[0010]

1 is a circuit diagram of a semiconductor memory circuit according to an embodiment of the present invention.

In FIG. 1, this embodiment comprises a constant voltage source circuit C3, a word line driving NOR gate circuit C2, a memory cell C1, and digit line load p-type MOS transistors M5 and M6, and controls them. The signal Y1 is applied and the power supply voltages VCC and VEE are supplied.

Here, the memory cell C1 includes resistors R1 and R1.
2, n-type MOS transistors M1 to M4. NO
The output of the R gate circuit C2 becomes the word line W, and the digit lines D and D (inverted value) are provided in the vertical direction.

The word line driving NOR gate circuit C2 for determining the level of the word line W operates by the constant power source voltage supplied by the constant voltage source circuit C3. Therefore, for example, the output voltage of the constant voltage source circuit C3 is 4 [ V], the high level of the word line W becomes 4 [V].

FIG. 5 shows a very simple example of the constant voltage source circuit C3, which outputs a constant voltage by changing the ratio of the resistors Ra and Rb. For example, Ra = 1K
Ω, Rb = 4 KΩ, constant power supply voltage VCC-VEE = 5
When viewed as [V], the output OUT is 4 [V].

Threshold voltage V of n-type MOS transistor
_{When T} = 0.7 [V], the cell ratio is as follows.

Cell ratio = {(W _M3 / L _M3 ) ・ (5-
0.7) ² } / {(W _M1 / L _M1 ) ・ (4-0.7) ² }
= 1.7 × (W _M3 / L _M3 ) / (W _M1 / L _M1 ) That is, the cell ratio can be increased 1.7 times without changing the size of the n-type MOS transistor of the memory cell. Further, the impedance of the n-type MOS transistor M1 is about 1. When the gate voltage becomes 80%.
25 times larger, the potential of the node N1 drops further, the potential difference between the nodes N1 and N2 increases, and the memory cell C1 becomes more stable.

As a result, as shown in FIG. 4, the cell ratio can be increased when the cell area is constant, and the cell area can be reduced when the cell ratio is constant. In FIG. 4, characteristic line 4
Reference numeral 1 is a conventional example, and characteristic line 42 is this embodiment. The vertical axis shows the cell area and the horizontal axis shows the cell ratio.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. In FIG. 2, in the present embodiment, the power supply voltage of the p-type MOS transistors M5 and M6 for digit line load is also supplied by the constant voltage source circuit C3. Other parts are the same as in FIG. The node potential of the memory cell C1 is the resistance of the power supply voltage due to the p-type MOS transistors M5 and M6 for digit line load, the n-type MOS transistors M1 and M2 for transmission gates of the memory cell, and the n-type MOS transistors M3 and M4 for holding data. Since these are determined by division, these MOS
When the power supply voltage of the transistors M5 and M6 is lowered, the level of the node on the low level side becomes closer to the voltage VEE level, and the level difference between the nodes N1 and N2 increases.
As a result, the data holding capacity is further improved.

[0019]

As described above, according to the present invention, since the word line potential of the memory cell is set lower than the power supply voltage applied to the memory cell, the cell ratio can be increased and the memory cell can be selected. It is possible to improve the data retention characteristic of the memory cell and to reduce the memory cell area for the memory cell having a sufficient cell ratio.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional memory cell.

FIG. 4 is a characteristic diagram showing the effect of FIG.

5 is a circuit diagram showing an example of the constant voltage source circuit of FIG.

[Explanation of symbols]

C1 memory cell M1 to M4 n-type MOS transistor R1, R2, Ra, Rb resistance M5, M6 digit line load p-type MOS transistor W word line D, D (inverted value) digit line C2 word line driving NOR gate circuit C3 Constant voltage source circuit 41, 42 Characteristic line N1, N2 node

Claims (2)

[Claims] 1. A semiconductor memory device including, in a memory cell, a flip-flop circuit in which input and output terminals of a pair of inverters are cross-connected to each other, wherein a potential of a word line when the memory cell is in a selected state is the memory cell. A semiconductor memory circuit comprising means for lowering the power supply voltage applied to the cell itself. 2. The semiconductor memory circuit according to claim 1, further comprising means for lowering the potential of the digit line when the memory cell is selected to a level equivalent to the potential of the word line.