JPH05291303A - Formation of negative resist pattern - Google Patents

Abstract

PURPOSE:To form a negative resist pattern for forming a high-productivity T-shaped gate electrode pattern by means of an inexpensive equipment for high-speed operation of a gallium arsenide (GaAs) IC. CONSTITUTION:A first recess pattern 54 is formed in a negative resist layer 52 by photolithography. In order to prevent the mixing with resist to be applied in the next process, a mixing prevention layer 56 is formed. Negative resist is applied again onto the mixing prevention layer 56 as an upper-layer resist layer 60 and then a third recess pattern 62 is formed by photolithography. By washing away with water the mixing prevention layer 56 which is exposed at the bottom of the third recess pattern 62, the first, the second, and the third recesses are caused to communicate with each other to form a head-heavy resist pattern 64.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a negative resist pattern for forming a gate electrode of a semiconductor device.

[0002]

2. Description of the Related Art In recent years, in gallium arsenide (GaAs) ICs and the like, miniaturization of the gate length has been advanced in order to increase the speed. However, there is a problem in that the resistance increases as the gate length decreases. In order to solve this, the literature: “A novelelectron bea
m exposure technique for
0.1 μm T-shaped gate fabric
Cation ”N.N. Samoto et al. , J.
Vac. Sci. Technol. B8 (6) No
v. / Dec. 1990. , Pp 1335 discloses a gate electrode having a T-shaped cross section taken along the gate length direction. FIG. 6 schematically shows this electrode structure in a perspective view. In this gate electrode structure, the gate length L is made short and the gate width M is made large, resulting in a T-shaped structure in which the lower layer portion of the gate electrode is narrow and the upper layer portion is enlarged. In addition to the T-shaped type, gate electrodes of this type include those called Γ (gamma) type and mushroom type.

As a method for forming this type of gate electrode, the above-mentioned document discloses the following method.

That is, as shown in FIG. 7, a lower molecular weight PMMA (polymethylmethacrylate) of the lower resist layer 12 is coated on the underlayer 10 to a thickness of 0.25 μm, and then the upper resist layer 14 is coated to a thickness of 1 μm. High molecular weight P
Coating with MMA ((A) of FIG. 7).

Next, by exposing the upper resist layer 14 with an electron beam in such an amount that the upper resist layer 14 alone is exposed, the groove 18 which defines the upper layer portion of the gate electrode is formed by developing (see (B in FIG. 7). )).

Next, the lower resist layer 12 is similarly exposed with an electron beam and then developed to form a groove 20 defining the lower layer portion of the gate electrode (FIG. 7C).

Finally, metal is deposited to fill the grooves 20 and 18 to form a metal layer 22 (FIG. 8A). After that, the upper resist layer 14 is lifted off.
And an unnecessary portion of the metal layer on it are peeled off, so that the desired gate pattern 24 (lower layer portion 24a and upper layer portion 24
It is indicated by b. ) Is obtained ((B) of FIG. 8).

In this way, the gate electrode 24 including the lower layer portion 24a for determining the gate length and the upper layer portion 24b having a length larger than the gate length of the lower layer portion is obtained.

[0009]

However, the above-mentioned electron beam exposure method has a problem that the apparatus is expensive and the productivity is low.

An object of the present invention is gallium arsenide (GaA).
s) A negative type for forming a gate electrode having a structure in which the upper layer portion is larger than the lower layer portion by using an inexpensive device for high speed in an IC or the like and by a method with high productivity It is to provide a method for forming a resist pattern.

[0011]

In order to achieve this object, according to the present invention, a gate electrode comprising a lower layer portion for determining the gate length and an upper layer portion having a length larger than the gate length of the lower layer portion. In forming a negative resist pattern for forming the lower resist layer, (a) a lower resist layer having a first groove pattern for defining the lower layer portion is formed on a semiconductor substrate by using a phase shifter method. Process,
(B) forming a mixing prevention layer having a second groove pattern communicating with the first groove pattern on the lower resist layer, and (c) forming the mixing prevention layer on the mixing prevention layer more than the first groove pattern. Forming an upper resist layer having a large length in the gate length direction, communicating with the second groove pattern, and having a third groove pattern for defining the upper layer portion in cooperation with the second groove pattern; And a step of performing.

Further, according to the present invention, a negative type resist pattern for forming a gate electrode composed of a lower layer portion for determining the gate length and an upper layer portion having a length larger than the gate length of the lower layer portion is formed. First, (a) a step of forming a lower resist layer having a first groove pattern for defining the lower layer portion on a semiconductor underlayer by using a phase shifter method, and (b) including the lower resist layer Forming a mixing prevention layer on the semiconductor underlayer so that the surface is flat; and (c) forming a groove bottom on the mixing prevention layer with a length larger than a length of the first groove pattern in the gate length direction. Forming an upper resist layer having a third groove pattern for defining at least a part of the upper layer portion, and (d) a portion of the mixing prevention layer exposed in the third groove pattern. To form a second groove pattern in the mixing prevention layer, and also remove a portion of the mixing prevention layer in the first groove pattern to form the gate with the first, second and third groove patterns. Forming a gate groove pattern for defining an electrode.

Further, according to the present invention, a negative resist pattern for forming a gate electrode composed of a lower layer portion for determining the gate length and an upper layer portion having a length larger than the gate length of the lower layer portion is formed. (A)
A step of forming an exposed portion and a non-exposed portion on the lower resist layer formed on the base substrate by using a phase shifter method, and (b) forming a mixing prevention layer on the exposed lower resist layer. (C) an upper resist layer having a third groove pattern on the anti-mixing layer, the groove bottom being larger than the length of the non-exposed portion in the gate length direction and defining at least a part of the upper layer. Forming process,
(D) removing the portion of the mixing prevention layer exposed in the third groove pattern to form a second groove pattern, and (e) the unexposed portion not exposed in the second groove pattern. May be removed to form a first groove pattern, thus forming a gate groove pattern for defining the gate electrode with the first, second and third groove patterns.

[0014]

According to the structure of the present invention, the negative resist is
A lower resist layer is formed, exposed using a phase shifter method, and then developed to form a first groove pattern defining a lower layer portion of the gate electrode. An intermediate layer is provided as a mixing prevention layer in order to prevent mixing with a negative resist applied in the next step before or after this development. A negative resist is again formed thereon as an upper layer, and this is exposed using a normal exposure mask, and then developed to form a third groove pattern defining the upper layer of the gate electrode. When the mixing prevention layer is provided before the development of the first groove pattern formation, the mixing prevention layer portion exposed in the third groove pattern is removed, and then the non-exposed portion of the lower resist layer is removed, A second groove pattern is formed.

Alternatively, when the mixing prevention layer is provided after the development for forming the first groove pattern, the second groove pattern is formed by removing the mixing prevention layer exposed in the third groove pattern. , Recover the first groove pattern. As a result, a negative resist pattern having a gate groove pattern which is formed by communicating the first, second and third groove patterns and defines a gate electrode is formed.

As described above, according to the present invention, two negative resist layers are formed, and the mixing prevention layers for both negative resist layers are provided between them. Then, the lower resist layer is formed into a fine groove pattern defining the lower layer portion of the gate electrode by a photolithography process using a phase shifter method,
The upper resist layer is subjected to a photolithography process using an ordinary exposure method to form a groove pattern defining an enormous upper layer portion of the gate electrode. Therefore, according to the method of the present invention, the throughput can be increased by using an inexpensive device.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the shapes, sizes, and arrangement relationships of the respective constituent components to the extent that the present invention can be understood. Further, the following examples are merely preferable examples, and therefore, numerical, material and other conditions described in this example are merely examples and are not limited to these exemplified conditions.

<Embodiment 1> FIG. 1 is a diagram for explaining a basic embodiment of a negative resist pattern forming method of the present invention. FIG. 1A shows a method obtained by the forming method of the present invention. FIG. 6 is a cross-sectional view of a resist pattern for forming a gate electrode, which is formed.

FIG. 1B is a cross-sectional view showing a gate electrode having an enormous head formed by using the resist pattern shown in FIG. 1A, for example, a T-type gate electrode.

First, a semiconductor substrate 50 is prepared as a base, and a negative resist layer is formed by coating on this one main surface. Next, this resist layer is exposed using a phase shifter method to form an exposed portion and a non-exposed portion. Then, the resist layer is developed to provide a first groove pattern 54 for defining a lower layer portion of the gate electrode in this resist layer to form a lower resist layer 52. In this case, the material of the resist layer may be any negative resist material. Further, the development for forming the first groove pattern 54 described above may be performed subsequent to the exposure of the negative resist layer, or may be performed in the final step of the step of forming the negative resist pattern of the present invention. Also good. It may be performed at a suitable stage according to the design.

Next, on the lower resist layer 52, a mixing prevention layer 5 for preventing the resist of the layer 52 and the resist of the upper resist layer formed in a later step from being mixed.
6 is provided. The mixing prevention layer 56 has a second groove pattern 58 communicating with the first groove pattern 54.
The length of the second groove pattern 58 in the gate length direction is set to the first length.
The groove pattern 54 has a length equal to or greater than the length. In order to form the mixing prevention layer 56, first, a suitable material for preventing mixing is applied to form a film (not shown) having a flat upper surface. If the first groove pattern 54 is already formed in the lower resist layer 52,
This film is formed so as to fill the groove pattern 54.
After that, after forming the upper resist layer on the upper side,
The second groove pattern 58 may be formed by using an appropriate etching process or peeling process.

Then, an upper resist layer 60 is formed on the mixing prevention layer 56. This upper resist layer 60
Has a third groove pattern 62 for defining an upper layer portion of the gate electrode. The length of the third groove pattern 62 along the gate length direction is made larger than the length of the first groove pattern 54. To form the upper resist layer 60, after forming a film of a mixing prevention material, a negative resist material is applied on the upper surface of this film to once form a resist layer. After that, in the resist layer, the upper portion of the first groove pattern is exposed to light over a range wider than the length of the first groove pattern along the gate length direction. Then, the resist layer is developed to form the third groove pattern 62.

After forming the third groove pattern 62, the groove 62 is formed.
The second groove pattern 58 is formed by etching away or peeling off the mixing prevention layer 56 exposed to the outside. After that, when the first groove pattern 54 is already formed and the mixing prevention material is embedded in the groove 54,
At the same time, the anti-mixing material is removed by the above etching removal or peeling to restore the first groove pattern 54. Alternatively, when the first groove pattern 54 remains in the unexposed state, the second groove pattern 58 is formed and then the first groove pattern 5 is formed by developing the unexposed portion.
4 is formed. Thus, finally (A) of FIG.
The negative resist pattern as shown in FIG.
Can be formed on.

The negative resist pattern 6 of FIG. 1A.
4 is vapor-deposited using an appropriate gate metal material according to the design, and then the upper resist layer 60 and the lower resist layer 52 are removed by a lift-off method to obtain the gate electrode 68. The gate electrode 68 has a lower layer portion 6
8a and the upper layer portion 68b (FIG. 1 (B)).

As described above, according to the present invention, a negative pattern having a required groove pattern is formed by two photolithography steps, one mixing prevention layer forming step, and this mixing prevention layer etching removal step. A resist pattern can be formed. Therefore, a negative resist pattern can be formed with good productivity using an inexpensive apparatus.

<Second Embodiment> Next, the second embodiment of the present invention will be described more specifically. 2A to 2D
And (A)-(C) of FIG. 3 are process drawings for explaining the second embodiment. Each drawing shows a cross section of the structure obtained in the main process step taken along the gate length direction.

First, a GaAs substrate 50 is used as a semiconductor base.
And prepare a wafer alignment mark (not shown).

Next, a first groove pattern 54 for defining the lower part of the gate electrode is formed on the lower resist layer 52 on the substrate 50 by the phase shifter method. For this reason,
The first resist layer 70 is coated to a thickness of about 0.3 μm. As the negative resist material for the first resist layer 70, for example, FSMR (FSMR is a trade name of Fuji Chemical Industry Co., Ltd.) is used. Next, this structure was baked on a hot plate at 70 ° C. for 140 seconds to obtain the structure shown in FIG.
A structure as shown in (A) is obtained.

Next, the baked first layer resist layer 70 is formed.
Substrate 50 having a stepper (reduction projection exposure apparatus) RA
101-VL (manufactured by Hitachi Ltd.). A retardation mask is used as an exposure mask used for this stepper. Particularly in this embodiment, it is preferable to form the light-shielding pattern, that is, the non-exposed portion (also referred to as the unexposed portion) on the first resist layer 70 by utilizing the edge of the shifter of the retardation mask. This is because according to this method, a fine light-shielding pattern can be obtained. Next, in this embodiment, after exposing the first resist layer 70 for 0.5 seconds, the FSM
The resist is developed with an R developing solution to remove the non-exposed portion. As a result, the first groove pattern 5 is formed on the first resist layer 70.
4 is formed, and the lower resist layer 52 is obtained. This first groove pattern 54 is also called a well. A structure having a lower resist layer 52 on a substrate 50 is shown in FIG.

Next, in order to form the mixing prevention layer 56 on the substrate 50 including the lower resist layer 52, PVA (polyvinyl alcohol) as a mixing prevention material is spin-coated to a thickness of about 0.05 μm (see FIG. 2). (C)). The surface of the mixing prevention layer 56 is made flat. The mixing prevention layer 56 can prevent the respective resists of the upper layer resist layer and the lower layer resist layer 52, which are formed in a later step, from being mixed with each other. At this point, the mixing prevention layer 56 is not peeled off.

Subsequently, a second resist layer 72 is formed on the mixing prevention layer 56. In this example,
In this case, the resist material is also FSMR described above, and is formed by spin coating with a layer thickness of about 0.5 μm. Then, the second resist layer 72 is heated to about 70 ° C.
And bake for about 140 seconds ((D) of FIG. 2).

Next, a third groove pattern 62 for defining at least a part of the upper layer portion of the gate electrode is formed in the second resist layer 72. Therefore, after mounting a phase difference mask or a mask provided with a normal light-shielding pattern on a stepper of the same type as the above stepper and exposing the second resist layer 72 for 0.5 seconds, the stepper is exposed to 110
Bake at a temperature of ℃ for about 140 seconds.

By this exposure, a non-exposed portion 74 and an exposed portion 76 are formed on the second resist layer 72. In this case, the length of the non-exposed portion 74 in the portion in contact with the mixing prevention layer 56 is made longer than the length of the first groove pattern 54 in the direction along the gate length direction, and the non-exposed portion 74 is also formed.
Is preferably exposed so as to completely cover the first groove pattern in the gate length direction. The state of the second resist layer 72 after this exposure is shown in FIG.

Then, for 40 seconds with FSMR developer,
The exposed second resist layer 72 is developed and further rinsed with pure water for 30 seconds to form a third groove pattern 62 ((B) of FIG. 3). This third groove pattern 62 is also called a well. The resist layer on which the third groove pattern 62 is formed in this way is referred to as an upper resist layer 60.

Next, the portion of the mixing prevention layer 56 exposed in the third groove pattern 62 is removed. In this embodiment, this removal is performed by peeling by washing with water. At this time, the upper resist layer 60 and the lower resist layer 5
A part of the mixing prevention layer 56 sandwiched between the first and second layers is also slightly removed in a lateral direction so as to bite under the upper resist layer 60, and further, the mixing in which the first groove pattern 54 is embedded. The blocking material is also removed. By this removal, the second groove pattern 58 is formed. In this way, the first, second and third groove patterns 54, 58 and 62 communicate with each other. Further, in this embodiment, the second groove pattern 58 also defines a part of the upper layer portion of the gate electrode. As described above, the gate groove pattern 80 is obtained. A negative resist pattern having the gate groove pattern 80 is shown by 82 ((C) of FIG. 3).

Finally, a metal vapor deposition device EVC-1501
A structure having a negative resist pattern 80 is set on a semiconductor underlayer 50 in (manufactured by Nichiden Anelva Co.), and aluminum (Al) is set to a thickness of about 6000 A ° (angstrom) on a plane by, for example, an electron beam evaporation method. Vapor deposition so that Next, the structure body on which the vapor deposition layer (not shown) is formed is immersed in, for example, a dimethylformamide solution for about 10 minutes, and then the gate electrode pattern 68 is formed by lift-off ((D) of FIG. 3). The lower layer portion of the gate electrode 68 is indicated by 68a, and the upper layer portion thereof is indicated by 68b. In this way, by using the negative resist pattern formed according to the present invention, it is possible to form the gate electrode whose head is larger than that of the lower portion when seen in a sectional view along the gate length direction. In addition, when the metal is vapor-deposited, it does not enter even a slight biting portion on both sides of the second groove.

<Third Embodiment> Next, a third embodiment of the present invention will be described. 4 and 5 are views for explaining a negative resist pattern forming process for forming a T-shaped gate electrode, similarly to the second embodiment. Each figure is shown in Figure 2.
As in FIG. 3 and FIG. 3, it is represented by a cross section cut along the gate length direction.

In the figure, the same components as those shown in FIGS. 2 and 3 are designated by the same reference numerals.

First, in the same manner as in the step of FIG.
After the wafer alignment mark (not shown) is formed on the substrate 50, the first resist layer 7 is formed on the substrate 50.
Form 0. This layer 70 is formed by coating FSMR (manufactured by Fuji Chemical Industry Co., Ltd.) to a thickness of 0.3 μm and baking it on a hot plate at 70 ° C. for 140 seconds ((A) of FIG. 4).

Then, the substrate 50 having the first resist layer 70 is set on the stepper RA101-VLII (manufactured by Hitachi, Ltd.) in the same manner as in the step of FIG. 2B described above.
Exposure is performed by the phase shifter method. Also in this case, the phase difference mask is used. The exposure in this case is performed for about 0.5 seconds, and the exposed portion 52a and the unexposed portion 52 are formed on the first resist layer 70.
b is formed ((B) of FIG. 4). In this exposure, the pattern of the unexposed portion is preferably formed by using the edge of the shifter of the retardation mask. By doing so, a light shielding pattern having a fine length in the gate length direction can be formed.

Next, in order to prevent mixing with the FSMR which is the resist material of the second resist layer which is applied to the underlayer 50 in the next step, PVA is used as an anti-mixing material.
(Polyvinyl alcohol) is spin-coated on the first resist layer 70 to a thickness of about 0.05 μm, and the mixing prevention layer 5 is formed.
6 is formed ((C) of FIG. 4).

Then, an upper resist layer 60 having a third groove pattern 62 is formed on the mixing prevention layer 56 (FIG. 5B). Therefore, in this embodiment, first, FSMR as a negative resist material is applied by spin coating to a film thickness of about 0.5 μm to form the second resist layer 72 ((D) of FIG. 4). Subsequently, after baking the second resist layer 72 at about 70 ° C. for about 140 seconds, the second resist layer 72 is baked on the second resist layer 72 as shown in FIG.
Exposure is performed by the same method as described in 1. In this way, a structure as shown in FIG. 5A is obtained. In the figure, 76 is an exposed portion, and 74 is a non-exposed portion (also referred to as an unexposed portion). In this case, the unexposed portion 74
The length of the portion of the first resist layer 52 in contact with the mixing prevention layer 56 in the direction along the gate length direction is the unexposed portion 52 of the first resist layer 52.
It is preferable to form the unexposed portion 52b so as to be longer than the length b and completely cover the unexposed portion 52b in the gate length direction. FIG. 5A shows such a state.

Subsequently, the second resist layer 72 is developed with the FSMR developer for 40 seconds in the same manner as described with reference to FIG. 3B, and further rinsed with pure water for 30 seconds to form the third groove pattern. 62 (also called well) is formed (FIG. 5)
(B)). Thus, the upper resist layer 60 having the resist groove pattern defining at least a part of the upper portion of the gate electrode is obtained.

Next, the mixing prevention layer 56 exposed in the third groove pattern 62 is removed by washing with water to form a second groove pattern 58. Similar to the second embodiment, the second groove pattern 58 is formed so as to slightly extend in the lateral direction to the lower side of the upper resist layer 60. Following this, the unexposed portion 52 of the lower resist layer 52
b is removed by FSMR developer to remove the first groove pattern 5
4 is formed. As a result, a negative resist pattern 82 having a gate groove pattern 80 in which the first, second and third groove patterns 54, 58 and 62 communicate with each other is obtained (FIG. 5).
(C)).

Also in this embodiment, the second groove pattern 58 defines a part of the upper layer portion of the gate electrode. Also, the first groove pattern 54 defines a lower layer portion of the gate electrode.

Finally, aluminum (Al) is vapor-deposited on the plane to a thickness of 6000 A ° (angstrom) by the electron beam vapor deposition method similar to that described in the second embodiment. Next, the resist layers 60 and 52, which are the bases of the vapor-deposited layer, are immersed in a dimethylformamide solution for about 10 minutes and then lifted off to form the lower layer portion 68a and the upper layer portion 68.
A gate pattern 68 of b is formed ((D) of FIG. 5).

It is obvious that the present invention is not limited to the above-mentioned embodiments but many modifications and changes can be made. For example, in the above-mentioned embodiments, the method of forming the negative resist pattern for forming the gate electrode having a T-shaped cross section has been described. The present invention can be applied to any resist pattern. In addition, numerical conditions, materials, and other conditions can be appropriately modified according to the design.

Further, in the above-mentioned embodiment, the phase shifter method using the mask including the edge is explained, but it is obvious that other phase shifter method may be used depending on the design.

[0049]

As is apparent from the above description, according to the method of forming a negative resist pattern of the present invention,
By applying the resist twice, by photolithography by the exposure method twice, by forming the mixing prevention layer once, and by removing it, it is possible to use a negative type resist pattern having a required groove pattern using an apparatus which is cheaper than the conventional one. Becomes possible,
Moreover, productivity is also improved. Therefore, according to the present invention,
A T-shaped gate electrode having a gate length of 0.2 μm or less can be easily formed by a simple process.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a basic first embodiment of a method for forming a negative resist pattern according to the present invention.

FIG. 2 is a process chart of the first half used for describing a second embodiment of the method for forming a negative resist pattern of the present invention.

FIG. 3 is a process diagram that follows FIG.

FIG. 4 is a process chart of the first half used for describing a third embodiment of the method for forming a negative resist pattern of the present invention.

5 is a process chart that follows FIG. 4. FIG.

FIG. 6 is an explanatory diagram of the present invention and a conventional gate electrode.

FIG. 7 is a first half process diagram for explaining a conventional method of forming a resist turn for forming a gate electrode.

8 is a process chart that follows FIG. 7. FIG.

[Explanation of symbols]

 10: Underlayer (substrate) 12: Lower resist layer 14: Upper resist layer 18: Upper groove 20: Lower groove 22: Evaporated metal 24: Gate electrode 24a: Lower gate electrode 24b: Upper gate electrode 50: Semiconductor substrate 52: Lower resist layer 54: First groove pattern 56: Mixing prevention layer 58: Second groove pattern 60: Upper resist layer 62: Third groove pattern 64: Negative resist pattern 68: Gate electrode 68a: Lower gate electrode 68b: Gate electrode Upper part 70: First resist layer 72: Second resist layer 74: Non-exposed part 76: Exposed part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/027 7352-4M H01L 21/30 311 W 7352-4M 361 U

Claims (3)

[Claims] 1. A negative type resist pattern for forming a gate electrode comprising a lower layer portion for determining a gate length and an upper layer portion having a length larger than the gate length of the lower layer portion, wherein Forming a lower resist layer having a first groove pattern for defining the lower layer portion on the lower ground by using a phase shifter method; and (b) forming the first groove pattern on the lower resist layer. Forming a mixing prevention layer having a communicating second groove pattern, and (c) forming a second groove pattern on the mixing prevention layer having a length in the gate length direction larger than that of the first groove pattern. And a step of forming an upper resist layer having a third groove pattern for defining the upper layer portion in combination with the second groove pattern, the negative resist pattern. Forming method. 2. A negative type resist pattern for forming a gate electrode comprising a lower layer portion for determining a gate length and an upper layer portion having a length larger than the gate length of the lower layer portion. Forming a lower resist layer having a first groove pattern for defining the lower layer portion on the lower ground by using a phase shifter method, and (b) on the semiconductor underlayer including the lower resist layer, A step of forming an anti-mixing layer so that the surface becomes flat, and (c) a groove bottom portion on the anti-mixing layer is larger than a length of the first groove pattern in the gate length direction, and at least the upper layer portion is formed. Forming an upper resist layer having a third groove pattern for defining a part, and (d) removing the portion of the mixing prevention layer exposed in the third groove pattern to remove the mixture. To form a second groove pattern in grayed prevention layer, wherein also part of the mixing-preventing layer is removed in the first groove pattern in the first, second
And a step of forming a gate groove pattern for defining the gate electrode with a third groove pattern, the method of forming a negative resist pattern. 3. A negative resist pattern for forming a gate electrode comprising a lower layer portion for determining a gate length and an upper layer portion having a length larger than the gate length of the lower layer portion, wherein (a) a base Using a phase shifter method for the lower resist layer formed on the substrate to form an exposed portion and a non-exposed portion, and (b) a step of forming a mixing prevention layer on the exposed lower resist layer. (C) An upper resist layer having a third groove pattern for defining at least a part of the upper layer portion having a groove bottom portion larger than the length of the non-exposed portion in the gate length direction is formed on the mixing prevention layer. And (d) removing a portion of the mixing prevention layer exposed in the third groove pattern to form a second groove pattern, and (e) not exposing in the second groove pattern. The above Removing the exposed portion to form a first groove pattern, and thus forming a gate groove pattern for defining the gate electrode with first, second and third groove patterns. Method for forming negative resist pattern.