JPH0529934B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for diagnosing control words in a microprogram-controlled data processing device.

(b) Technical background When a microprogram-controlled data processing device has an error correction code logic mechanism for control words, it is common to use a control word modified by the error correction code logic mechanism described above. In cases where the next microaddress is determined by the instruction itself, there is a problem in that the arithmetic cycle associated with the control storage cannot be sped up due to the logic delay required for error correction.

One solution to this problem is to execute maintenance commands at regular intervals from a preventive maintenance perspective, and if an error occurs, correct the control word at that point, so that the error can be avoided during the actual execution of the command. Since it can reduce the probability of detection, its implementation has been desired.

(c) Prior art and problems In a data processing device that writes a control word corrected by error correction code logic (hereinafter referred to as ECC) into a control storage unit, the control word is normally checked by ECC. A control word that has not been corrected by ECC is used for the arithmetic unit, and if a 1-bit error occurs, the instruction is interrupted, the control word where the error occurred is rewritten, and the instruction is retried again. I had adopted a method of doing so. However, with this method, not all commands can be retried, which poses a problem that seriously affects the system.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention has been proposed in the sense of preventive maintenance, for example, by reading out the control words from the control storage section at regular intervals, correcting and rewriting any errors that occur, and The purpose of this invention is to provide a method for reducing errors that occur during the execution of instructions.

(e) Configuration of the invention A control storage unit storing a microprogram;
It has an address register that addresses the control storage section, a data register that holds the control word read from the control storage section, and an error correction code logic mechanism that inputs the contents of the data register and detects and corrects errors. However, normally, data processing is performed using the control word read from the control storage unit without going through the error correction code logic mechanism, and error detection and correction processing is performed in parallel by the error correction code logic mechanism. and when an error is detected, writing the corrected control word into the control storage unit and correcting it,
In the microprogram control device that retries using the corrected control word, at least:
A counter capable of adding or subtracting a fixed number; connecting means for transferring the output of the counter to the address register; and means for detecting that a specific control word has been read from the control storage section to the data register. The control memory section is accessed and the specific control word is read out by a specific command generated at a constant cycle, and when it is detected that the specific control word has been read out, the program After putting the control device into a diagnostic state, the control word at the address indicated by the value added or subtracted from the counter is read out, and when an error is detected in the read control word, the error is corrected by the error correction logic mechanism. For example, if a specific control word is read and checked at regular time intervals and an error occurs, the Since it can be corrected at any point in time, it has the effect of reducing errors that occur during actual instruction execution.

(f) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings.
The figure is a block diagram showing one embodiment of the present invention.

In the drawing, 1 is a control memory (CS) consisting of random access memory, 2 is an address register (AR), 3 is a read register (RR),
31 is a flag bit that specifies a specific control word, 4 is a write register (WR), 5 is an error correction code logic mechanism (ECC) using an error correction code, and 6 is counted up in a micro operation cycle and specified by a specific means. 7 is a control circuit for a counter (CONT) whose initial value can be set or whose output can be blocked.

First, for example, a special diagnostic command is generated at regular time intervals (for example, the time interval of an interval timer), and the operating part of the command is set in the address register (AR) 2 and stored in the control memory (CS).
1 is accessed, a specific control word is read into the read register (RR) 3, and when a flag 31 indicating the specific control word is detected, the control circuit 7 is activated for diagnosis. At this time, if the control circuit 7 is stopped, it accepts this activation and starts the diagnostic operation, but if it is already in operation, the activation is invalidated.

When the control circuit 7 accepts the start-up, the control circuit 7 sets the state of the data processing device to a diagnostic state and invalidates the interface signal generated by the microprogram to other devices (or units).

The control circuit 7 is a counter (CONT) 6.
+1 and save that value to the address register (AR).
2, the control memory (CS) 1 is accessed, and the control word read out to the read register (RR) 3 is checked in the error correction code logic (ECC) 5.

At this time, if there is no error, the control circuit 7 sets all "0" in the address register (AR) 2, reads out the control word (non-operation instruction) at address 0, and
After putting the data processing device in a waiting state, the diagnostic state is canceled, a diagnostic end signal is sent to an instruction control unit (not shown), and the next instruction is requested.

If an error is detected, the error correction code logic (ECC) 5 corrects the control word,
Set the corrected data in write register (WR) 4 and rewrite it in control memory (CS) 1. Then, set all “0” in address register (AR) 2 and write the control word at address 0. reading,
After canceling the diagnostic state, the command control unit (not shown) sends a diagnostic end signal and a system automatic recovery signal (a hardware fault has occurred, but the software automatically recovers the fault. send out a signal to inform the public.

When the instruction control unit receives the above system automatic recovery signal, it moves to interrupt processing.
It operates to identify that a hardware failure has occurred but has been automatically restored and to proceed to the original process.

The above operation is repeated, for example, at every fixed time interval of the interval timer, and each time the counter (CONT) 6 is incremented by 1, so that all control words are read out and checked within a specific time, If an error occurs, the operation of correcting it at that point is continued at all times, and a sufficient preventive maintenance effect can be obtained.

Since it operates as described above, the specific control word is read out in the same control process as a normal instruction, such as "detection of a specific control word by the maintenance instruction control storage access control word reading decoder." , the control memory can be checked.

The automatic error correction mechanism by ECC is limited to 1-bit errors and cannot correct 2-bit errors, but the probability of this case occurring is extremely low, so realistically it can be ignored. For example, the problem can be solved by duplicating the control memories and switching them, so this does not become a factor that hinders the implementation of the present invention.

In the above embodiment, an example was explained in which a special diagnostic command is generated at fixed time intervals using an interval timer, but considering the basic configuration of the present invention, the present invention is not limited to this. It goes without saying that a specific control word can be read by, for example, generating the above-mentioned special maintenance command from software. In this case, the maintenance command can forcibly check the control storage. In particular, even if the control memory or a specific area thereof is busy for a long time, the software can detect this and issue the special maintenance command to check the control memory. , the effect is great.

(g) Effects of the invention As explained in detail above, according to the present invention,
For example, control memory (CS) is diagnosed at regular intervals, and if an error occurs, the contents of the control memory are corrected at that point, so actual commands (but not maintenance commands) This has the effect of reducing the probability that an error will occur in the control memory during the execution stage, and improving the reliability of the data processing device.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. In the figure, 1 is a control memory (CS), 2 is an address register (AR), 3 is a read register (RR), 31 is a flag bit, 4 is a write register (WR), 5 is an error correction code logic (ECC), 6 represents a counter (CONT), and 7 represents a control circuit.

Claims (1)

[Claims] 1. A control storage section that stores a microprogram, an address register that addresses the control storage section, a data register that holds a control word read from the control storage section, and a control storage section that stores a microprogram. It has an error correction code logic mechanism that inputs contents and detects and corrects errors, and normally performs data processing using control words read from the control storage unit without going through the error correction code logic mechanism. At the same time, an error correction code logic mechanism performs error detection and correction processing in parallel, and when an error is detected, the corrected control word is written into the control storage section and corrected, and the corrected control word is used to correct the error. A microprogram control device for retrying includes at least a counter capable of adding or subtracting a fixed number, a connection means for transferring the output of the counter to the address register, and a specific control word that transfers the data from the control storage section to the address register. A means for detecting that the specific control word has been read out is provided, and the control storage section is accessed and the specific control word is read out by a specific command generated at a constant cycle, and the specific control word is read out. When it is detected that the program control device has been read out, the program controller is placed in a diagnostic state, and the control word at the address indicated by the value added or subtracted from the above counter is read out, and an error is detected in the read control word. When the error is detected, the error is corrected by the error correction logic mechanism and the control storage section is rewritten.