JPH05297817A - Display control circuit device for flat panel display device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a display control circuit device of a flat panel display device in which current consumption is significantly reduced. [Configuration] NAND circuits 171, FF 173, FF for inputting a write command signal or the like from a control bus 131
The write command detection circuit 17 configured by 175, when the polarity of the frame signal 8 is switched when there is no write command,
Clock pulse train control signal 1 that switches from High to Low
6 is sent to the switching circuit device 18. Circuit device 1
Reference numeral 8 denotes an opening / closing operation according to Low / High of the control signal 16, which opens when receiving the control signal 16 of Low level, and the driver control circuit 2 of the clock pulse train 4
Cut off transmission to 17. As a result, the circuit 217 and the shift register 211 stop the operation according to the clock pulse train 4. At this time, the SEG driver 21 outputs the LCD drive voltage 7 based on the horizontal scanning signal pulse train 5 by using the individual display data already stored in the internal memory 216.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control circuit device for a flat panel display device such as an LCD display panel.

[0002]

2. Description of the Related Art In recent years, flat panel display devices such as LCD display panels have been widely used in office automation equipment and the like. As an example of a conventional display control circuit device used in this type of flat panel display device, an example in which an LCD display panel (hereinafter abbreviated as LCD panel) is used in the flat panel display device is shown in FIGS.
Shown in. FIG. 4 is a circuit configuration diagram of the display control circuit device of the LCD panel, and FIG. 5 is a circuit configuration diagram of the segment driver (hereinafter abbreviated as SEG driver) in FIG.

In FIGS. 4 and 5, reference numeral 1 is a rectangular LCD in which display elements are arranged in a plurality of columns and rows, respectively.
It is a panel, and here is 640 columns and 480 rows for a total of 30
It is assumed that 7,200 LCD elements as display elements are arranged. Reference numeral 21 denotes an SEG driver in which four are arranged in parallel on the upper side with respect to the row direction of the LCD panel 1 and four are arranged in parallel on the lower side to display on the LCD element. LCD for each SEG driver
With respect to the LCD elements provided on the panel 1, 640/4 = 160 elements in the row direction and 4 in the column direction.
80/2 = 240 elements in total for 38,400 elements.

The SEG driver 21 inputs an 8-bit display data signal 3 for displaying an LCD element from a graphic controller, which will be described later, in synchronization with a clock pulse train 4 to perform serial / parallel conversion, and then the LCD.
The individual display data for 38,400 elements of the elements are temporarily stored, and a pulse is output for each clock pulse train 4 of the number of pulses corresponding to the display element group for one row from a graphic controller described later. Horizontal scanning line signal pulse train 5 [in this example, 20 clock pulses by the clock pulse train 4 x 4 (S arranged in parallel)
Number of EG drivers 21) = 80 pulses, one horizontal scanning line signal pulse is output]
A serial / parallel shift register (hereinafter abbreviated as shift register) 211 for outputting the temporarily stored individual display data after parallel conversion to an internal memory described later.
And the individual display data for 160 LCD elements from the shift register 211 are sequentially received, and 160 × 240 = 38,400 LC which is handled by one SEG driver 21.
An internal memory 216 including a RAM for storing individual display data for D elements, and 160 LCD elements in a level shifter circuit described below for sequentially extracting individual display data for 160 LCD elements from the internal memory 216 in accordance with the horizontal scanning line signal pulse train 5. Latch circuit 212 for transferring as the minute individual display data signal 6, and the above-mentioned 160V LCD element individual display data signal 6 which is the 0V / 5V signal output from this latch circuit 212 is required to drive the LCD element -20V / 5V The number of pulses of the clock pulse train 4 corresponding to the display element group for one screen from the graphic controller which will be described later (in this example, 20 clock pulses by the clock pulse train 4 × 4 × 480 (the number of display elements arranged in the row direction) =
38,400 pulses], the level shifter circuit 213 receives the frame signal 8 whose polarity is inverted, and inverts the polarity of the -20V / 5V voltage output every time the polarity of the frame signal 8 is inverted. And a pre-drive circuit 214 which further adjusts the output voltage to output the output of the level shifter circuit 213 so that the LCD element can be displayed in a desired display shade, and the output of the pre-drive circuit 214 is supplied with the LCD element of the LCD element. A drive circuit 215 that imparts a high withstand voltage required for direct driving and converts it into an LCD element drive voltage 7, and the clock pulse train 4.
And the horizontal scanning line signal pulse train 5 and a graphic controller described later (in the case of the first stage SEG driver)
Alternatively, when a control signal (not shown) is received from the SEG driver of the previous stage (in the case of SEG drivers of the second stage and thereafter), the clock pulse train 4 is sent to the shift register 211, and the number of the clock pulses 4 sent is this example. When the number of pulses reaches 20, the sending of the clock train pulse 4 to the shift register 211 is temporarily stopped and a control signal is sent to the SEG driver of the next stage, and when the pulse of the horizontal scanning line signal pulse train 5 is received, the control returns to the original operation. The driver control circuit 217 for performing

Reference numeral 9 receives a horizontal scanning line signal pulse train 5 and a frame signal 8 and outputs L from the SEG driver 21.
It is a common driver (hereinafter referred to as COM driver) for switching the CD element drive voltage 7 row by row so as to sequentially apply to the 640 LCD element groups arranged in each row of the LCD panel 1. In the case of this example, , The LCD panel 1
2 are arrayed in the column direction, and one COM
The driver 9 is in charge of switching 240 rows of LCD element columns. Reference numeral 10 denotes a memory device (hereinafter abbreviated as VRAM) for storing display data to be displayed by each LCD element of the LCD panel 1. A reference numeral 11 retrieves display data stored in the VRAM 10 from the VRAM 10 and sends it to the SEG driver 21 as an 8-bit display data signal 3 in accordance with a read command from a microprocessor (hereinafter abbreviated as CPU) described later. The clock pulse train 4, the control signal (not shown) to the SEG driver 21, and the horizontal scanning line signal pulse train 5 and the frame signal 8 to the SEG driver 21 and C.
Graphic with a function to send to OM driver 9
It is an LCD controller as a controller.

Reference numeral 12 denotes a storage means for storing display data based on an input from an input device (not shown) such as a keyboard in the VRAM 10 in accordance with a write command from the CPU, which will be described later. Multiplex circuit 121, memory control circuit 12
2, a memory controller having a bidirectional switching circuit 123 and a decoder 124. Reference numeral 13 is a CPU, which is a control bus 131 for transmitting its command signal, an address bus 132 for transmitting an address signal relating to display data,
It is connected to a data bus 133 for transmitting a display data signal, and the display data is transmitted by these buses 132 and 133, and at the same time, via the control bus 131,
The LCD controller 11 outputs a read command for performing the above-mentioned various operations, and outputs a write command for causing the memory controller 12 to perform the above-mentioned display data storage operation. Reference numeral 14 is a clock oscillator such as a crystal oscillator that supplies the LCD controller 11 and the like with a clock frequency that is the basis of the clock pulse.

Since the circuit configuration of the display control circuit device of the LCD panel according to the prior art is the above-mentioned configuration, CP
First, the display data is VR by the read command from U13.
The 8-bit display data signal 3 based on the display data is extracted from the AM 10 and is supplied from the graphic controller 11 together with the clock pulse train 4, the horizontal scanning line signal pulse train 5, the frame signal 8 or the control signal. It is sent to the SEG driver 21. Each SEG driver 21 receives these signals and pulse trains, and the driver control circuit 2
The clock pulse train 4 is sent from 17 to the shift register 211, the 8-bit display data signal 3 is converted into parallel data by the shift register 211 at every cycle based on this clock pulse train, and the individual display data converted into parallel data is horizontally scanned. Each time the pulse of the line signal pulse train 5 is received, it is stored in the internal memory 216, and the latch circuit 212
Every time the pulse of the horizontal scanning line signal pulse train 5 is received, the individual display data stored in the internal memory 216 is transferred to the level shifter circuit 213 as the individual display data signal 6 for 160 LCD elements, and thereafter, the pre-drive circuit 214 and the drive circuit. After passing 215, the LCD element drive voltage 7 is simultaneously output to the LCD elements for one row of the display panel 1 from the four SEG drivers 21 arranged in parallel. As a result, the LCD elements for one row perform the display operation.

For the COM driver 9, the horizontal scanning line signal pulse train 5 is sent from the graphic controller 11.
And the frame signal 8 is transmitted. The COM driver 9
Each time the pulse of the horizontal scanning line signal pulse train 5 is received, the row-by-row switching is performed so that the LCD element drive voltage 7 is sequentially applied to the LCD element group arranged in each row of the LCD panel 1. Thus, in the case of this example, 480
By receiving the pulses for the horizontal scanning line signals, the LCD
The display of all LCD elements for one screen arranged on the display panel 1 is completed. After that, each time the frame signal 8 is received, the above-described operation is repeated to continue the display operation on the LCD display panel 1.

In the display control circuit device of the above-described conventional flat panel display device, the flat panel display device is L
Although the case of the CD panel has been described, the same applies to the case where the flat panel display device uses the principle of ELD (electroluminescence) or PD (plasma display). However, in the flat panel display device using the ELD or PD, the polarity of the frame signal 8 does not need to be inverted for each pulse number of the clock pulse train corresponding to the display element group for one screen, and the frame signal 8 is for one screen. It is sufficient that a pulse is output for each pulse number of the clock pulse train corresponding to the display element group.

[0010]

In the display control circuit device of the flat panel display device according to the above-mentioned prior art, the display operation is performed in a predetermined manner. However, the repeated display operation of the flat panel display device is performed. As the speed becomes higher, that is, as the pulse period of the clock pulse train becomes shorter, the consumption current becomes larger, which is becoming a problem. In the display control circuit device of the flat panel display device according to the conventional technology, the consumption current value of the SEG driver occupies a large proportion of the consumption current value, and particularly the consumption of the shift register and the control circuit in the SEG driver. It is an electric current.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a display control circuit device of a flat panel display device capable of significantly reducing a current consumption value. is there.

[0012]

The above-mentioned objects of the present invention are as follows: 1) a plurality of segment drivers, a common driver,
A display control circuit for controlling display of a rectangular flat panel display device, comprising a memory device, a graphic controller, and a microprocessor, wherein display elements are arranged in a plurality of columns and a plurality of rows, respectively. Each of the segment drivers has an internal memory, and among the display data to be displayed by the display element, the individual display data to be displayed by the display element, which each segment driver is responsible for its display control, is stored in the segment driver. While storing in the memory, the display element drive output based on the individual display data stored in the internal memory is output for each of the display element groups arranged in the row direction, the common driver, Drive output for switching the drive to the display element groups arranged in different rows arranged in different rows To output the result, the memory device is for storing the display data, each of the display element is displayed, the graphic controller in accordance with a read command from the micro plot Princesa
A display data signal corresponding to the display data stored in the memory device, a clock pulse train that determines a timing for sequentially switching the display data signal, and each clock pulse train having a pulse number corresponding to the display element group for one row The horizontal scanning line signal pulse train output to the segment driver and the horizontal scanning line signal pulse train to the common driver. The microprocessor includes a control bus, an address bus and a data bus. And a write command for transmitting the display data through the address bus and the data bus and storing the display data in the memory device through the control bus, and the segment for the graphic controller. Driver and the above The display data signal to down driver,
In a display control circuit device of a flat panel display device for giving a read command for sending out the horizontal scanning line signal pulse train, a write command detection means and a clock pulse train cutoff means are additionally provided, and the write command detection means is A clock pulse train control signal for switching the operation of the clock pulse train cutoff means to the clock pulse train cutoff means in accordance with the presence or absence of the write command from the microprocessor. According to the output of the clock pulse train control signal from the detection means, the transmission of the clock pulse train to the segment driver is allowed or blocked, and 2) in the means described in 1 above, the clock pulse train cutoff means comprises: It is a switching circuit device and writes Only the command pulse detecting means outputs a clock pulse train control signal to close or open the circuit to allow or block the transmission of the clock pulse train to the segment driver. 3) In the means described in 1 above. The segment driver has a built-in clock pulse train cutoff means, which is a switching circuit device, and stores the display data stored in the memory device as individual display data in the internal memory in accordance with the clock pulse train control signal from the write command detection means. In addition to executing or stopping the operation, the display element drive output based on the individual display data stored in the internal memory is output for each display element group arranged in the row direction. 4) In the means described in the above items 1 to 3, the write command detecting means is A NAND that receives a write command from the microprocessor at one input side thereof, receives an address signal from the microprocessor at the other input side, and outputs a signal corresponding to the clock pulse train control signal from the output side to the segment driver. This is achieved by having a circuit.

[0013]

In the present invention, the CPU is provided on one of the input sides.
Receives the write command from the other side and sends CP to the other input side.
N which receives an address signal from U and outputs a driver control signal corresponding to a clock pulse train from its output side
A write command detecting means having an AND circuit for sending a clock pulse train control signal to the clock pulse train breaking means for switching the operation of the clock pulse train breaking means according to the presence or absence of a write command from the CPU, and the write command detecting means. A clock pulse train blocking means for permitting or blocking the transmission of the clock pulse train to the segment driver according to the clock pulse train control signal output;
Alternatively, the write command detection means and the clock pulse train cutoff means that is a switching circuit device are built in, and the display data stored in the memory device is stored in the internal memory according to the clock pulse train control signal from the write command detection means. SE for executing or stopping the operation of storing the individual display data in the memory and outputting a drive output for each of the display element groups arranged in the row direction based on the individual display data stored in the internal memory
The SEG driver is provided with a G driver, and in the case of a signal indicating that there is a write command in response to the clock pulse train control signal from the write command detection means, these SEG drivers send the clock pulse train to the SEG driver as in the prior art. From the driver control circuit to the shift register,
The display data in the memory device that has been newly written is stored in the internal memory as individual display data, and the drive output based on the display data that has been newly written is stored in the horizontal scanning line signal pulse train. Each pulse is output to the display element group. When the driver control signal output is a signal indicating that there is no write command, the reception of the clock pulse train is stopped, and the shift register inputs the display data signal in synchronization with the clock pulse train to perform serial / parallel conversion. The above operation is not performed, and the drive output based on the individual display data already stored in the internal memory is output to the display element group for each pulse of the horizontal scanning line signal pulse train.

As a result, in the case where the same screen is continuously displayed on the flat panel display device, which is a case often occurring in the case of a device such as a word processor that displays a still screen, the screen display Since the display data for display is not changed, the driver control signal output is a signal without a write command.
The transmission of the EG driver to the driver control circuit is stopped, and the operation of the driver control circuit according to the clock pulse train is stopped. Along with this, the clock pulse train is no longer transmitted to the shift register, and the operation of converting the display data signal into parallel data, which is performed for each pulse of the clock pulse train of the shift register, is also stopped.

In this case, the SEG driver operates by the horizontal scanning line signal pulse train having a period significantly longer than the period of the clock pulse train as described above, and latches each time the pulse of the horizontal scanning line signal pulse train is received. The individual display data after parallel conversion already stored in the internal memory in the circuit is transferred to the level shifter circuit, and thereafter,
The LCD element drive voltage is simultaneously output to the LCD elements of the display panel from the plurality of SEG drivers arranged in parallel through the pre-drive circuit and the drive circuit. As a result, the current consumption of the SEG driver can be significantly reduced.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. Embodiment 1; FIG. 1A shows a switching circuit device as a clock pulse train interruption means in FIG.
The circuit configuration diagram shown together with the EG driver, FIG.
2, a circuit configuration diagram of the write command detection circuit in FIG.
FIG. 6 is a circuit configuration diagram of a display control circuit device of an LCD panel according to an embodiment corresponding to claims 1, 2, and 4 of the present invention. The same parts as those of the display control circuit device of the display device of the LCD panel according to the conventional example of FIGS.
The description is omitted. In FIG. 1 and FIG. 2, reference numeral 18 denotes a switching circuit device as a clock pulse interruption device, which inputs a clock pulse train control signal 16 from a write command detecting means described later, and this clock pulse train control signal 16 has a write command. If the signal is a high level signal, the circuit is closed, and the clock pulse train 4 is passed through to be input to the driver control circuit 217 of the SEG driver 21.
When it is an ow level signal, the circuit is opened, and the driver control circuit 217 of the clock pulse train 4 is opened.
It cuts off the transmission to.

Reference numeral 17 denotes a write command detecting circuit as a write command detecting means. First, the NAND circuit 171 receives a write command from the CPU 13 on one input side thereof via the control bus 131 and inputs the other. The address signal from the CPU on the side of the address bus 1
A signal 172 which is received via 32 and has a High level only when there is a write command and an address signal is present, and which has a Low level when either the write command or the address signal or both signals are absent is output. This signal 172 is supplied to the first flip-flop circuit (hereinafter abbreviated as FF) 173 at the next stage. FF
The signal 172 receives the signal 172 and the frame signal 8, and when the signal 172 switches from the Low level to the High level, the signal 172 immediately switches to the High level and the signal 1
When 72 switches to the Low level, a signal 174 for switching from the High level to the Low level is output at the timing when the polarity of the frame signal 8 switches.
The signal 174 is further provided to the second flip-flop circuit (hereinafter abbreviated as FF) 175 at the next stage.
The FF 175 switches from the Low level to the High level at the timing when the signal 174 switches from the High level to the Low level, until the polarity of the frame signal 8 switches to the original polarity (in the case of this embodiment,
A high level state is maintained (while two screens are displayed on the LCD panel 1), and a driver control signal output 16 that switches from a high level to a low level is output at the timing when the polarity of the frame signal 8 switches to the original polarity.

In this embodiment, since the above-mentioned configuration is adopted, the CP
When there is a write command from U13, the write command detection circuit 17 outputs the Hig as the driver control signal output 16.
When the h level signal is output and the switching circuit device 18 receives this high level signal, the switching circuit device 18 inputs the clock pulse train 4 to the driver control circuit 217. Therefore, the SEG driver 21 operates in the same manner as in the conventional example. Take action. When there is no write command from the CPU 13, the write command detection circuit 17 outputs a low level signal as the driver control signal output 16, and when the switching circuit device 18 receives this low level signal, the switching circuit device 18 opens. , The input of the clock pulse train 4 to the driver control circuit 217 is cut off.

In this case, since the clock pulse train 4 is not input to the driver control circuit 217, the driver control circuit 217 does not output the clock pulse train 4 to the shift register 211. Therefore, since the clock pulse train 4 is not input, the shift register 211 does not perform the operation of converting the 8-bit display data signal 3 for each pulse of the clock pulse train 4 into parallel data. The SEG driver 21 sets the individual display data already stored in the internal memory 216 to 160 for each pulse of the horizontal scanning line signal pulse train 5 as in the case of the conventional example.
The individual display data signal 6 for the LCD element is transferred to the extraction level shifter circuit 213 by the latch circuit 212. The subsequent operations of the level shifter circuit 213, the pre-drive circuit 214, and the drive circuit 215 are the same as those of the conventional SE.
This is similar to the case of the G driver 21. The COM driver 9 also operates exactly the same as in the conventional example.

In this embodiment, since the above-mentioned operation is performed, C
When there is no write command from the PU 13, the SEG driver 21 is particularly equipped with a driver control circuit 2
17 and the shift register 211 do not operate for each pulse of the clock pulse train 4. Embodiment 2; FIG. 3 is a circuit configuration diagram of an SEG driver according to another embodiment corresponding to claims 1, 2, and 3 of the present invention. 1 and 2, the display control circuit device of the display device of the LCD panel according to the embodiment of the present invention, and FIGS.
The same parts as those of the display control circuit device of the display device of the LCD panel according to the conventional example of FIG. Reference numeral 15 is an SEG driver, which is different from the SEG driver 21 of the conventional example in the driver control circuit 217.
The difference is that a switching circuit device 18 as a clock pulse cutoff device is integrally built in at the input end side of the clock pulse train, and a terminal 151 for receiving the clock pulse train control signal 16 is added. ..

Since the different embodiment has the above-mentioned configuration, the SE is determined according to the presence / absence of the write command from the CPU 13.
The G driver 15 performs the same operation as the SEG driver 21 in the case of the above-described embodiment of the present invention, and obtains the effect that the number of parts can be reduced, in addition to the operation and effect in the case of the embodiment of the present invention. You can In the explanation so far,
The frame signal 8 is a signal whose polarity is inverted for each pulse number corresponding to the display element group for one screen of the clock pulse train 4, but, for example, in a flat panel display device using an ELD or PD. The frame signal 8 may be one in which a pulse is output for each pulse number of the clock pulse train 4 corresponding to the display element group for one screen. In this case, the write command detection circuit 17 displays one screen on the flat panel display device in which the polarity of the frame signal 8 is switched to the original polarity when, for example, the write command from the CPU 13 is absent. At the timing when the polarity of the frame signal 8 switches to the original polarity while continuing the High level state for a period
Since it only outputs the driver control signal output 16 that switches from the High level to the Low level, the CPU
SEG driver 1 when there is no write command from 13
The operations of the driver control circuits 217 and 5 and 21 of the shift register 211 so as not to perform the operation for each pulse of the clock pulse train 4 are performed in the same manner.

Further, in the above description, the internal memory 216 of the SEG drivers 15 and 21 has been described as merely a RAM, but more specifically, it has come to be used more recently in DRAM, SRAM, and more recently. Cash that came
Memory can be used. Further, in the above description, the shift register 211 included in the SEG drivers 15 and 21 receives the pulse of the horizontal scanning line signal pulse train 5 and outputs the individual display data after parallel conversion to the internal memory 216.
The shift register also receives the clock pulse train control signal 16, and depending on the presence or absence of a write command from the clock pulse train control signal 16, for example, in the case of no write command, the shift register Although the parallel conversion operation is not performed as described above, when the write command is present, when the pulse of the horizontal scanning line signal pulse train 5 is received, the individual display data after the parallel conversion is directly output to the latch circuit 212 together with the internal memory 216. You may do it.

Furthermore, in the above description, the switching circuit device 18 includes the driver control circuit 21 of each SEG driver 15 or each SEG driver 21.
Although it has been arranged immediately before the clock pulse train input end of No. 7, it may be arranged at a portion commonly transmitting the clock pulse train 4 to the SEG driver, or may be built in the LCD controller 11. Is.

[0024]

According to the present invention, one input side receives a write command from the CPU, the other input side receives an address signal from the CPU, and the output side thereof receives a driver control signal corresponding to a clock pulse train. And a write command detecting means for sending to the clock pulse train interrupting means a clock pulse train control signal for switching the operation of the clock pulse train interrupting means in accordance with the presence / absence of a write command from the CPU. A clock pulse train cutoff unit that is a switching circuit device that allows or blocks the transmission of the clock pulse train to the segment driver according to the clock pulse train control signal output from the detection unit, or the write command detection unit and the switching unit. Clock pulse train that is a circuit device Disconnection means is built in, and in accordance with a clock pulse train control signal from the write command detection means, the operation of storing the display data stored in the memory device as the individual display data in the internal memory is executed or stopped. , An SEG driver for outputting a drive output for each of the display element groups arranged in the row direction based on the individual display data stored in the internal memory, and these SEG drivers are provided from the write command detecting means. In the case of a signal indicating that there is a write command according to the clock pulse train control signal of
A clock pulse train is given from the driver control circuit of the SEG driver to the shift register to store the display data in the memory device, which has been updated by writing, in the internal memory as individual display data, and is updated by the writing. The drive output based on the display data is output to the display element group for each pulse of the horizontal scanning line signal pulse train.

When the driver control signal output is a signal indicating that there is no write command, the reception of the clock pulse train is stopped, and the shift register inputs the display data signal in synchronization with the clock pulse train to perform serial / parallel conversion. It is configured such that the drive operation based on the individual display data already stored in the internal memory is output to the display element group for each pulse of the horizontal scanning line signal pulse train.

In such a configuration, when the same screen is continuously displayed on the flat panel display device, since the display data is not changed, the clock pulse train control signal is a signal without a write command. The operation according to the clock pulse of the circuit is stopped. Along with this, the operation of converting the display data signal into parallel data for each pulse of the clock pulse train by the shift register is also stopped, so that the current consumption in the shift register and the control circuit can be significantly reduced. In this case, since the SEG driver continues the operation after the internal memory based on the horizontal scanning line signal pulse train having a cycle significantly longer than the cycle of the clock pulse train, the display operation for the display panel device continues without any trouble. To be done.

As an example, as a flat panel display device, LCD display elements of 640 columns. 480 lines, 30 total
In the case of controlling the display of an LCD panel with 7,200 arranged by an 8-bit display data signal, the current consumption value of the SEG driver when there is a write command is about 1.06 mA, whereas there is no write command. In this case, the current consumption value of the SEG driver was about 0.07 mA, which was significantly reduced to about 1/15 of the write command.

[Brief description of drawings]

FIG. 1A is a circuit configuration diagram showing a switching circuit device in FIG. 2 described later together with an SEG driver,
2B is a circuit configuration diagram of the write command detection circuit in FIG.

FIG. 2 is a circuit configuration diagram of a display control circuit device of an LCD panel according to an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of an SEG driver according to another embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a display control circuit device of a conventional LCD panel.

5 is a circuit configuration diagram of the SEG driver in FIG.

[Explanation of symbols]

1 flat panel display device (LCD panel) 4 clock pulse train 5 horizontal scanning signal pulse train 7 LCD element drive voltage 8 frame signal 9 common (COM) driver 10 memory device 11 graphic (LCD) controller 13 microprocessor (CPU) 131 control bus 132 address bus 133 data bus 15 segment (SEG) driver 151 terminal 16 clock pulse train control signal 17 write command detection means (circuit) 171 NAND circuit 173 FF 175 FF 18 clock pulse train cutoff means (switching circuit device) 21 segment (SEG) driver 211 shift register 216 internal memory 217 driver control circuit

Claims (4)

[Claims] 1. A plurality of segment drivers, a common driver, a memory device, a graphic controller,
A display control circuit device for controlling the display of a rectangular flat panel display device having a microprocessor and a plurality of display elements arranged in a plurality of columns and a plurality of rows, wherein the segment driver has an internal Of the display data to be displayed by the display element, having a memory,
Each segment driver stores the individual display data to be displayed by the display element sharing the display control in the internal memory, and the display element drive output based on the individual display data stored in the internal memory. Is output for each of the display element groups arranged in the row direction, and the common driver performs drive switching for the display element groups arranged in the row direction arranged in different rows. An output, the memory device stores display data displayed by each of the display elements, and the graphic controller stores the data in the memory device according to a read command from the microprocessor. The display data signal corresponding to the displayed display data and the timing switch that sequentially switches this display data signal. And a horizontal scanning line signal pulse train output for each of the clock pulse trains of the number of pulses corresponding to the display element group for one row is sent to the segment driver, and the horizontal scanning line signal pulse train is The microprocessor is connected to a control bus, an address bus and a data bus, and transmits the display data by the address bus and the data bus, and also via the control bus. A write command for storing the display data in the memory device,
And a write command to the graphic controller for giving a read command for causing the segment driver and the common driver to send out the display data signal and the horizontal scanning line signal pulse train. Detecting means and clock pulse train interrupting means are additionally provided, and the write command detecting means supplies a clock pulse train control signal for switching the operation of the clock pulse train interrupting means in accordance with the presence or absence of the write command from the microprocessor. The clock pulse train cutoff means transmits or receives the clock pulse train cutoff means to the segment driver in response to the clock pulse train control signal output from the write command detection means. A display control circuit device for a flat panel display device, characterized in that: 2. The display control circuit device for a flat panel display device according to claim 1, wherein the clock pulse train cutoff means is a switching circuit device, and the circuit is closed or open according to the clock pulse train control signal output from the write command detection means. Then, the display control circuit device of the flat panel display device, which allows or blocks the transmission of the clock pulse train to the segment driver. 3. A display control circuit device for a flat panel display device according to claim 1 or 2, wherein the segment driver includes a clock pulse train interruption means which is a switching circuit device, and a clock pulse train control from a write command detection means. According to the signal, the operation of storing the display data stored in the memory device as the individual display data in the internal memory is executed or stopped, and the display element is driven based on the individual display data stored in the internal memory. A display control circuit device for a flat panel display device, wherein an output is output for each display element group arranged in the row direction. 4. A display control circuit device for a flat panel display device according to any one of claims 1 to 3, wherein the write command detecting means receives a write command from the microprocessor at one of its input sides and receives at the other input side thereof. A display control circuit device for a flat panel display device, comprising: a NAND circuit which receives an address signal from the microprocessor and outputs a signal corresponding to a clock pulse train control signal from an output side thereof to a segment driver. ..