JPH05282193A - DRAM address control device and data transfer system - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To provide an address control unit of a DRAM used for a hard disk or the like that does not require refresh during data transfer and avoids a decrease in data transfer speed. A generation unit for generating / instructing an address of a DRAM 405 includes an address counter 601, a column address latch unit 605, a row address latch unit 604,
An address multiplexer 608 that multiplexes the latched column address and row address and outputs the multiplexed address to the DRAM is provided.
m bits below the column address latch means 605,
The j + m + 1 bits to the most significant bit of the address counter 601 are connected to the higher order of the column address latch means 605, and the m + 1 bits to j + m bits of the address counter 601 are connected to the row address latch means 604.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device such as a magnetic disk or an optical disk and a DRAM (Dyna) used as a data transfer buffer in a system including these storage devices.
MIC Random Access Memory) address control device and address control circuit.

[0002]

2. Description of the Related Art In a storage device such as a magnetic disk or an optical disk device, and in a system including these storage devices, the data transfer control unit and the buffer memory control unit generally have the overall configuration shown in FIG. In FIG. 4, the DRAM 405 is a host computer 401.
Is a buffer memory for temporarily storing data when accessing a storage device 409 such as a magnetic disk or an optical disk.

In the buffer memory control section, data from the host computer 401 connected to the bus 415 via the I / F (interface) section 402 and the bus 416.
And the data of the storage device 409 connected via the I / F unit 403 is arbitrated by the data control unit 404 to select one of the host side and the device side and connect to the DRAM 405 via the bus 414. .. Further, the address generation unit 408 generates an address signal 413 which indicates at which address on the DRAM 405 the data on the bus 414 should be read or written. Then, the row address strobe (R
AS) 412, column address strobe (CAS) 4
11, a buffer control signal such as a write enable (WE) 410 is sent to the DRAM 405 together with the data signal 414 and the address signal 413 to read and write data. The timing of the buffer control signal and the basic operation cycle of data access are shown in FIG. Generally, when accessing a DRAM, it is necessary to input an address to be accessed in two steps, a row address and a column address, as in the timing shown in FIG.

DRAM stores "1" and "0" depending on whether charges are stored in a capacitor made of a semiconductor. However, since the accumulated charge is discharged with time, it is necessary to rewrite the data regularly. This is called refresh, and in FIG. 4, the refresh controller 406 causes the address generator 40 to
8 and the control signal generation unit 407 are instructed to rewrite the data. During the refresh period, data transfer is generally interrupted, so that a decrease in the data transfer rate due to refresh is inevitable.

FIG. 6 shows a block diagram of the address generator 408. As shown in FIG. 6, the address generator 408
Has a host side address counter 601, a device side address counter 602, a selector 603, a row address latch 604, a column address latch 605, and an address multiplexer 608. The host-side address counter 601 sequentially counts addresses on the host side that access the DRAM 405. The device-side address counter 602 sequentially counts device-side addresses that access the DRAM 405. The selector 603 selects either the host-side address or the device-side address. The row address latch 604 and the column address latch 605 temporarily hold the address selected by the selector 603 and output it as a row address 606 and a column address 607, respectively. The address multiplexer 608 multiplexes the signals of the row address 606 and the column address 607 to generate the address signal 41.
3 is output to the DRAM 405.

A method of multiplexing the address counter output and the row address and column address in the conventional address generator 408 will be described with reference to FIG. In FIG. 7, the address counter 6 on the device side is considered by considering the state where the host side address counter is selected for simplification of description.
02 and the selector 603 for selecting one of the two addresses on the host side and the device side is omitted. In a DRAM having an address space of 2n, the binary address counter 601 requires n bits. In FIG.
0 to n-1 indicate the digit of the counter, 0 digit is the least significant, n-
One digit indicates the highest place. Further, k represents the number of bits of the row address, and (n−k) represents the number of bits of the column address.

First, the leading address on the DRAM 405 for accessing the address counter 601 is set. The address counter 601 sequentially counts each time the DRAM 405 is accessed from the address set by the host. The address latches 604 and 605 temporarily hold the address output from the address counter 601,
Bit 0 to bit n-k-1 of address counter 601
Lower bits up to column address 607, bit n-
The high-order bits from k to bit n-1 are row address 60
Output as 6. And the address multiplexer 6
08 multiplexes the row address 606 and the column address 607 output from the address latches 604 and 605. Therefore, the DRAM 405 selects the row address 606 and the column address 607 according to an instruction from the control signal generation unit 407. The address signal 413 is output to.

As described above, the DRAM always requires refreshing. There are several methods for refreshing the DRAM, but all of them have the number of row addresses (2 j power) required for refreshing determined by the DRAM within a predetermined time (refresh cycle T). Access is performed to refresh all addresses.

Therefore, if the data is read or written over the number of row addresses required for refreshing (2 to the j-th power), refreshing is performed by data transfer, and a refresh cycle during data transfer is unnecessary. Is.

However, considering that refresh is performed by data transfer in the configuration shown in FIG. 7, in order to count up the row address by one, all the column addresses (2 ((n−k−) 1) power) must be output. Therefore, in order to output the number of row addresses required for refreshing (2 to the j-th power), 2 (j + n−k−1) -th data must be transferred within the refresh cycle T. For example, the refresh format is 256 refresh cycles / 4 ms capacity 256 k × 1 bit DRAM (number of digits of address counter n = 18, k = 9, refresh cycle T = 4 m).
s, the number of refresh addresses = 256 = 2 to the power of j: j =
In 8), to perform refresh by data transfer, 6
4 kbit of continuous data is required, and the cycle time of one data must be 60 ns or less. Also, the refresh format is 1M × 1 bit DRAM (n = 20, with 512 refresh cycles / 8 ms).
k = 10, refresh cycle T = 8 ms, refresh address number = 512 = 2 to the power of j: j = 9), and 256 k
Bit continuous data is required, and the cycle time of one data must be 30 ns or less.
Thus, this method is not practical because the cycle time is fast, the usable DRAM is limited, and the amount of data continuously required is too large. Therefore, a refresh cycle dedicated to refreshing is required even during data transfer, and during that period, the memory cannot be read or written, so that the data transfer rate is unavoidably lowered.

Further, in FIG. 7, it is considered to replace the row address 606 and the column address 607 of the address counter. That is, bit 0 to bit (n-
If the lower bits up to (k-1) become the row address, the row address will be updated each time the address is counted.
The refresh cycle during the data transfer can be eliminated by simply transferring the data corresponding to the row address of (power). For example, in the 1M × 1 bit DRAM, continuous data may be 512 bits, and the cycle time of one data may be 15.6 μs or less. For example, in a hard disk, an optical disk, etc., the minimum unit of the number of transfer data is a sector, and a certain length (256, 51
2, 1024 bytes, etc.). Also, UNIX
In the system, input / output to / from the file system is performed in block units, and the minimum unit of the transfer data number is 4 kbytes, 8 kbytes, or 512 bytes or 1 kbyte even considering a fragment block. This one block of data transfer can be sufficiently refreshed.

However, in this method, since the address is counted and the row address is updated every time data is accessed, the fast page mode shown in FIG. 8, the nibble mode shown in FIG. 9, and the static column shown in FIG. 10 are used. It is not possible to use the high-speed access mode such as the mode in which a high-speed access is made only by changing the column address after confirming the row address. Therefore, the access speed of DRAM cannot be fully used. In the high-speed page mode shown in FIG. 8, after the row address is fixed, only the column address is changed at the fall (or rise) of the column address strobe (CAS) 411 to enable high-speed access. In the nibble mode shown in FIG. 9, after the row address and the column address are fixed, the address of the lower 2 bits is sequentially changed inside the DRAM at the falling edge (or rising edge) of the column address strobe (CAS) 411. By going, it is possible to access sequentially without instructing the address. In the static column mode shown in FIG. 10, even after the row address and the column address are fixed, the column address strobe (CAS) 411 is not changed, but only the column address is changed to enable high-speed access. These high-speed access modes cannot be used when the row address 606 and the column address 607 are exchanged and the column address of the address counter is changed from lower to higher.

[0013]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In M, some refresh cycle is required regardless of the presence or absence of data transfer, and during that period, reading and writing of the memory are generally interrupted. Therefore, a decrease in the data transfer rate due to refreshing is inevitable during data transfer.

There is also a method in which the row address and the column address are exchanged, and refresh is performed by data transfer. However, this method cannot use the high speed access mode and D
It cannot be expected that the data transfer speed will be increased by making full use of the power of RAM.

An object of the present invention is to provide an access means for avoiding a decrease in data transfer rate due to refresh during data transfer in a high speed access mode of DRAM.

[0016]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a DRAM address control device having an address generation unit for generating and instructing a DRAM address for a DRAM that temporarily stores data. The address generation unit multiplexes an address counter that sequentially counts data accesses, a column address latch unit that latches a column address, a row address latch unit that latches a row address, and a latched column address and a row address. And an address multiplexer for outputting to the DRAM, and the lower 0 bits to m bits of the address counter (where m is an integer of 0 or more) are placed below the column address latch means and j + m + 1 of the address counter. Bit (however, j is a natural number) ~ best Connect the bit on top of the column address latch means, said address counter m + 1
Bits ~ j + m bits are connected to the row address latch means.

Further, the address counter and the address multiplexer may be connected without providing the column address latch means and the row address latch means.

M and j are the number of row addresses required for refreshing DRAM to the power of 2j, the refresh period of DRAM is T, the minimum unit of transfer data of DRAM is D, the data transfer rate of DRAM is S, The data bus width of DRAM is W,

[0019]

[Equation 3]

[0020]

[Equation 4]

Let m satisfy the above equation.

The address generator also has an address multiplexer that multiplexes the row address and the column address and outputs an address signal to the DRAM.

The DRAM to be controlled can be accessed using fast page mode, nibble mode or static column mode.

Between one or more information processing devices that process information and transfer data and another information processing device that receives data from the information processing device, the information processing device and the other information A DRAM that temporarily holds data when performing data transfer with a processing device; a data transfer control unit that controls data transfer between the information processing device and the other information processing device via the DRAM; In a data transfer system having an address counter for sequentially counting data accesses and controlling an address of the DRAM to perform a refresh operation, the buffer memory control section stops the refresh operation during data transfer. The lower 0 bits to m bits of the address counter (where m is an integer of 0 or more) are stored in the lower order of the column address. Address counter of j + m + 1 bit (where, j is a natural number) distributing - the most significant bit to the upper column address, the m + 1 bits to j + m bits of said address counter to a row address. Also,
The other information processing device may be a storage unit.

[0025]

The address counter of the address generator sequentially counts the addresses to be accessed for each data access. Lower 0 bits to m bits (where m is an integer of 0 or more) of the address counter are set to the lower side of the column address latch, and j + m + 1 bits (where j is a natural number) to the most significant bit of the address counter. The address counter is divided into a row address and a column address by connecting to the upper part of a column address latch and connecting m + 1 bits to j + m bits of the address counter to a row address latch.

[0026]

EXAMPLE An example of the present invention will be described below.

Generally, in a recording device or a system including the recording device, data transfer is performed by using data of a certain fixed length as a minimum unit.

For example, in a hard disk, an optical disk or the like, the minimum unit of the number of transfer data is a sector and has a certain length (256, 512, 1024 bytes, etc.). Also, in the UNIX system, input / output to / from the file system is performed in block units, and the minimum unit of the transfer data number is 4 kbytes, 8 kbytes, or 512 bytes or 1 kbyte even considering a fragment block. Here, if the number of row addresses necessary for refreshing can be accessed within the refresh cycle by the data transfer of the minimum unit, the refreshing during the data transfer becomes unnecessary. In order to realize this, the relation of the following equation is necessary.

[0029]

[Equation 5]

Here, D is the minimum unit of the number of transfer data, 2
Is the number of row addresses required for refreshing, W is the data bus width of the buffer, and B is a number greater than or equal to 1 indicating how many times D is 2 to the j-th power * W. The data transfer rate S required to transfer the data amount represented by the above equation within the refresh cycle T is represented by the following equation.

[0031]

[Equation 6]

In Expressions 5 and 6, B is considered to be the number of column addresses accessible while counting up one row address. Here, if B is 2 or more,

[0033]

[Equation 7]

There is an integer m greater than or equal to 0. At this time from number 5

[0035]

[Equation 8]

The data transfer rate S is as follows.

[0037]

[Equation 9]

Transforming equation 9

[0039]

[Equation 10]

It becomes When there is an integer m equal to or greater than 0 that satisfies Eqs. 8 and 10, the (m + 1) th power of 2 is considered to be the number of column addresses accessible to the same row address, similar to B in Eqs. 9 and 10. Be done. Therefore, if the address control circuit is configured to output 2 (m + 1) th column address to one row address and count up the row address, DR
It is possible to refresh by data transfer while using the high-speed access mode of AM.

The configuration of the address control device will be specifically described below with reference to the drawings. FIG. 1 shows a method of multiplexing the address counter output, row address, and column address in the address generator of the present invention. In FIG. 1, FIG.
Similarly, for the sake of simplification of the description, considering the state where the host side address counter is selected, the device side address counter 602 and the selector 603 for selecting one of the two addresses of the host side and the device side are omitted. ing.

The address counter 601 generates an address which is sequentially counted from the set address for each data access, like the conventional one. The column address latch 605 temporarily holds bits 0 to m of the address counter 601 at its lower level and bits k + m + 1 to bit n-1 at its upper level, and outputs the upper and lower levels as a column address 607 to the address multiplexer 608. To do. Also, the row address latch 604 temporarily holds the bits m + 1 to k + m of the address counter 601, and outputs them as a row address 606 to the address multiplexer 608. Address multiplexer 608
Outputs the address signal 413 to the DRAM 405 by multiplexing the row address 606 and the column address 607 according to an instruction from the control signal generator. With this configuration, the column address is set to 2 (m
Every time the (+1) th power is output, one row address is counted.

As an example, UNIX of 8 kbytes / block
In the system, when the data width is 1 byte and the data transfer rate S is 2 MB / s, the refresh cycle T16m
s, a DRAM having a 1M address space, which is the number of row addresses 1024 required for refresh (Hitachi 1M ×
HM514400, 4Mbit DRAM with 4-bit configuration
Etc.) is used as a transfer buffer.

In Expression 8, D = 8192 bytes (2 to the 13th power), 2 to the jth power = 1024 (2 to the 10th power), W = 1
Since it is a byte, 2 (m + 1) th power = 8, and m ≦
2 is required. Also, looking at Equation 10, S
= 2 MB / s and T = 16 ms, it can be seen that the value of m (m ≦ 2) obtained by Equation 8 also satisfies Equation 10.

As described above, in the present embodiment, D is determined in consideration of the data bus width W of the buffer from the minimum unit transfer data number D and the row address number 2 required for refreshing to the power j. An integer m equal to or greater than 0 is obtained by calculating the multiple of 2 to the power of j × W (Equation 5, Equation 6 and Equation 7).
Ask for. It suffices to be able to perform refresh by data transfer within the refresh cycle T at the data transfer rate S using the obtained m. At this time, bit 0 to bit m of the address counter 601 are placed in the lower order,
Bit k + m + 1 to bit n-1 are set to the higher order, and the upper and lower order are combined to form a column address 607. Also, the bit m + 1 to the bit k of the address counter 601
+ M is the row address 606. As a result, since the lower bits of the column address come from the lower bits of the address counter, the lower m bits of the column address are counted and then the digits of the row address are counted. Therefore, even in the high-speed access mode, one row address can be accessed up to the number of column addresses up to the power of 2 (m + 1). That is, DRAM
When sequentially counting the value of the address counter, the address generation unit of the address control unit outputs the same row address so that the row address of the number necessary for refresh can be accessed by the data transfer of the minimum unit within the refresh cycle. It has an address distribution means for allocating the digits of the address counter to rows and columns so that when the number of column addresses is set and the number of column addresses is output, the row address is incremented by one.

FIG. 2 shows the configuration of the address control device when m = 2. A DRAM having an address space of 1M (2 to the 20th power) requires a 20-bit address counter, and here, the row address and the column address are each 10 bits. In FIG.
If the counter is constructed according to FIG. 1, k = 10, m =
Since 2, n = 20, the column address is bit 0 to bit 2 and bit 13 to bit 19, and the row address is bit 3 to bit 12, so these are input to the address multiplexer.

When the address counter is sequentially counted according to the data access with such a structure, the row address is counted every time eight column addresses are output. Therefore, in high-speed access mode, 1
Up to eight column addresses can be accessed for one row address.

FIG. 3 shows an example of the relationship among the row address, the column address, the row address strobe (RAS), and the column address strobe (CAS) in the high speed page mode in the configuration shown in FIG. To output eight column addresses for one row address,
As shown in FIG. 3A, there is a method of outputting eight column addresses all at once for one row address. That is, in the fast page mode, the column address strobe (CAS) 41 is set after the row address is fixed.
At the falling edge (or rising edge) of 1, high-speed access is possible by changing only the column address. Alternatively, it can be realized by outputting an arbitrary number of column addresses of 8 or less and repeating this several times. The control signals of RAS and CAS shown in FIGS. 3B and 3C are generated by a control signal generation unit described later.

In FIG. 1, in the case of the high speed page mode and the static column mode among the high speed access modes, there is no problem even if the bits of the row address and the column address are exchanged among them. Also, in the nibble mode, swapping of the bits of the row address is good, but in the column address, the lower 2 bits are fixed, and swapping of the other bits is allowed.

Although FIG. 1 shows the case where k = j, that is, (the number of bits of the row address) = (the number of bits of the row address required for refresh), when k> j (the capacity is 1 Mbit and k = 10, j = 9 DRAM, etc.)
As shown in FIG. 11, lower 0 bits to m bits of the address counter are lower in the column address, m + 1 bits to j + m bits are lower in the row address, and j + m + 1.
The bits to the most significant bit can be arbitrarily distributed to the upper bits of the remaining column address and row address. In this case, in the row address, bits can be exchanged in the lower j bits of the row address.

In FIG. 1, the address latch is used in the preceding stage of the address multiplexer, but a method of directly allocating the row address and the column address from the address counter to the address multiplexer is also possible. In this case, as shown in FIG. become.

Next, FIG. 6 shows a block diagram including the counters on the host side and the device side when the above-mentioned address generator is used.

As shown in FIG. 6, the address generator includes a host side address counter 601, a device side address counter 602, a selector 603, and a row address latch 6.
04, a column address latch 605, and an address multiplexer 608. The host-side address counter 601 sequentially counts addresses on the host side that access the DRAM 405. Device side address counter 6
02 sequentially counts the addresses on the device side that access the DRAM 405. Host side address counter 60
1 and the device side address counter 602 make bit 0 to bit m of the address counter the lower order and bit k + m + 1 to bit n−1 the higher order, and combine the upper order and the lower order to form a column address. Further, the bits m + 1 to k + m of the address counter are row addresses. The host-side address counter 601 and the device-side address counter 602 sequentially count each data access. The selector 603 selects either the host-side address or the device-side address. Row address latch 604 and column address latch 605
Holds the address selected by the selector 603 and outputs it as a row address 606 and a column address 607, respectively. Address multiplexer 608
Multiplexes the signals of the row address 606 and the column address 607 to DRA the address signal 413.
Output to M405.

In a storage device such as a magnetic disk or an optical disk device, and a system including these storage devices,
The entire structure of the data transfer control unit and the buffer memory control unit is as shown in FIG. In FIG. 4, D
The RAM 405 is a buffer memory for temporarily storing data when the host computer 401 accesses the storage device 409 such as a magnetic disk or an optical disk.

In the buffer memory control unit, the data from the host computer 401 connected to the bus 415 via the I / F (interface) unit 402 and the bus 416.
And the data of the storage device 409 connected via the I / F unit 403 is arbitrated by the data control unit 404 to select one of the host side and the device side and connect to the DRAM 405 via the bus 414. .. Further, the address generation unit 408 generates an address signal 413 which indicates at which address on the DRAM 405 the data on the bus 414 should be read or written. Then, the row address strobe (R
AS) 412, column address strobe (CAS) 4
11, a buffer control signal such as a write enable (WE) 410 is sent to the DRAM 405 together with the data signal 414 and the address signal 413 to read and write data. In FIG. 4, the refresh control unit 406 instructs the address generation unit 408 and the control signal generation unit 407 to rewrite the data except when data is being transferred. During the data transfer, the refresh operation can be performed as described above by the data transfer.
6 stops control.

As described above, since the refresh operation can also serve as the data transfer during the data transfer, it is possible to avoid the decrease in the data transfer rate due to the refresh from the refresh control unit during the data transfer.

Although FIG. 4 exemplifies data transfer between the host computer and the storage device, the present invention can be used for data transfer between another information processing device and the storage device, or between information processing devices. is there. The present invention can be used not only for data transfer between two information processing devices, but also for data transfer between a plurality of information processing devices. Further, the data transfer system of the data transfer control unit and the buffer memory control unit may be mounted on the information processing device side or the storage device side. The present invention can also be applied to a display memory in a display device.

According to the present invention, a storage device such as a hard disk or an optical disk, and a DR used as a transfer buffer between a system including these storage devices or an information processing device.
In the AM, the refresh cycle during data transfer can be eliminated, and the reduction in data transfer rate due to refresh can be avoided. Further, since the high-speed access mode can be used, the transfer speed can be increased by making the best use of the ability of the DRAM.

Further, since it can be realized by optimizing the allocation of the value of the address counter to the row and the column, the circuit scale is not increased.

[0060]

In the high speed access mode of the DRAM, it is possible to provide an access means for avoiding the reduction of the data transfer rate due to the refresh during the data transfer.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an address generator according to the present invention.

FIG. 2 is a block diagram of a specific example of an address generator according to the present invention.

FIG. 3 is a timing chart for explaining allocation of column addresses to row addresses according to the present invention.

FIG. 4 is a data transfer control unit such as a storage device according to the present invention;
FIG. 3 is a block diagram of a buffer memory control unit.

FIG. 5 is a timing chart of a basic operation cycle of DRAM.

FIG. 6 is a block diagram of an address generator.

FIG. 7 is a block diagram of a conventional address generator.

FIG. 8 is a timing chart of a fast page mode cycle.

FIG. 9 is a timing chart of a nibble mode cycle.

FIG. 10 is a timing chart of a static column mode cycle.

FIG. 11 is a block diagram of an embodiment of an address generator according to the present invention.

FIG. 12 is a block diagram of an embodiment of an address generator according to the present invention.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Yamamoto 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Inside Hitachi Imaging Information Systems Co., Ltd. Inside Hitachi Imaging Information Systems Co., Ltd. (72) Motoyasu Tsunoda 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture Inside Microelectronics Equipment Development Laboratory, Hitachi, Ltd. 2880 Kozu, Odawara Plant, Hitachi Ltd.

Claims (7)

[Claims] 1. A DRAM for temporarily storing data,
In a DRAM address control device having an address generation unit for generating and instructing a DRAM address, the address generation unit includes an address counter for sequentially counting data accesses, a column address latch unit for latching a column address, and a row address latch. Row address latching means and an address multiplexer for multiplexing the latched column address and row address and outputting the multiplexed row address and row address to the DRAM. The lower 0 bits to m bits of the address counter (where m is 0 or more). An integer) to the lower order of the column address latch means and j + m + 1 of the address counter.
A DRAM characterized in that bits (where j is a natural number) to the most significant bit are connected to the higher order of the column address latch means, and m + 1 bits to j + m bits of the address counter are connected to the row address latch means. Address control device. 2. A DRAM for temporarily storing data,
In a DRAM address control device having an address generation unit for generating and instructing a DRAM address, the address generation unit divides the output of the address counter into a column address and a row address by dividing the output of the address counter into a multi-address. Plex and DR
An address multiplexer for outputting to the AM, and the lower 0 bits to m bits (where m is an integer of 0 or more) of the address counter are placed on the lower side of the column address side of the address multiplexer, and j + m + 1 of the address counter. Bit (however, j is a natural number)
A DRAM address control device characterized in that the most significant bit is connected to the upper side of the address multiplexer on the column address side, and the m + 1 to j + m bits of the address counter are connected to the row address side of the address multiplexer. 3. The m and j according to claim 1 or 2, wherein the number of row addresses required for refreshing the DRAM is 2 to the power of j, and the refresh cycle of the DRAM is T or DR.
Let D be the minimum unit of AM transfer data, S be the DRAM data transfer rate, and W be the DRAM data bus width. [Equation 2] A DRAM address control device, wherein m satisfies the above formula. 4. A DRAM address control device according to claim 1, 2 or 3, wherein the DRAM to be controlled is accessed by using a fast page mode. 5. A DRAM address control device according to claim 1, 2 or 3, wherein the DRAM to be controlled is accessed by using a nibble mode. 6. The DRAM address control device according to claim 1, 2 or 3, wherein the DRAM to be controlled is accessed by using a static column mode. 7. The information processing device and the other information processing device, which are between one or more information processing devices that process information and transfer data, and another information processing device that receives data from the information processing device. DRAM that temporarily holds data when data is transferred to another information processing apparatus, and a data transfer control unit that controls data transfer between the information processing apparatus and another information processing apparatus via the DRAM And a buffer memory control unit for controlling the address of the DRAM by providing an address counter for sequentially counting data accesses and performing a refresh operation, wherein the buffer memory control unit performs a refresh operation during data transfer. And the lower 0 bits to m bits (where m is an integer of 0 or more) of the address counter are set to the lower order of the column address. Address counter j + m +
1 bit (where j is a natural number) to the most significant bit in the upper part of the column address, and m of the address counter
A data transfer system characterized by allocating +1 bit to j + m bit to a row address.