JPH05282144A - Pipeline processor - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a pipeline processing device in which overhead caused by intermittent data transmission and reception between a data supply unit and a pipeline processing unit is small. [Structure] Temporary storage remaining amount counter 401, which is provided at the input stage of a pipeline processing device and indicates the remaining amount of temporary storage
The value of is compared with the preset upper limit value 403 and lower limit value 406. Based on the outputs of the upper limit comparator 402 and the lower limit comparator 405, the data input request generation unit 406 having a hysteresis characteristic controls the data input request signal 307 output to the data supply unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processing apparatus for sequentially processing supplied data at high speed.

[0002]

2. Description of the Related Art As a conventional pipeline processing device,
For example, there is one disclosed in Japanese Patent Laid-Open No. 59-16053 “Pipeline arithmetic unit”. Figure 3 shows the above example
It is rewritten for easy comparison with the present invention. In the figure, a data supply unit 301 is a temporary storage 302.
Supply data to. The temporary storage 302 temporarily stores the supplied data, and then the pipeline processing unit 303.
Send to. The temporary storage control unit 304 controls the data writing from the data supply unit 301 based on the write instruction signal 305 or the data reading to the pipeline processing unit 303 based on the read instruction signal 306, and the temporary storage 302. When there is no free area at, the data input request signal 307 is controlled to stop the data transmission from the data supply unit 301.

Next, the operation will be described.

The data supply unit 301 is usually constituted by a hard-wired logic or a central processing unit, stores data for pipeline processing, and supplies the data to the temporary storage 302. Since the operation clocks of the data supply unit 301 and the pipeline processing unit 303 are generally different, clock synchronization is performed in the temporary storage 302 in addition to simple data storage. Now, when data is supplied from the data supply unit 301,
Generally, data is intermittently supplied depending on the storage capacity of the temporary storage 302 or the processing speed of the pipeline processing unit 303. In particular, when the processing speed of the pipeline processing unit 303 is slower than the data supply speed of the data supply unit 301, only intermittent data supply can be performed at all times. Further, even when the processing speed of the pipeline processing unit 303 is faster than the data supply speed of the data supply unit 301, the data supply is intermittent, such as when the data supply unit 301 is performing other processing. In some cases, it is unavoidable. Furthermore, when the storage capacity of the temporary storage 302 is small, the cycle of the intermittent operation is generally short. The temporary storage control unit 304 controls the intermittent data supply. That is, the data supply unit 301
When the pipeline processing unit 303 cannot completely process the data supplied from the temporary storage unit 302 and the temporary storage unit 302 becomes full of data, the temporary storage control unit 304 sends a data input request signal 307 to the data supply unit 301. Use to suspend the data supply. After that, the pipeline processing unit 30
When the amount of data stored in the temporary storage 302 decreases as the processing of No. 3 progresses, the temporary storage control unit 304 again causes the data supply unit 301 to respond to the data input request signal 307.
Restart the data supply from.

Now, the temporary storage control unit 304, for example,
It is configured as shown in FIG. In the figure, a write instruction signal 305 and a read instruction signal 306 cause the temporary storage remaining amount counter 401 to count up and count down, respectively. The upper limit comparator 402 compares a preset upper limit value 403 of the temporary storage remaining amount with a temporary storage remaining amount counter value. The data input request generation unit 404 also generates a data input request signal 307 based on the output of the upper limit comparator 402. The temporary storage remaining amount counter 401 is an up / down counter, and when data is input from the data supply unit 301, the write instruction signal 3
It is counted up by 05. Further, the read instruction signal 30 output from the pipeline processing device 303
Counted down by 6. The value of the temporary storage remaining amount counter 401 is then compared with the upper limit value 403 of the temporary storage remaining amount, and it is determined whether or not it has exceeded the upper limit value 403.
When the temporary storage remaining amount exceeds the upper limit value 403, the data input request generation unit 404 reverses the polarity of the data input request signal 307 and temporarily stops the data supply from the data supply unit 301. FIG. 5 shows a state of the above temporary storage remaining amount control. First, from t = 0 to t = A, the temporary storage remaining amount approaches the upper limit value 403 with time, but since it does not exceed the upper limit value 403, the data input request signal remains in the requested state. is there. At t = A,
The data input request signal 307 is once in the non-request state (data input stopped state) because the remaining temporary storage capacity exceeds the upper limit value 403. However, at t = B, since the upper limit value 403 is exceeded, the data input request signal is output. 307 is in a request state.
Further, when the upper limit value 403 is exceeded again at t = C, the data input request 307 becomes the non-request state, and at t = D, the request state is made again.

[0006]

Since the conventional pipeline processing apparatus is constructed as described above, the data input request signal is sent each time the remaining temporary storage capacity rises or falls near the upper limit value. Had to control and restart the data supply. Therefore, there is a drawback in that the overhead due to the process switching in the data supply unit increases and the processing performance deteriorates. Particularly, when the data supply unit is mainly configured by the central processing unit, the processing performance may be significantly deteriorated.

[0007]

According to the present invention, an upper limit value and a lower limit value of a temporary storage remaining amount are provided in a temporary storage control unit,
The control of the data input request signal has a hysteresis characteristic.

[0008]

The change point to the request or non-request of the data input request signal is limited to the case where the temporary storage remaining amount largely changes by providing the hysteresis characteristic.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

In the embodiment shown here, the block diagram of the entire pipeline processing apparatus is the same as that of FIG. The present embodiment is different from the conventional example in the internal configuration of the temporary storage control unit 304 in FIG. 3, and the difference will be mainly described below.

FIG. 1 is a block diagram of a temporary storage control unit 304 of a pipeline processing device according to an embodiment of the present invention. In the figure, a write instruction signal 305,
And the read instruction signal 306 causes the temporary storage remaining amount counter 401 to count up and count down, respectively. Upper limit comparator 402 and lower limit comparator 4
05 is the upper limit value 4 of the preset temporary storage remaining amount.
03, and the lower limit value 406 and the temporary storage remaining amount counter value are respectively compared. In addition, the data input request generation unit 4
04 is an upper limit comparator 402 and a lower limit comparator 405.
The data input request signal 307 is generated based on the output of The temporary storage remaining amount counter 401 is an up / down counter, and when data is input from the data supply unit 301, it is counted up by the write instruction signal 305. Further, it is counted down by the read instruction signal 306 output from the pipeline processing device 303. The value of the temporary storage remaining amount counter 401 is then compared with the upper limit value 403 and the lower limit value 406 of the temporary storage remaining amount, and it is determined whether or not the upper limit value 403 and the lower limit value 406 are exceeded. When the remaining temporary storage capacity exceeds the upper limit value 403 for the first time from the state where the temporary storage capacity is less than the lower limit value 406, the data input request generation unit 404 reverses the polarity of the data input request signal 307, and the data supply unit 301 supplies the data. Pause. In addition, once the data input request signal 307
When the data supply is stopped by reversing the polarity of, the data supply stopped state is maintained until the lower limit value 406 is first exceeded. This point is different from the conventional example. Therefore, for example, even when the temporary storage remaining amount is in the vicinity of the upper limit value 403 and the lower limit value 406, or between the both, the polarity of the data input request signal 307 does not change unnecessarily. FIG. 2 shows a state of the above temporary storage remaining amount control. In the figure, the temporary storage remaining amount increases with time from t = 0 and exceeds the lower limit 406 for the first time at the time of t = A. After that, t = B
Up and down near the lower limit 406 and below the upper limit 403, the data input request signal 307 remains in the required state until the upper limit 403 is exceeded for the first time. The data input request signal 307 becomes the non-request state at t = B when the temporary storage remaining amount is less than the lower limit value 406 and exceeds the upper limit value 403 for the first time. Immediately after that, the upper limit value 403 is again cut, or the value falls near the lower limit value 406, but from the time point t = B when the upper limit value 403 is first exceeded,
The request state of the data input request signal 307 is held until the time point t = C at which the lower limit value 406 is first exceeded. After passing t = C, the initial state is restored again, and the data request input signal 307 is kept until the temporary storage remaining amount exceeds the upper limit value 403 for the first time.
Keeps the requested state.

[0012]

As described above, according to the present invention, when the change point to the request or non-request of the data input request signal has the hysteresis characteristic, the temporary storage remaining amount greatly changes. Since it is limited to only the above, the overhead due to the processing switching in the data supply unit is reduced and the processing performance is improved. Note that the degree of hysteresis can be easily changed by changing the range sandwiched by the upper limit value and the lower limit value, so that the optimum one can be selected according to the processing characteristics of the pipeline processing unit. Further, if the upper limit value and the lower limit value are made to coincide with each other, the same function as that of the conventional example can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a temporary storage control unit of a pipeline processing device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the temporary storage control unit of the pipeline processing device according to the embodiment of the present invention.

FIG. 3 is a block diagram of a pipeline processing device according to an embodiment of the present invention and a conventional example.

FIG. 4 is a block diagram showing a temporary storage control unit of a pipeline processing device in a conventional example.

FIG. 5 is a diagram for explaining the operation of a temporary storage control unit of a pipeline processing device in a conventional example.

[Explanation of symbols]

 301 data supply unit 302 temporary storage 303 pipeline processing unit 304 temporary storage control unit 305 write instruction signal 306 read instruction signal 307 data input request signal 401 temporary storage remaining amount counter 402 upper limit comparator 403 upper limit value 404 data input request generation unit 405 Lower limit comparator 406 Lower limit value

Claims (2)

[Claims] 1. A means for temporarily storing data to be supplied,
In the case where the synchronous difference with the data supply system operating with the same or different clock is absorbed and the data input request signal is generated to the data supply system, and the free space of the temporary storage means is small or does not exist. In the pipeline processing device having a control circuit for controlling the data input request signal to stop the data input, the pipeline processing device is provided with a data input request signal control means having a hysteresis characteristic. apparatus. 2. A data input request signal control means having a hysteresis characteristic, a residual quantity counter for counting the residual quantity of data in the temporary storage means, and an upper limit comparison for comparing the residual quantity counter value with an upper limit value. And a lower limit comparator for comparing the remaining amount counter value and the lower limit value, based on the outputs of the upper limit comparator and the lower limit comparator,
The pipeline processing device according to claim 1, further comprising: a control circuit for controlling a data input request signal.