JPH0528638Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention is a subcode output circuit for outputting the subcode Q read from the disc to the outside in a CD (compact disc) playback device. Regarding.

(b) Conventional technology In a CD, an 8-bit subcode is attached to a total of 32 symbols, 24 information symbols (8 bits) and 8 validity symbols (8 bits), and these are It is EFM8-14 modulated and recorded on the disk as one frame of 588 channel bits together with a 24-bit frame synchronization signal.
Subcodes are P, Q, R, S, T, U, V, W
The P and Q channels are used for program functions such as finding the beginning of songs and playing them in a preset order. Each channel of these subcodes consists of 98 frames, or 98 bits, and in particular:
The format of subcode Q is 2 bits of subcode synchronization signals S ₀ and S ₁ , 4 bits of control data, 4 bits of address data, and 72
bit data and 16-bit CRC (Cyclic
Redundancy Code).

The subcode output circuit of a conventional CD playback device is
Detects a frame synchronization signal from the EFM signal read from the disk, demodulates the EFM signal following the frame synchronization signal to obtain an 8-bit subcode, and stores Q channel data in the subcode in a shift register. After completing the data of the subcode Q by accumulating the subcode Q for each frame, the data of the subcode Q is serially output from the shift register to an external device, for example, a microcomputer. The microcomputer uses the serially transmitted subcode Q to display the track number, time, etc., and also uses it as data for moving the optical pickup to the target value.

A technique similar to that described above is described in detail in Japanese Patent Application Laid-open No. 83261/1983.

(c) Problems to be solved by the invention However, in conventional subcode output circuits, the subcode output from the serial output terminal always starts from the MSB (most significant bit) or
It is decided that only one direction starts from the LSB (least significant bit). For example, the subcode on disk is
It is stored from the MSB direction, and serial output is also possible.
It is often output from the MSB direction. On the other hand, some microcomputers that receive serial output data have a built-in serial input function configured to input from the LSB direction.
When such a microcomputer is used to control a CD playback device, the subcodes transferred from the MSB direction must be rearranged in a direction that is easier for the microcomputer to use, resulting in inconveniences such as longer programs. It was hot.

(d) Means for solving the problem The present invention was created in view of the above-mentioned points. a frame synchronization signal detection circuit that detects a frame synchronization signal from an EFM signal, a subcode synchronization signal detection circuit that detects a subcode synchronization signal from an EFM signal, and the frame synchronization signal detection circuit. a shift control circuit that creates a shift clock for the first shift register based on the detection output of the subcode synchronization signal detection circuit and the detection output of the subcode synchronization signal detection circuit; a second shift register that outputs;
Based on a control signal applied from the outside, the parallel output of the first shift register is directly applied to the second shift register, and the order from the most significant bit to the least significant bit is changed and applied to the second register. By providing a switching circuit that can switch between the functions of subcode data, it is possible to select the external output order of subcode data from the most significant bit to the least significant bit.

(E) Effect According to the above-described means, when a predetermined control signal is applied to the switching circuit, the subcode stored in the first shift register is preset directly to the second shift register via the switching circuit. ,
When a synchronous clock pulse is externally applied to the second shift register, the subcode is outputted from the MSB direction, while when other control signals are applied to the switching circuit, the subcode accumulated in the first shift register is is preset in the second shift register with the order of MSB and LSB reversed, and when a synchronous clock pulse is applied to the second shift register at this time, the subcode is outputted from the LSB direction. Therefore, the transfer method can be freely selected depending on the type of microcomputer that serially inputs the subcode.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. 22-bit shift register 1 converts the EFM signal read from the disk into a 4.3218MHz EFM synchronization pulse created by a PLL circuit (not shown).
It is input by PLCK. The frame synchronization signal detection circuit 2 detects that the EFM signal input to the shift register 1 is a frame synchronization signal, that is, the 11 bits before and after each have a continuous value, and when the frame synchronization signal is detected, Generates detection output FSD. The 14-bit latch circuit 3 selects the 9th to 9th bits of the shift register 1.
Each 22-bit output is applied and holds the 14 bits of one symbol following the frame synchronization signal, and the output of the 14-bit latch circuit 3 converts the 14-bit EFM signal into an 8-bit symbol.
The signal is applied to the EFM decoder 4 and also to the subcode synchronization signal detection circuit 5 which detects whether the 14-bit symbol indicates a subcode synchronization signal. The subcode synchronization signal detection circuit 5 detects the synchronization signal S ₀ (00100000000001 for a 14-bit pattern).
and synchronization signal S ₁ (in a 14-bit pattern
00000000010010) and generates a detection output SSD.

On the other hand, the 8-bit output of the EFM decoder 4 is applied to the data bus 7 via the buffer 6, and the audio information symbols and validity symbols are stored via the data bus 7 in a RAM (not shown). The output of the EFM decoder 4 is also connected to a subcode register 8, and when the output data is a subcode, it is held in the subcode register 8. Further, the bit indicating the Q channel of the subcode is stored in the first shift register 9.
applied to the data input of

The first shift register 9 is composed of 80 bits, and sequentially shifts and stores the applied data in response to the shift clock SUBCLK applied from the shift control circuit 10. The shift control circuit 10 generates a shift clock SUBCLK based on the detection output SSD and the detection output FSD, and after the subcode synchronization signals S ₀ and S ₁ are detected, the detection output
Every time FSD is output, 80 shift clocks SUBCLK are generated in synchronization with the completion of input of the 14-bit symbol of the EFM signal following the frame synchronization signal. Therefore, the first shift register 9 stores subcode Q data for the 80 frame period following the subcode synchronization signals S ₀ and S ₁ , that is, 4-bit control data and 4-bit address data.
72 bits of information data is stored.

The 80-bit output of the first shift register 9 is applied to a switching circuit 11. The switching circuit 11 is
It is controlled by the control signal M/L applied to the external terminal 12. For example, when the control signal M/L is "0", the 80-bit output of the first shift register 9 is directly transferred to the second shift register 9. When the control signal M/L is “1”, the MSB and LSB of the 80-bit output of the first shift register 9 are transferred to the register 13.
The arrangement is completely reversed and transferred to the second shift register 13. Therefore, the second shift register 13 is switched to the switching circuit 1 by the preset pulse PS.
When transfer data from 1 is input, when the control signal M/L is "0", its contents are the same as those of the first shift register 9;
When L is "1", the arrangement is completely opposite to that of the first shift register 9. This second shift register 13 performs a shift operation in response to a synchronous clock pulse SCK applied to an external terminal 14 from the microcomputer, and serially outputs the held data sequentially from an external terminal 15 to the microcomputer. Therefore, when the control signal M/L is "0", the accumulated 80-bit subcode Q is the MSB.
When the control signal M/L is "1", serial output is performed from the LSB direction.

(G) Effects of the invention According to the invention as described above, the subcode Q read from the disk is MSB, depending on the serial input method of the microcomputer used.
It is possible to take out data from either the LSB direction or the LSB direction, which has the advantage of easing restrictions on microcomputer programming.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1... 22-bit shift register, 2... Frame synchronization signal detection circuit, 3... 14-bit latch circuit, 4... EFM decoder, 5... Subcode synchronization signal detection circuit, 6... Buffer, 7... Device bus, 8...Subcode register, 9...First shift register, 10...Shift control circuit, 11...
...Switching circuit, 13...Second shift register.

Claims (1)

[Scope of utility model registration request] means for converting the EFM signal read from the disk into 8-bit symbols; a first shift register to which subcode data output from the means is applied; and detecting a frame synchronization signal from the EFM signal. a frame synchronization signal detection circuit;
a subcode synchronization signal detection circuit that detects a subcode synchronization signal from the EFM signal; and a subcode synchronization signal detection circuit that detects a subcode synchronization signal from the EFM signal; a shift control circuit that creates a shift clock; a second shift register that serially outputs data to an external terminal in accordance with an externally applied synchronous clock pulse; A switching circuit is provided that selects between a function of applying the parallel output of the shift register to the second shift register as it is and a function of changing the order from the most significant bit to the least significant bit and applying it to the second shift register. . A subcode output circuit for a CD playback device, characterized in that the order of external output of the subcode data can be selected from the most significant bit to the least significant bit.