JPH05257907A - On-chip multiprocessor system - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to reduce power consumption in a multiprocessor system sharing a main memory in accordance with a load. [Configuration] If the load is lower than a certain level, the processor 101
When the determination is made, 101 passes its process to another processor 111, and thereafter controls the device 103 that shuts off its clock to stop the clock 104. [Effect] Power consumption can be reduced by stopping the clock.
In addition, the execution environment of all processes continues to be kept in good condition. When integrated in one semiconductor chip 100 at the same time, the clock terminal 121 is common to the processors, and therefore the time difference between clocks is small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system having a plurality of processors, a so-called multiprocessor information processing system (hereinafter referred to as a multiprocessor system).

[0002]

2. Description of the Related Art Conventionally, it has been proposed in Japanese Patent Laid-Open No. 61-122733 to reduce the power consumption of an information processing system having a plurality of processors. In this technique, two microprocessor devices are composed of a master system and a slave system, each clock is separate, and the power consumption is reduced by reducing or stopping the clock of the slave system when the load is low. It is intended. In addition, the technology to integrate multiple processors on a single chip of an integrated circuit is 1991 EYE International Conference on Computer Design: VISII Computers.
And Processors 128-131 (1991 IEEE INT
ERNATIONAL CONFERENCE ON Computer Design: VLSI in C
omputers & Processors pp.128-131). This technology integrates two processors capable of independently processing information on one chip. However, this document does not particularly describe how to reduce power consumption by controlling clock stop or clock frequency reduction.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention The prior art described in the above-mentioned Japanese Patent Laid-Open No. 2004-242242 is provided with a plurality of processors that share a main memory and can process a plurality of processes in parallel in a time-sharing manner. When applied to a multiprocessor system that has, some problems occur. For example, reducing the clock of some processors results in the simultaneous existence of system clocks at multiple frequencies. One numerical example is 20 MHz and 5 MHz. A circuit shared by a plurality of processors, for example, a logic circuit that manages the right to use a shared main memory includes a sequential circuit. Another example of a circuit shared by a plurality of processors is an input / output device control circuit. Therefore, sequential logic circuits that include system clocks at multiple frequencies are more complex than logic circuits that operate correctly only for system clocks at a single frequency. As an exception, consistently asynchronous / to accommodate differences between multiple system clocks
When the synchronous conversion circuit is used, it does not increase the complexity of the shared logic circuit between the processors, but the asynchronous / synchronous conversion circuit causes a delay time of 0.5-1 clock cycle, so a high-speed shared circuit is designed. The problem of being unable to do so. Secondly, if the clock of one processor is stopped, there is a problem that the processes remaining in the stopped processor cannot be executed. A process is a name of one unit and one program in a multitasking processor. Therefore, for example, in the command processing program from the user, since the command input from the user is usually made from the keyboard, only a very small CPU time is operating, and the clock of this command processing program is stopped. There is a high possibility that it will enter the program of the processor. However, although the keyboard input rate is slow, the system must respond quickly to each keystroke. Therefore, if a quick response is required, the clock supply to the processor must be restarted each time a key is input, and the overhead caused by the trouble of stopping / restarting the clock is large. In other words, the effect of reducing power consumption is diminished by the amount of overhead processing.

Regarding the on-chip multiprocessor system in which a plurality of processors are integrated on one chip, the conventional technique disclosed in the above-mentioned Japanese Patent Laid-Open Publication is used to supply a plurality of system clocks to a semiconductor chip. There must be. Therefore, when supplying a plurality of system clocks to the semiconductor chip, there is a problem that the number of external terminals of the semiconductor chip increases. Further, if the synchronous circuit described above is used, the absolute time difference between the clocks in the phase where the clock triggers match must be suppressed within a certain fixed time. When different clocks are input from a plurality of external terminals, it is difficult to satisfy this condition, especially when operating at a frequency of 100 MHz or higher.

Therefore, an object of the present invention is to reduce the power consumption in an on-chip multiprocessor system which is composed of a plurality of processors which share a main memory and can process a plurality of processes in parallel in a time division manner. Is to reduce. Further, another object of the present invention is that a problem that occurs when using the conventional technique, that is, the complexity of the logic circuit of the shared portion increases due to the use of a plurality of system clocks, or the shared portion cannot operate at high speed. Another problem is to solve the problem that the effect of reducing the power consumption is diminished due to the trouble of frequent clock stop / supply restart caused by including a process such as a user command processing process in the stop program. Another object of the present invention is to increase the number of external terminals of a semiconductor chip, which occurs when a plurality of system clocks are input to the semiconductor chip from a plurality of external terminals when a plurality of processors are integrated on one chip. Or, it is possible to solve the problem that a high-speed system is difficult to design due to a time difference between a plurality of system clocks.

[0006]

In order to achieve the above object, an on-chip multiprocessor system according to a typical embodiment of the present invention comprises a first and a second processor which share a main memory, and an external clock. And a first supply connected between the clock supply terminal and the first processor for controlling supply / interruption of a clock from the clock supply terminal to the first processor. And / a cutoff circuit, and a second supply / cutoff circuit connected between the clock supply terminal and the second processor for controlling supply / cutoff of a clock from the clock supply terminal to the second processor. It is determined that the total load of processes on one of the first and second processors is lighter than a predetermined level. In accordance with the result of the determination, the process of the one processor is transmitted to the other processor of the first and second processors, and thereafter, the process of the first and second supply / cutoff circuits corresponding to the one processor is transmitted. One is characterized in that the supply of the clock signal is stopped.

[0007]

According to the exemplary embodiment of the present invention, when it is determined that the total load of processes on one processor is less than a predetermined level, the supply of the clock signal to one processor is stopped. Therefore, the power consumption of the entire system can be reduced. Moreover, since a plurality of system clocks do not exist at the same time, the above-mentioned problem that the complexity of the logic circuit in the shared portion increases or the high-speed operation of the shared portion becomes impossible does not occur. Further, since the process such as the user command processing process is moved to another processor, the problem of reducing the power consumption due to the trouble of frequent clock stop / restart described above does not occur. Further, since one clock supply terminal to which an external clock is supplied may be provided in one chip, the number of external terminals of the semiconductor chip is increased or a time difference is generated between a plurality of system clocks, which makes it difficult to design a high-speed system. Such problems can be solved. Other objects and features of the present invention will be apparent from the following examples.

[0008]

FIG. 1 shows an example of an information processing apparatus centering on an on-chip multiprocessor according to an embodiment of the present invention. Two processors 10 inside the semiconductor chip 100
1, 111 share and use the main memory 123.
The system clock 121 is input to the clock supply terminal of the chip 100 from outside the chip. A circuit for dividing the clock from the outside to adjust the duty ratio of the clock waveform is not described because it is not related to the present invention. The system clock 121 is the semiconductor chip 100.
The signals are input to the clock input terminals of the processors 101 and 111 via the internal AND gates 102 and 112, respectively. The function of the AND gate is that both input signals are 1
Only when is output 1 as the output signal. Therefore, in the example of the processor 101, when the output signal 105 of the clock cutoff control circuit 103 is 1, the system clock 121 is the signal 104.
When the output signal 105 is 0, the system clock 121 is not transmitted to the signal 104. Processor 11
Since 1 is also the same, the description is omitted.

In the on-chip multiprocessor system of this embodiment, it is possible to perform a migration process of migrating a certain process from one processor 104 to the other processor 114 and executing it. In a multiprocessor system sharing the main memory 123, this moving process is easy. In this move processing, the restart address, information of the programming register at the time of restart, and a message requesting the process move are sent to the two processors 101 and 11 via the main memory 123.
It can be executed by transmitting information to and from 1. This processing can be realized within the scope of the current technology. In the on-chip multiprocessor system of this embodiment, each of the two processors 101 and 111 has a multitasking processing capability capable of processing a plurality of processes in parallel in a time division manner. Further, in the on-chip multiprocessor system of this embodiment, the two processors 101 and 111 are
For each of the above, there is a system call in the program that can obtain information about the current system, such as the number of currently running processes.

FIG. 2 is a flowchart of software for shutting off the clock in the multiprocessor system of FIG. This software is placed in the main memory 123 and executed by the processor 101 or 111. Especially with this software, a processor (CP
U) the number of active (running) processes is a fixed number t
In the following cases, it is judged that the load is light and the own clock is cut off. However, when the processor is active, it means that substantial calculation processing is being performed, and when the processor is not active, it means that substantial calculation processing is not being performed, such as waiting for a key input from the user. Four variables i, s, t and M are used in the operation. The variable i is used as a counter variable. The variable s is used to count the number of active processes. These four variables exist as the values of programming registers inside the processor 101 or 111. It is assumed that the variable t has been assigned with an appropriate value before the operation starts. The operation of the processor by software will be described below.

Process 201: The operation starts. Go to process 202. Process 202: Use the previous system call to get information about the process running on this processor. This system call finds the total number of processes currently running on this processor and assigns this to the variable M. Go to processing 203. The loop of the processes 203 to 207 is formed for the purpose of performing a process for all the processes from process 1 to process M. The variable i is used as a process number counter. Process 203: Substitute 1 for variable i. Substitute 0 for variable s. Go to process 204. Process 204: Check whether the i-th process is active. If the i-th process is active, go to operation 205. Otherwise, go to processing 206. Process 205: Add 1 to the variable s. Go to process 206. Process 206: Process 20 if the variable i is larger than the variable M
8 or else to step 207. Process 207: Add 1 to the variable i. Go to process 204. Process 208: At this point, the total number of active processes is substituted in the variable s. The variable s and the variable t are compared.
If s is larger than t, the processing ends. Otherwise process 20
Go to 9. Process 209: If another CPU is operating by the clock supply, proceed to process 210. Otherwise, the process cannot be moved, so processing ends. Process 210: Move all processes existing in its own CPU to another CPU via the bus 122 and the main memory 123. Go to processing 211. Process 211: Stop the clock of the own CPU. Processing Exit. The software shown in FIG. 2 is set to be automatically activated at a certain time interval, for example, every 10 minutes. Therefore, even if the user is unaware, it is possible to perform automatic operation that reduces power consumption according to the load situation.

It is needless to say that the present invention is not limited to the above-mentioned embodiment, and various modifications can be made within the scope of the technical idea thereof. For example, the number of processors is not limited to two, and three, four, or more processors are also possible. It is also possible to adopt a hierarchical memory configuration in which two private caches are arranged between the two processors 101 and 111 and the bus 122, and a shared cache is arranged between the bus 122 and the main memory 123. it can.

[0013]

According to the present invention, the power consumption is increased in the on-chip multiprocessor system including a plurality of processors that share the main memory and can process a plurality of processes in parallel in a time-sharing manner. Can be reduced. In addition, a problem that occurs when the conventional technique is used, that is, the complexity of the logic circuit of the shared portion increases due to the use of a plurality of system clocks, or the high-speed operation of the shared portion becomes impossible, or It is possible to solve the problem that the effect of reducing the power consumption is diminished due to the trouble of frequently stopping / restarting the clock caused by including a process such as a user command processing process. Further, when a plurality of processors are integrated on one chip, the number of external terminals of the semiconductor chip increases because a plurality of system clocks are input to the semiconductor chip from a plurality of external terminals, or the number of system clocks between the plurality of system clocks increases. It is possible to solve the problem that a time lag causes a difficulty in designing a high-speed system.

[Brief description of drawings]

FIG. 1 is an overall view of an information processing system including an on-chip multiprocessor system and a main memory according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a part of processing of software in the information processing system of FIG.

[Explanation of symbols]

100 ... Semiconductor chip, 101, 111 ... Processor,
102, 112 ... AND gates, 103, 113 ... Clock shutoff management device, 104, 114 ... Clock signals supplied to individual processors, 105, 115 ... Clock shutoff control signals, 121 ... System clock, 122 ... System bus, 123 ... main storage device, 201: start of processing, 202 ... 211: processing, 212: end of processing.

Front page continuation (72) Inventor Terumi Sawase 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the semiconductor design and development center, Hitachi, Ltd.

Claims (2)

[Claims] 1. A first and a second processor which share a main memory, a clock supply terminal to which an external clock is supplied, and a clock supply terminal which is connected between the clock supply terminal and the first processor. A first supply / interruption circuit for controlling supply / interruption of a clock from the clock supply terminal to the first processor; and a connection between the clock supply terminal and the second processor, A second supply / control for controlling the supply / cutoff of the clock to the second processor
A cutoff circuit is provided on a single chip, and when it is determined that the total load of processes in one of the first and second processors is lower than a predetermined level, the determination result is determined according to the determination result. Information of the process of the one processor to the other processor of the first and second processors, and then one of the first and second supply / cutoff circuits corresponding to the one processor supplies the clock signal. An on-chip multiprocessor system characterized by stopping. 2. The first and second processors are multitasking processors capable of processing a plurality of processes in parallel in a time-sharing manner, respectively. On-chip multiprocessor system.