JPH05257815A - Central processing unit - Google Patents

Abstract

PURPOSE:To protect memory contents from destruction due to illegal memory access by deciding whether a memory address for an operation instruction detected by an instruction detection part is true or false by a check part. CONSTITUTION:When the operation instruction for reading from or writing to a data area and a stack area during program execution is detected by the instruction detection part 7 from an instruction decoding result, the check part 10 decides whether the memory address for the operation instruction detected by the instruction detection part 7 is true or false according to a memory address range set in an area determination register 9. Consequently, the memory contents can effectively be protected from the destruction due to illegal memory access. Further, a detection setting register 11 decides whether or not the setting state of the memory address range by the area setting register 9 is effective or ineffective and a program check for the operation check can selectively be made.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit for controlling programs, and more particularly to a central processing unit with a memory protection function.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram illustrating the configuration of a conventional central processing unit. In the figure, 1 is a control unit for controlling each process, 2 is a memory address storing instructions (by a program counter), and data used in arithmetic and logical operations (by a general-purpose register). ), A register unit 3 for actually performing arithmetic operations or logical operations, an instruction decoding unit 4 for reading and decoding instructions, and a reference numeral 5 for outputting results of arithmetic operations or logical operations. A data bus 6 is an address bus for designating a memory address when reading or writing. The operation of FIG. 3 will be described below with reference to the flowchart shown in FIG.

FIG. 4 is a flow chart showing an example of a data transfer processing procedure in the central processing unit shown in FIG. Note that (1) to (5) show each procedure. To execute the data transfer in the program, the instruction decoding signal is sent to the instruction decoding unit 4 by the control unit 1. The instruction decoding unit 4, which has received the signal via the data bus 5, outputs the data of the program counter to the address bus 6 in order to read the contents of the memory indicated by the program counter of the register unit 2, and then via the data bus 5. The contents of memory are read and the instructions are decoded (1). The operands are also read in the same manner. The control unit 1 sends an operation signal to the arithmetic and logic operation unit 3 to execute the operation (3) when the operation processing of the operand is necessary based on the instruction decoding result of the instruction decoding unit 4 (2). After the calculation is completed, in order to store the result data in the memory, the address of the memory is output to the address bus 6 (4), the result data is output via the data bus 5 (5) and stored in the specified memory. Then, the process ends.

[0004]

Since the conventional central processing unit is constructed as described above, the program to be executed is logically wrong and the data is output to the memory area in which the instructions of the program are stored. If the contents of the memory area where the instruction is stored are destroyed, or if the stack memory overflows and the contents of the memory other than the stack area are destroyed, the central processing unit does not There is a problem that it cannot be detected that the operation is illegal.

The present invention has been made in order to solve the above problems, and detects the execution of data input / output processing with respect to a memory other than the data area or the stack area, thereby accommodating program execution. It is an object of the present invention to provide a central processing unit capable of preventing the destruction of memory contents due to unauthorized access.

[0006]

A central processing unit according to the present invention includes an instruction detecting section for detecting an operation instruction for reading or writing a data area and a stack area during program execution from an instruction decoding result, and an instruction detecting section. Based on the address detection unit that detects the memory address for the operation instruction detected by the unit, the area setting register that sets the accessible memory address range for the operation instruction, and the memory address range set in this area setting register And a check unit that determines the authenticity of the memory address for the operation command detected by the command detection unit.

Further, a detection setting register for determining whether the setting state of the memory address range by the area setting register is valid or invalid is provided.

[0008]

According to the present invention, when the instruction detection unit detects an operation instruction for reading or writing the data area and the stack area at the time of program execution from the instruction decoding result, the checking unit sets the memory address range set in the area setting register. Based on the above, the authenticity of the memory address for the operation instruction detected by the instruction detecting unit is determined, and the destruction of the memory content by the illegal memory access is effectively protected.

Further, the detection setting register makes it possible to determine whether the setting state of the memory address range by the area setting register is valid or invalid, and selectively executes the program check for the operation instruction.

[0010]

1 is a block diagram for explaining the configuration of a central processing unit showing an embodiment of the present invention. In the figure, 1 is a control unit for controlling each process, 2 is a memory address storing instructions (by a program counter), and data used in arithmetic and logical operations (by a general-purpose register). ) To register, 3
Is an arithmetic and logic operation unit that actually performs arithmetic and logical operations, 4
Is an instruction decoding unit for reading and decoding instructions, 5 is a data bus for outputting the results of arithmetic operations and logical operations, 6
Is an address bus for designating a memory address when reading or writing. Reference numeral 7 is an instruction detection unit for detecting an operation on a data area and a stack area during program execution, 8 is an address detection unit for detecting a memory address of an operation target, and 9 is an accessible range for each memory. The area setting register is provided with a data area upper address register 9a, a data area lower address register 9b, a stack area top address register 9c, a stack area bottom address register 9d, and the like. Reference numeral 10 is a check unit for detecting whether or not the operation is for the range of the memory specified by the area setting register, and 11 is for setting whether to enable or disable the detection function based on the content of the area setting register 9. It is a detection setting register of.

In the central processing unit having the above-described structure, when the instruction detecting section 7 detects an operation instruction for reading or writing the data area and the stack area during program execution from the instruction decoding result, the checking section 10 Based on the memory address range set in the area setting register 9, the authenticity of the memory address with respect to the operation instruction detected by the instruction detecting unit 7 is determined, and the destruction of the memory content due to the illegal memory access is effectively protected.

Further, the detection setting register 11 makes it possible to determine the setting state of the memory address range by the area setting register 9 as valid or invalid, and selectively executes the program check for the operation instruction.

FIG. 2 is a flow chart showing an example of a data transfer processing procedure in the central processing unit shown in FIG. Note that (1) to (9) show each procedure.

The execution of data transfer in a program is
The control unit 1 sends an instruction decoding signal to the instruction decoding unit 4. Instruction decoding unit 4 which has received a signal via data bus 5
Outputs the data of the program counter to the address bus 6 in order to read the contents of the memory indicated by the program counter of the register unit 2, reads the contents of the memory via the data bus 5, and decodes the instruction (1). .. The operands are also read in the same manner. The control unit 1 sends an operation signal to the arithmetic and logic operation unit 3 to execute the operation (3) when the operation processing of the operand is necessary based on the instruction decoding result of the instruction decoding unit 4 (2). After the calculation is completed, the control unit 1 checks whether or not the detection setting register 11 is a true value (the detection mechanism is valid) (4), and if YES, sends a command for memory operation detection to the instruction detection unit 7, It is checked whether it is an operation command (5), and if YES, a command is sent to the address detection unit 8 to obtain the address of the memory to be operated, and whether the obtained address is within the range of the area setting register 9. The check unit 10 is instructed to check whether or not it is within the range of the area setting register 9.
(6) If NO, it is possible to notify the program being executed or another program by generating exception processing (7), assuming that an illegal memory access outside the area setting registration start range has occurred. ..

On the other hand, if the determinations in steps (4) and (5) are NO (when the detection setting register 11 is a false value or is not a memory operation instruction) or when the determination in step (6) is YES (or In the case of operation within the area setting register range), the address of the memory is output to the address bus 6 to store the data in the memory (8), and the result data is output via the data bus 5 (9). , Store it in the specified memory, and finish the process.

[0016]

As described above, according to the present invention, when the instruction detecting section detects an operation instruction for reading or writing the data area and the stack area during program execution from the instruction decoding result, the checking section sets the area. Since it is configured to judge the authenticity of the memory address for the operation instruction detected by the instruction detection unit based on the memory address range set in the register, it is possible to effectively protect the memory contents from being destroyed by unauthorized memory access. You can

Further, since the detection setting register determines whether the setting state of the memory address range by the area setting register is valid or invalid, the program check execution for the operation instruction can be selectively performed.

Therefore, it becomes easy to find a logical error in the memory operation of the program to be executed,
This has the effect of significantly reducing the labor and processing time during program development and debugging.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a central processing unit showing an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a data transfer processing procedure in the central processing unit shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of a conventional central processing unit.

4 is a flowchart showing an example of a data transfer processing procedure in the central processing unit shown in FIG.

[Explanation of symbols]

 1 control unit 2 register unit 3 arithmetic logic operation unit 4 instruction decoding unit 5 data bus 6 address bus 7 instruction detection unit 8 address detection unit 9 area setting register 9a data area upper address register 9b data area lower address register 9c stack area top address Register 9d Stack area bottom address register 10 Check unit 11 Detection setting register

Claims (2)

[Claims] 1. A central processing unit for processing data according to a decoded instruction, and an instruction detection unit for detecting an operation instruction for reading or writing data area and stack area during program execution from an instruction decoding result, and this instruction. An address detection unit that detects a memory address for the operation instruction detected by the detection unit, an area setting register that sets a memory address range accessible to the operation instruction, and a memory address set in the area setting register A central processing unit, comprising: a check unit that determines the authenticity of a memory address for the operation instruction detected by the instruction detection unit based on a range. 2. The central processing unit according to claim 1, further comprising a detection setting register that determines whether the setting state of the memory address range by the region setting register is valid or invalid.