JPH05257164A - Active matrix substrate - Google Patents

Abstract

(57) [Abstract] [Purpose] In an active matrix substrate, the resistance of wiring for transmitting a video signal is reduced to prevent signal delay. [Structure] The light-shielding film 15 and the additional capacitance common wiring 8 are formed in parallel, and the light-shielding film 15 and the additional capacitance common wiring 8 are electrically connected through contact holes 7c and 9c provided in an interlayer insulating film. Therefore, the light shielding film 15 and the additional capacitance common wiring 8 are connected in parallel, and the resistance is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an active matrix substrate used in, for example, an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, active matrix display devices using liquid crystal as a display medium have been actively studied. Above all, an active matrix type display device using liquid crystal has been studied as a flat display, and its results have been steadily increasing. Such an active matrix type liquid crystal display device includes a pixel electrode, a thin film transistor (TF).
T) and the like are formed on the active matrix substrate, a counter substrate on which a counter electrode is formed, and a liquid crystal layer sealed between the counter substrates.

In particular, in an active matrix type liquid crystal display device (LCD) which is designed in a small size and high definition, the area of the picture element is small due to its design, so that it is formed between the picture element electrode and the counter electrode. Capacitor capacity becomes smaller.
Therefore, there arises a problem that the video signal cannot be held for a required time. In addition, there is a problem that the fluctuation of the potential of the bus wiring with respect to the potential of the pixel electrode becomes large. Therefore, an additional capacitance is provided to compensate for the lack of capacitance between the pixel electrode and the counter electrode.

FIG. 4 is a plan view of one pixel of a conventional active matrix substrate having an additional capacitor, and FIG. 5 is a sectional view taken along the TFT 25 of the active matrix substrate (BB ′ in FIG. 4). FIG. This active matrix substrate is formed on the insulating substrate 11 by
Semiconductor layer 3 made of polycrystalline silicon having channel layers 12a and 12b, source electrode 23 and drain electrode 24
0 is formed. Channel layer 12 of semiconductor layer 30
The electric resistance of the portions other than a and 12b is reduced by performing the doping by the ion implantation method.

On the substrate 11 covering the semiconductor layer 30,
A gate insulating film 13 is formed, and on the gate insulating film 13, gate electrodes 3a and 3b made of polycrystalline Si of either n ⁺ or p ⁺ and an additional capacitance electrode 6 are formed. The above-mentioned doping is performed on the gate electrode 3a,
3b is used as a mask. The gate electrode 3a is shown in FIG.
As shown in FIG. 5, the gate bus wiring 1 is partly formed, and the gate electrode 3 b is formed by a portion branched from the gate bus wiring 1. The additional capacitance electrode 6 is a part of the strip-shaped additional capacitance common wiring 8 as shown in FIG. 1, and the additional capacitance is formed at a portion where the additional capacitance common wiring 8 and the pixel electrode 4 face each other.

Further, a first interlayer insulating film 14 is formed on the entire surface of the substrate 11 so as to cover the gate electrodes 3a and 3b. Through holes 7 a and 7 b are provided in the first interlayer insulating film 14. A metal layer 10a branched from the source bus line 2 is formed on the through hole 7a. In addition to the branched metal layer 10a, there is a metal layer 10b formed at the same time. Source bus wiring 2
Is connected to the source electrode 23 of the TFT 25 through the through hole 7a. Here, the TFT 25 has a structure called a dual gate having the gate electrodes 3a and 3b. One contact hole 7b is
It is filled with a metal such as Al in order to ensure the electrical connection between the drain electrode 24 of the TFT 25 and the metal layer 10b.

A second interlayer insulating film 17, a light shielding film 15, a third interlayer insulating film 18 and a picture element electrode 4 are formed in this order on this. The light-shielding film 15 and the metal layer 10b are
Connection is made via a contact hole 9b provided in the second interlayer insulating film 17. The light shielding film 15 is formed of a Ti-W alloy or the like. The light shielding film 15 also plays a role of realizing ohmic contact between the metal such as Al filling the contact hole 7b and the pixel electrode 4 made of ITO or the like. The light-shielding film 15 and the pixel electrode 4 are connected via a contact hole 16b formed in the third interlayer insulating film 18.

[0008]

By the way, in this conventional substrate, the source bus line 2 which is first turned on after one of the gate bus lines 1 is turned on,
Since the time until the gate bus line 1 is turned off is sufficiently long, the video signal sent through the source bus line 2 is written in the pixel electrode 4 and the additional capacitance electrode 6 with a margin. However, in the source bus line 2 that is finally turned on, the time until the gate bus line 1 is turned off is short, so there is a problem that the writing time of the video signal is restricted.

Further, since the additional capacitance common wiring 8 is formed of n ⁺ polycrystalline Si, it cannot be said that the resistance is sufficiently small. Therefore, the signal sent to the additional capacitance common line 8 is delayed, the video signal cannot be written within the limited writing time described above, and the potential written in the pixel electrode 4 fluctuates. is there. This problem will be described with reference to FIG.

FIG. 6 shows an equivalent circuit diagram of one picture element portion. Between the picture element electrode 33 connected to the drain electrode 32 of the TFT 31 and the counter electrode 34 facing the picture element electrode 33 and connected to the counter electrode wiring, a capacitance CLC is formed with a liquid crystal layer interposed therebetween. It The drain electrode 32 of the TFT 31 is connected to the additional capacitance common line via the additional capacitance CS. Further, a capacitance Cgd is formed between the gate electrode 35 and the drain electrode 32 of the TFT 31.

At this time, when a gate-on signal is sent to the gate bus wiring of the TFT, the TFT is turned on,
The video signal Vd is written in the source bus line. Here, when the time constant of signal transmission of the additional capacitance common wiring is τCS and the signal writing time TON to the pixel electrode is TON, if the condition of τCS << TON is not satisfied, the additional capacitance CS is insufficiently charged. However, there arises a problem that the potential of the pixel electrode fluctuates.

By the way, the TFT is turned off, and τCS
The electric potential Vd 'of the pixel electrode corresponding to the actual display state after a sufficiently long time has passed is expressed by the following formula 1.

Vd ′ = Vd− {Cgd / (Cgd + CLC + CS) · ΔVg} -a (1) where ΔVg is the difference between the gate potential when the TFT is on and the gate potential when it is off. Is. “A” represents a change in potential that occurs because the additional capacitance cannot be sufficiently charged within the writing time, and is represented by the following two equations.

A = Vd · exp (−Ton / τCS) · {CS / (Cgd + CLC + CS)} (2) In the second term in the above equation 1, the voltage of the gate bus wiring changes in order to turn off the TFT. The change in the potential of the pixel electrode due to In order to perform faithful display by the written video signal, the value of the second term of the equation 1 and the value of a in the equation 2 must be reduced. In order to reduce the value of the second term in Equation 1, it is necessary that Cgd << CLC + CS (3) holds. Since the pixel electrodes are small and the CLC is small in a high-definition active matrix substrate,
To satisfy the condition of Equation 3, additional capacitance C of a certain size
S is required.

As described above, since the additional capacitance CS needs to have a certain size, it is necessary to satisfy Ton << τCS (4) in order to reduce the value of a. Especially, the drive circuit is TFT
With a small-sized and high-definition active matrix substrate formed on the same substrate as the array, it is difficult to satisfy the conditions of the above four expressions. The reason is as follows.

The number of gate bus wirings increases, and the time allocated to each gate bus wiring becomes shorter.

In the method in which the driver IC is mounted, the video signal is output to all the source bus wirings at the same time, but there is no problem. Since the data is output, the write time in the source bus line for the last write is shortened.

It is necessary to reduce the line width of the wiring in order to prevent the reduction of the aperture ratio due to the higher definition of the display device. Therefore, the resistance of the additional capacitance common wiring increases, and τCS cannot be reduced.

Even if the number of picture elements increases, the size of the additional capacitance common electrode per picture element cannot be reduced. Therefore, the total sum of the additional capacitances connected to one additional capacitance common line increases, and τCS cannot be reduced.

As a solution to such a problem, it is considered to apply a voltage having the same potential as the counter electrode to both ends of the additional capacitance common wiring, but this alone does not sufficiently reduce the resistance of the additional capacitance common wiring. Not a sufficient solution.

The present invention solves such a problem, and an object of the present invention is to provide an active matrix substrate in which the resistance of a wiring for transmitting a video signal can be reduced to prevent signal delay.

[0022]

An active matrix substrate of the present invention has a three-dimensional structure in which a pixel electrode, a light-shielding film, and a common wiring for additional capacitors are laminated on each other with an interlayer insulating film interposed therebetween. In addition, a planar structure in which the pixel electrodes are arranged in a matrix, the light-shielding film is formed in a strip shape along the pixel electrodes arranged in one direction, and the additional capacitance common wiring is formed in parallel with the light-shielding film. And the light-shielding film is electrically connected to the additional capacitance common line through a contact hole provided in the interlayer insulating film, whereby the above object can be achieved.

The light shielding film is made of W, Ti, Mo or Ti--.
It may be formed of W alloy.

[0024]

In the present invention, the light-shielding film and the additional capacitance common wiring are formed in parallel, and the light-shielding film and the additional capacitance common wiring are electrically connected through the contact hole provided in the interlayer insulating film. Therefore, the light-shielding film and the additional capacitance common wiring are connected in parallel, and the resistance is reduced.

[0025]

EXAMPLE FIG. 3 shows a schematic plan view of an active matrix display device.

This display device comprises an insulating film substrate 1 made of glass or the like.
1. A gate drive circuit 54, a source drive circuit 55 and a T
The FT array portion 53 is formed. TFT array section 5
3 is provided with a gate bus line 1 as a large number of parallel scanning lines extending from the gate drive circuit 54. From the source drive circuit 55, a large number of source bus lines 2 as signal lines are arranged orthogonal to the gate bus line 1.
Further, in parallel with the source bus line 2, the additional capacitance common line 8
Are arranged.

A TFT 25, a pixel 57 and an additional capacitor 27 are provided in a rectangular area between the two gate bus lines 1 and sandwiched by the source bus line 2 and the additional capacitor common line 8. .. The gate electrode of the TFT 25 is connected to the gate bus line 1, and the source electrode is connected to the source bus line 2. The picture element 57 is configured by enclosing a liquid crystal between the picture element electrode connected to the drain electrode of the TFT 25 and the counter electrode on the counter substrate. Further, the additional capacitance common line 8 is connected to an electrode having the same potential as the counter electrode.

FIG. 1 is a plan view of one picture element in the active matrix substrate of this embodiment. FIG. 2 is a sectional view taken along the line AA ′ in FIG. The structure of this active matrix substrate will be described according to the manufacturing process.

First, for example, CVD is performed on the insulating substrate 11.
After the semiconductor layer 30 made of polycrystalline Si was patterned by the method, an insulating film to be the gate insulating film 13 was formed on the entire surface of the substrate 11. This insulating film is formed, for example, by the CVD method,
It is formed by a sputtering method or a method of thermally oxidizing the upper surface of the polycrystalline Si thin film 30. Gate insulating film 13
Has a thickness of, for example, about 100 nm. Moreover, the layer thickness of the semiconductor layer 30 is, for example, 40 to 80 nm.

Next, after depositing low-resistance polycrystalline Si, patterning was performed to form the gate bus wiring 1, the gate electrodes 3a and 3b, and the additional capacitance common wiring 8. The additional capacitance common wiring 8 includes the additional capacitance electrode 6 which is a portion formed to project as shown in FIG. Then, the semiconductor layer 3 is formed by using the gate electrodes 3a and 3b as a mask and a mask formed by a photolithography method.
Ions are implanted into a portion other than below the 0 gate electrode.
Thereby, the channel layers 12a and 12b are formed in the semiconductor layer 30.
Is formed.

Then, a first interlayer insulating film 14 is formed on the entire surface of the substrate to have a thickness of 700 nm, for example. next,
The contact hole 7 is formed at a predetermined position of the first interlayer insulating film 14.
a, 7b and the contact hole 7c were formed. The contact holes 7a, 7b, 7c are provided on the source electrode 23, the drain electrode 24, and the additional capacitance common line 8, respectively.

Next, the source bus wiring 2 and the metal layer 10
a, 10b, 10c and the like were simultaneously formed using a low resistance metal such as Al. At this time, the metal layers 10a, 10b, 1
0c is formed so as to fill the contact holes 7a, 7b, 7c, respectively, and is connected to the source electrode 23, the drain electrode 24, and the additional capacitance common line 8. The metal layers 10a, 10b, 1 protruding on the first interlayer insulating film 14
The layer thickness of 0c is, for example, 600 nm. The metal layer 10a is a part branched from the source bus line 2,
The source bus line 2 is connected to the source electrode 23 via the metal layer 10a and the contact hole 7a.

Next, a second interlayer insulating film 17 was formed on the entire surface of this substrate to a thickness of 600 nm by, for example, the CVD method. Next, contact holes 9b and 9c were formed in the second interlayer insulating film 17. The contact hole 9b is for connecting the drain electrode, and the contact hole 9c is for electrically connecting the light shielding film 15 and the additional capacitance common line 8.

Next, the light shielding film 15 was patterned so as to fill the contact holes 9b and 9c in addition to the upper portion of the TFT 25. The material of the light-shielding film 15 is, for example, a metal such as a Ti—W alloy and has a thickness of 120 to 150 nm.
And The light shielding film 15 does not exist around the contact hole 9b, but since the metal layer 10b is formed in this portion, light does not leak from the portion where the light shielding film 15 is not present. The light-shielding film 15 can be made of a metal such as W, Ti, or Mo, in addition to the above Ti-W alloy. The light-shielding film 15 on the contact hole 9b is for making ohmic contact with the drain electrode 24 and the pixel electrode 4 described later.

Then, the third interlayer insulating film 18 is formed to a thickness of 200 n.
m, the contact hole 16b is opened, and the pixel electrode 4 is formed.
Formed.

Therefore, in the active matrix substrate of this embodiment having the above structure, the light shielding film 15 is formed.
And the additional capacitance common line 8 are formed in parallel with each other, and the light-shielding film 15 and the additional capacitance common line 8 are provided in the first and second interlayer insulating films 14 and 17, respectively.
Since they are electrically connected via c, the circuit configuration is such that the light-shielding film 15 and the additional capacitance common wiring 8 are connected in parallel, the resistance is reduced, and the occurrence of signal delay can be suppressed.

Further, since the additional capacitance common line 8 and the light-shielding film 15 have a two-layer structure, it is possible to prevent disconnection that occurs when the line width of the additional capacitance common line 8 is narrowed in order to increase the aperture ratio. it can.

[0038]

As described in detail above, the active matrix substrate of the present invention has a circuit configuration in which the light shielding film and the additional capacitance common wiring are connected in parallel, the resistance is reduced, and the occurrence of signal delay can be suppressed. .. In addition, since the additional capacitance common wiring and the light shielding film have a two-layer structure, the line width of the additional capacitance common wiring can be made small while preventing the disconnection, which results in a high aperture ratio and a bright screen. A fine display device can be provided.

[Brief description of drawings]

FIG. 1 is a plan view showing one picture element in an active matrix substrate of this embodiment.

2 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 3 is a schematic plan view of an active matrix display device including the active matrix substrate of FIG.

FIG. 4 is a plan view of one picture element in a conventional active matrix substrate.

5 is a cross-sectional view taken along the line BB ′ of FIG.

FIG. 6 is an equivalent circuit diagram of a picture element portion.

[Explanation of symbols]

 1 gate bus wiring 2 source bus wiring 3a, 3b gate electrode 4 picture element electrode 6 additional capacitance electrode 7a, 7b, 7c contact hole 8 additional capacitance common electrode 9b, 9c contact hole 10a, 10b, 10c metal layer 11 insulating substrate 12a , 12b Channel layer 13 Gate insulating film 14 First interlayer insulating film 15 Light-shielding film 16b Contact hole 17 Second interlayer insulating film 18 Third interlayer insulating film 23 Source electrode 24 Drain electrode 25 TFT 30 Semiconductor layer

Claims (2)

[Claims] 1. A three-dimensional structure in which a pixel electrode, a light-shielding film, and a common wiring for additional capacitance are stacked on each other with an interlayer insulating film interposed therebetween, and the pixel electrodes are arranged in a matrix. The light-shielding film has a planar structure in which the light-shielding film is formed in a strip shape along one direction of the element electrodes, and the additional capacitance common wiring is formed in parallel with the light-shielding film, and the light-shielding film is common to the additional capacitance. The active matrix substrate according to claim 1, wherein the active matrix substrate is electrically connected to the wiring through a contact hole provided in the interlayer insulating film. 2. The active matrix substrate according to claim 1, wherein the light shielding film is made of W, Ti, Mo, or Ti—W alloy.