JPH052478A - Program protecting system - Google Patents

Abstract

PURPOSE:To make it unable to start a CPU even when the third party produces the duplicated product and to protect a copyright by building the same cipher ROM in both CPU and program memory. CONSTITUTION:An address preparing circuit 13, after a system is started, prepares an arbitrary address A and it is inputted into a serial address transmitting circuit 15 and a cipher ROM 14. The cipher ROM 14 outputs corresponding cipher data D1 to a comparing circuit 17. On the other hand, the address A from the transmitting circuit 15 is received by a serial address receiving circuit 24 and inputted to a cipher ROM 22. At the cipher ROM 22, corresponding cipher data D2 are outputted to a serial cipher transmitting circuit 23. Here, the cipher data D2 are serially converted and transmitted to a serial cipher receiving circuit 16 as cipher data D2S. At the cipher receiving circuit 16, the cipher data D2S are re-converted and inputted to the comparing circuit 17 as the cipher data D2. At the comparing circuit 17, cipher data D1 and D2 are compared, and at the time of non-coincidence, the starting of the program is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program protection system, and more particularly to a program protection system for preventing duplication of programs of a data processing system using a CPU.

[0002]

2. Description of the Related Art A conventional technique for preventing program memory duplication in a program protection system is to divide a program memory into a plurality of program blocks.
I didn't know which program block was at the beginning of the program memory.

[0003]

The conventional program protection system described above has a drawback in that it is easy to decode the interface between the CPU and the program memory. Further, the contents of the program memory can be easily decoded by a ROM writer or the like, and therefore, there is a drawback that a copy can be easily made.

[0004]

A program protection system of the present invention stores a central processing unit having a first memory circuit storing first encrypted data and a second encrypted data identical to the encrypted data. A program memory having a second storage circuit for storing a program, an address generation circuit for generating an address for reading the first and second encrypted data from the first and second storage circuits, and A comparison circuit for comparing the first and second encrypted data read from the first and second storage circuits, a first parallel-serial conversion circuit for converting the address into a serial address of serial data, and the serial address To a first serial-parallel conversion circuit for re-converting to the address of parallel data, and one of the first and second A second parallel-serial conversion circuit that converts serial data to serial encrypted data of serial data; a second serial-parallel conversion circuit that reconverts the serial encrypted data to the encrypted data of parallel data; and the central processing unit. The data processing system having the program memory includes a control circuit for controlling switching between processing of the first and second encrypted data and normal processing.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the program protection system of the present invention.

As shown in FIG. 1, the program protection system of this embodiment includes a CPU 1, a program memory 2, and
The address decoding circuit 3 is provided.

FIG. 2 is a circuit diagram showing the configuration of the CPU 1. The CPU 1 includes a CPU core 11, a control circuit 12,
Address generation circuit 13, encryption ROM 14, serial address transmission circuit 15, serial encryption reception circuit 16
And a comparator 17.

The CPU core 11 has the same function as a conventional CPU. The control circuit 12 is a circuit for controlling the reset signal of the CPU core 11. The address generation circuit 13 has a function of generating and outputting an arbitrary address A from 00 to FFH after the system is activated. Code RO
M14 outputs the encrypted data D1 corresponding to the address A output from the address generation circuit 13. Comparison circuit 1
7 is a coincidence signal C when two input signals are compared and coincident with each other.
Is output.

The serial address transmission circuit 15 converts the address A from parallel to serial and converts the serial address AS.
And a buffer 151,
Shift register 152 and start bit addition circuit 15
3 and a clock generation circuit 154.

The serial cipher receiving circuit 16 converts the received serial cipher data D2S into serial parallel data,
A circuit for reconstructing the original parallel encrypted data D2, which includes a buffer 161 and a shift register 162.
And a start bit detection circuit 163 and a clock generation circuit 164.

FIG. 3 is a circuit diagram showing the configuration of the program memory 2. The program memory 2 has a memory core 21.
An encryption ROM 22, a serial encryption transmission circuit 23,
And a serial address receiving circuit 24.

The memory core 21 is a conventional memory in which programs are stored. The encryption ROM 22 is
It is similar to the encryption ROM 14 of the CPU 1 and outputs the encryption data D2 corresponding to the input address.

The serial cipher transmission circuit 23 is a circuit for converting the cipher D2 into parallel-serial data and transmitting it as serial cipher data D2S, and includes a buffer 231, a shift register 232, and a start bit addition circuit 233.
And a clock generation circuit 234.

The serial address receiving circuit 24 performs serial-parallel conversion on the received serial address AS,
A circuit for reconstructing the original parallel address A, including a buffer 241, a shift register 242, a start bit detection circuit 243, and a clock generation circuit 24.
4 and are configured.

The address decoding circuit 3 decodes the address A from the CPU 1 to generate a chip select signal CS for the program memory 2.

Next, the operation of this embodiment will be described.

FIG. 4 is a time chart of the circuit of this embodiment shown in FIGS.

After the power is turned on, the reset signal RS changes from the high level to the low level, that is, the control circuit 1 of the CPU 1.
When the terminal RS of 2 changes to low level, the control circuit 12
Is the terminal ST at a low level, that is, the status signal ST
Is a low level. As a result, the CPU core 11 enters a reset state when the status signal ST goes low. The address generation circuit 13 generates an arbitrary address A from addresses 00 to FFH while the reset signal RS is at a low level. Then, the reset signal R
The state of the level is maintained while S is at the high level. The address A is input to the buffer 151 of the serial address transmission circuit 15 and the terminals A0 to A7 of the encryption RO14. The cipher RO14 compares the cipher data D1 in the range of 00 to FFH corresponding to the data of the terminals A0 to A7 with the comparison circuit 1.
Output to 7.

On the other hand, since the buffer 161 of the serial cipher reception circuit 16 which is the other input of the comparison circuit 17 outputs the data FFH immediately after the power is turned on, the two inputs do not match, so the comparison circuit 17 Output is low level. The address A input to the buffer 151 is latched and held, and is output as it is and input to the shift register 152.

Next, when the reset signal RS changes from low level to high level, the clock generation circuit 154 of the serial address transmission circuit 15 is reset and counts the number of pulses of the system clock CK input to the clock generation circuit 154. Then, the transmission clock CTK is output every eight counts of the pulse.

Here, the shift register 152 does not perform the shift operation when the level of the transmission clock CTK changes from the first high level to the low level after the power is turned on. After the second level change from the high level to the low level, the serial address AS obtained by performing parallel-serial conversion of the input address A is output from the terminal SO every time the level of the transmission clock changes from the high level to the low level. ..

The start bit adding circuit 153 sets the terminal OUT output to the low level when the level of the transmission clock CTK changes from the high level to the low level for the first time after the power is turned on, and changes the level from the high level to the low level. After the second change, the transmission clock CTK
The level state of the terminal IN input is latched every time the level changes from high level to low level, and the terminal OU
The T output is set to the same level state as the terminal IN input. The terminal OUT output is held at the high level after the tenth level change from the high level to the low level. By the above operation, the address A generated by the address generation circuit 13 from the CPU 1 is input to the program memory 2 as the serial address AS.

Next, the input serial address AS
Is the serial address receiving circuit 2 of the program memory 2.
4 is input to the terminal IN of the start bit detection circuit 243. The start bit detection circuit 243 changes the start bit detection signal SD, which is the output of the terminal Q, from the low level to the high level when the input of the terminal IN changes from the high level to the low level. Start bit detection circuit 24
3 is a reception clock CR from the clock generation circuit 244
When the level state of the terminal IN returns to the high level before one pulse of K is input, the start bit detection signal SD is returned to the low level to instruct the clock generation circuit 244 to stop the counting operation of the system clock CK. To do. Then, when the tenth reception clock CRK is input, the start bit detection signal SD is set to the low level.

The clock generation circuit 244 receives the system clock CK input while the terminal TR1 is at the high level.
Count the number of pulses. When the number of pulses is counted to 8, the system clock C is used as the reception clock CRK.
One pulse having the same width as one cycle of K is output. Or later,
A similar pulse is generated every 16 counts of the number of pulses of the system clock CK.

The start bit detection circuit 243 latches the level state of the serial address AS input to the terminal IN and transmits it to the terminal OUT every time the reception clock CRK generated by the clock generation circuit 244 is input.

At the same time, the shift register 242 shifts the serial address AS input to the terminal SI every time the reception clock CRK is input, performs serial-parallel conversion, and outputs the address A reconverted to parallel data. .. At the time when the shift register 242 completes the conversion from the serial address AS to the parallel address A, that is, when the clock generation circuit 244 outputs the ninth pulse of the reception clock CRK, the system clock CK is output to the terminal SH. One stop pulse SP with the same width as one cycle is output, and this stop pulse S
P is input to the terminal C of the buffer 241. Buffer 24
1 latches the address A, which is parallel data input at the time when this stop pulse SP is input, holds it, and outputs it to the encryption ROM 22.

In the encryption ROM 22, the address A sent from the CPU 1 output from the terminal DO of the buffer 241 of the serial address receiving circuit 24 is the terminals A0 to A.
Input to 7. Then, the encrypted data D2 corresponding to the address A is output to the terminals D0 to D7. The encrypted data D2 is stored in the buffer 23 of the serial cipher transmission circuit 23.
1, the shift register 232, the start bit addition circuit 233, and the clock generation circuit 234 perform serial conversion by the same operation as the serial address transmission circuit 15 of the CPU 1 described above, and transmit the serial encrypted data D2S to the CPU 1. ..

In the CPU 1, this serial encrypted data D
2S is received by the serial cipher reception circuit 16, and the buffer 161 and the shift register 162, which are its constituent elements, are received.
Then, the start bit adding circuit 163 and the clock generating circuit 164 perform serial / parallel reconversion by the same operation as the serial address receiving circuit 24 of the program memory 2 described above, and input to the comparison circuit 17 as parallel encrypted data D2. To do.

As described above, the comparison circuit 17 receives the encryption data D1 from the encryption ROM 14 at one terminal,
The cipher data D2 from the serial cipher receiving circuit 16 is applied to the other terminal, and the two input signals D1 and
When D2 is compared and coincident, a coincidence signal C of high level is output and input to the terminal CMP of the control circuit 12.

When the terminal CMP becomes high level, the control circuit 12 releases the reset operation of the CPU core 11 by setting the status signal ST from the terminal ST to high level.

If both cipher data D1 and D2 are compared and they do not match, the status signal ST holds the low level and the program is not started.

As described above, in the present embodiment, the same encryption ROM is built in both the CPU and the program memory so that a third person can change the contents of the program memory to the RO.
There is an advantage that the CPU cannot be started even if the copy is read by the M writer to make a duplicate, and the designer's copyright can be protected.

Next, a second embodiment of the present invention will be described.

5 and 6 are block diagrams of a CPU and a program memory showing a second embodiment of the present invention.

The difference of this embodiment from the above-mentioned first embodiment is that in FIG.
This means that the program memory 5 is replaced with the program memory 5, the address generation circuit and the comparison circuit on the CPU 1 side are moved to the program memory 5 side, and the gate circuit 57 is added to the program memory 5. In this regard, the serial transfer directions of the serial encrypted data D2S and the serial address AS are opposite. The other components are the same as those in the first embodiment, and the description thereof will be omitted so as not to be redundant except those directly connected to this embodiment.

In FIG. 5, the CPU 4 of this embodiment has a CPU core 41 similar to that of the first embodiment and an encryption ROM 44.
In addition to the above, it is configured to include a serial cipher transmission circuit 42 transferred from the program memory 2 of the first embodiment and a serial address reception circuit 43.

In FIG. 6, the program memory 5 of this embodiment has a memory core 51 similar to that of the first embodiment, an encryption ROM 52, and an address generation circuit transferred from the CPU 1 of the first embodiment. 53, a serial address transmission circuit 54, a serial cipher reception circuit 55, and a comparison circuit 5
6 and a newly added gate circuit 57.

Next, the operation of this embodiment will be described.

The gate circuit 57 of the program memory 5 is
While the input of the reset terminal RST is low level, the status terminal ST is set to low level and the address terminals AO0 to
The AO7, the data terminals DO0 to DO7, the chip select terminal CSO, and the read terminal RDO are set to the high impedance state. When the input of the reset terminal RST changes from the low level to the high level, the state is maintained as it is until the high level input is applied to the comparison signal terminal CMP. When a high level input is applied to the comparison signal terminal CMP, the address terminals AI0 to AI7 and AO0 to AO7,
Data terminals DI0 to DI7 and DO0 to DO7, chip select terminals CSI and CSO, read terminals RDI and RDO
Internally connect between each.

In this embodiment, the serial address AS is transferred from the program memory 5 to the CPU 4, and the CPU 4 performs serial-parallel conversion on the address A to read the cipher data D1 from the cipher ROM 44 and program it as the serial cipher data D1S. The basic operation of transferring to the memory 5, performing serial-parallel conversion and re-converting into the encrypted data D1 and comparing with the encrypted data D2 from the encrypted ROM 52 in the comparison circuit 56 is performed by serially encrypting the serial encrypted data D1S and the serial address AS. It is the same as the above-described first embodiment except that the transfer direction is opposite.

In the comparison circuit 56, the encrypted data D1,
When the comparison result of D2 is coincident, the coincidence signal C of high level is output and input to the terminal CMP of the gate circuit 57. The gate circuit 57 receives an external address A, data D, a memory read signal R, and a chip select signal CS from the memory core 51.
Connect to.

If the comparison result of the encrypted data D1 and D2 does not match, the gate circuit 57 does not connect the address A, the data D, the memory read signal R, and the chip select signal CS from the outside to the memory core 51.

In the first embodiment described above, the contents of the cipher ROM of the program memory can be easily read by the ROM writer, whereas in the present embodiment, the cipher data is read because the cipher data is compared in the program memory. I can't
Therefore, there is an advantage that the copy of the program memory is not made.

[0045]

As described above, the program protection system of the present invention includes the encryption ROM in both the CPU and the program memory, the address generation circuit, the comparison circuit, the serial encryption for serially transferring the encrypted data and the address. By providing the transmission circuit, the serial cipher reception circuit, the serial address transmission circuit, the serial address reception circuit, and the control circuit that controls them, it is possible to prevent a system from being copied by a third party. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a program protection system of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a CPU shown in FIG.

3 is a block diagram showing an example of a configuration of a program memory shown in FIG.

FIG. 4 is a flowchart showing an example of an operation in the program protection system of this embodiment.

FIG. 5 is a block diagram showing a configuration of a CPU of a second embodiment of the program protection system of the present invention.

FIG. 6 is a block diagram showing a configuration of a program memory of a second embodiment of the program protection system of the present invention.

[Explanation of symbols]

 1,4 CPU 2,5 Program memory 3 Address decoding circuit 11,41 CPU core 12 Control circuit 13,53 Address generation circuit 14, 22, 44, 52 Cryptographic ROM 15, 54 Serial address transmitting circuit 16,55 Serial cryptographic receiving circuit 17,56 Comparison circuit 21,51 Memory core 23,42 Serial cipher transmission circuit 24,43 Serial address reception circuit 57 Gate circuit 151,161,231,241 Buffer 152,162,232,242 Shift register 153,233 Start bit addition Circuit 163, 243 Start bit detection circuit 154, 234, 164, 244 Clock generation circuit

Claims (1)

Claims: What is claimed is: 1. A central processing unit having a first memory circuit storing first encrypted data, and a second memory circuit storing second encrypted data identical to the encrypted data. A program memory storing a program, an address generation circuit for generating an address for reading the first and second encrypted data from the first and second storage circuits, and the first and second storages. A comparison circuit for comparing the first and second encrypted data read from the circuit, a first parallel-serial conversion circuit for converting the address into a serial address of serial data, and the serial address for the address of parallel data And the first serial / parallel conversion circuit for re-converting the encrypted data into one of the first and second encrypted data. A second parallel-to-serial conversion circuit for converting into encrypted data, a second serial-to-parallel conversion circuit for re-converting the serial encrypted data into the encrypted data of parallel data, the central processing unit and the program memory. A program protection system comprising: a control circuit for controlling switching between processing of the first and second encrypted data and normal processing of the data processing system.