JPH05236300A - Video display interface device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a video display interface device capable of adjusting only a video signal without narrowing the band of the video signal and performing video signal separation that does not require fine adjustment. is there. [Structure] Chip sync clamp circuit 11 that clamps an input video signal and outputs a clamp video signal
A sync separation circuit 12 for extracting a sync signal from the clamp video signal, a pulse generation circuit 13 for producing a pulse from the sync signal, and a sample / hold circuit 14 for sampling and holding the clamp video signal by the pulse signal, The slicer 15 that separates and extracts the video signal from the clamped video signal that is input based on the held signal, the brightness / contrast adjustment circuit 16 that performs processing such as amplification of this video signal, and this video signal and the synchronization signal Mixing circuit 17 for mixing and outputting as a video signal
Composed of and.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display interface device which receives a video signal and supplies it to the display device as a video signal containing a video signal having an amplitude suitable for the display device.

[0002]

2. Description of the Related Art A video display interface device displays a video signal from a video signal reproducing device recorded in a video signal storage device such as a video tape or a laser disk or a video signal from a video deck, a TV tuner or the like on a display device. In order to display, only the video signal is extracted from the video signal which is a composite video signal consisting of the video signal and the synchronization signal, and the processing such as amplification and reduction is performed, and the video signal is sent to the display device again after being mixed with the synchronization signal. ing.

In such a video display interface device, as a circuit for extracting a video signal, a circuit shown in FIG.
There is a circuit like. In the figure, 1 is an N for video signal separation for separating and outputting a video signal from an input composite video signal.
It is a PN transistor. C is a coupling capacitor, R
Reference numerals ₁ and R ₂ are voltage dividing resistors for supplying a bias for separating the video signal and the synchronizing signal to the NPN transistor 1 and outputting only the video signal.

In the circuit of FIG. 3, the input is made during the period of the video signal.
A base current flows from the terminal to the NPN transistor 1.
Therefore, the capacitor C is charged to the polarity as shown in the figure,
Negative voltage is generated on the base side. In the period when there is no video signal
Is the resistance R ₂Slowly discharge through
It This voltage becomes the reverse bias of the NPN transistor 1.
Therefore, the NPN transistor 1 is cut off during the synchronization signal period.
And only the video signal is taken out (the output terminal in the figure
Side waveform diagram).

[0005]

[Problems to be Solved by the Invention]
In the conventional video signal separation circuit, the capacitor C is used.
Extract video signal from composite video signal by flow coupling
Since the frequency bandwidth of the video signal is narrowed
There is a problem that the video signal is distorted. Furthermore, this
As shown in Fig. 4, only the video signal is taken out by the circuit of
Constant voltage V _BLDone by clamping in
It In the figure, 2 is a video signal and 3 is a sync signal waveform.
is there. V_BLIs the clamp voltage.

The clamp voltage V _BL is equal to the resistances R ₁ and R ₂ of FIG.
Therefore, the combination of the resistors R ₁ and R ₂ was changed by using a volume or the like to finely adjust V _BL . As such, this adjustment was a daunting task. The present invention has been made in view of the above points, and an object thereof is to detect the level to be clamped from the composite video signal itself, without narrowing the band of the video signal,
Another object of the present invention is to realize a video display interface device capable of adjusting only a video signal by performing video signal separation that does not require fine adjustment.

[0007]

According to the present invention for solving the above-mentioned problems, a video display interface device for supplying to a display device a video signal obtained by subjecting a video signal of an input video signal which is a composite video signal to processing such as amplification. In the above, the chip sync clamp circuit for fixing the DC level of the input video signal and outputting the clamp video signal, the sync separation circuit for separating and outputting the sync signal from the clamp video signal, and the separated A pulse generating circuit that generates a pulse from a synchronization signal and outputs the pulse, and an output pulse signal of the pulse generating circuit as a sampling pulse.
A sample / hold circuit for extracting a slice level signal from a video signal, a slicer for extracting a video signal from a clamp video signal based on the slice level signal, and a process for amplifying, reducing, etc. the video signal output from the slicer. A brightness / contrast adjustment circuit to be applied, a synchronization signal output from the sync separation circuit, and a video signal output from the brightness / contrast adjustment circuit are input to a mixing circuit that outputs a video signal that is a composite video signal. It is characterized by being configured.

[0008]

The chip sync clamp circuit clamps the input video signal at a constant DC level, and inputs the clamp video signal of its output to the sync separation circuit, the sample / hold circuit and the slicer. The sync separation circuit is a clamp
The sync signal is extracted from the video signal and input to the mixing circuit and the pulse generation circuit. The pulse generation circuit generates a pulse based on the edge of the sync signal, and the sample / hold circuit samples and holds the clamp video signal at the time of inputting the pulse. The slicer cuts off the clamp video signal by this constant level signal and takes out the video signal. The brightness / contrast adjusting circuit adjusts the amplitude of the input video signal and inputs it to the mixing circuit, and the mixing circuit mixes the video signal and the synchronizing signal and outputs the video signal.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the figure, 11 is a chip sync clamp circuit for clamping a video signal which is an input composite video signal and outputting a clamp video signal having a fixed DC level.

Reference numeral 12 is the chip sync clamp circuit 1
It is a sync separation circuit for extracting and outputting only the sync signal from the clamp video signal input from 1. Reference numeral 13 is a pulse generation circuit which rises at the rear edge of the sync signal output from the sync separation circuit 12 and generates a pulse having a constant time width. Reference numeral 14 designates a clamp video signal input from the chip sync clamp circuit 11 to the pulse generation circuit 1
3 is a sample / hold circuit that samples the pulse input from the circuit 3 as a control signal and holds it at the level of the sampled signal.

A slicer 15 clamps the video signal input by the hold level signal output from the sample / hold circuit 14 and outputs only the video signal. The output video signal is amplified or reduced by the brightness / contrast adjustment circuit 16. Etc. receive processing. Reference numeral 17 denotes a mixing circuit which mixes the sync signal output from the sync separation circuit 12 and the video signal output from the brightness / contrast adjustment circuit 16 and outputs a video signal which is a composite video signal again.

Next, the operation of the apparatus of the embodiment configured as described above will be described with reference to the time chart of FIG.
In FIG. 2, (a) is a waveform diagram of a video signal which is a composite video signal clamped by the chip sync clamp circuit 11, and the sync signal is at a level from 0 V to V _SL ,
The lowest level of the video signal is clamped at V _SL .
FIG. 7B is a waveform diagram of the sync signal separated by the sync separation circuit 12 from the signal of FIG.

FIG. 3C is a waveform diagram of a pulse which rises at an edge A which is the rear edge of the synchronizing signal generated by the pulse generation circuit 13 and has a constant time width, and FIG. 4D is for controlling the pulse shown in FIG. FIG. 7 is an output waveform diagram of the sample / hold circuit 14 in which the video signal shown in FIG. 7A is sampled as a signal and held at the level V _SL at that time. (E) is a waveform diagram of the output signal of the slicer 15.

The input video signal is clamped by the chip sync clamp circuit 11 and, as shown in FIG. 2A, the video signal is output as a clamped video signal fixed at the V _SL level. The sync signal separation circuit 12 separates the sync signal from the input clamp video signal and outputs it, and inputs it to the pulse generation circuit 13 and the mixing circuit 17 (FIG. 2B).

As shown in FIG. 2C, the pulse generation circuit 13 generates a pulse having a constant time width from the edge A which is the rear edge of the synchronization signal, and the sample / hold circuit 14
To enter. The sample / hold circuit 14 samples the input clamped video signal by the pulse from the pulse generation circuit 13, holds it at the level of V _SL , and inputs the signal having the waveform shown in FIG. 2D to the slicer 15.

The slicer 15 by V _SL level of the DC voltage inputted, extracting only video signals by clamping the clamp video signal input to V _SL level (FIG. 2 (e) Figure). The video signal thus extracted is subjected to processing such as amplification and reduction in the brightness / contrast adjustment circuit 16 to be a signal having a desired amplitude, and then mixed with a synchronization signal in the mixing circuit 17 to be a video which is a composite video signal. The signal is output to a display device (not shown).

As described above, according to this embodiment, only the video signal can be taken out without narrowing the bandwidth on the basis of the level of the video signal of the input video signal or finely adjusting the circuit structure. Now you can get adjustable video images without any complication.

[0018]

As described in detail above, according to the present invention, it is possible to adjust only a video signal without narrowing the band of the video signal and performing video signal separation that does not require fine adjustment. The practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a time chart of each signal of the apparatus of the embodiment.

FIG. 3 is a circuit diagram of a conventional video signal / sync signal separation circuit.

FIG. 4 is an explanatory diagram of conventional video signal separation.

[Explanation of symbols]

 11 chip sync clamp circuit 12 sync separation circuit 13 pulse generation circuit 14 sample / hold circuit 15 slicer 16 brightness / contrast adjustment circuit 17 mixing circuit

Claims (1)

[Claims] 1. A video display interface device for supplying a video signal obtained by subjecting a video signal of an input video signal, which is a composite video signal, to a display device to a video signal which has been subjected to processing such as amplification. Chip sync clamp circuit that outputs video signals (1
1), a sync separation circuit (12) for separating and outputting a sync signal from the clamp video signal, a pulse generation circuit (13) for generating and outputting a pulse from the separated sync signal, and the pulse A sample / hold circuit (1) for extracting a slice level signal from the clamp video signal by using the output pulse signal of the generation circuit (13) as a sampling pulse.
4), a slicer (15) for extracting a video signal from the clamp video signal based on the slice level signal, and a brightness / contrast for performing processing such as amplification and reduction on the video signal output from the slicer (15) Adjustment circuit (16)
And a sync signal output from the sync separation circuit (12) and a video signal output from the brightness / contrast adjustment circuit (16) are input to output a video signal which is a composite video signal. ) And a video display interface device comprising.