JPH05226178A - Laminated ceramic capacitor and manufacture thereof - Google Patents

Abstract

PURPOSE:To inspect a deviation of laminated layers by simple means without decreasing the yield. CONSTITUTION:A ceramic green sheet 1 is manufactured by a doctor blade method, and inner electrodes 2 and markers 3 for confirming a laminated state of a rectangle are printed by using Ag paste on the manufactured sheet 1 by a screen printing method. Then, the sheet 1 is cut in a predetermined size, necessary number of the sheets 1 in each of which the electrodes 2 are printed are laminated, and the sheets 1 in which the electrodes 2 are not printed are laminated as protective layers on and underneath the sheet 1. After laminating, this laminate is thermally press-bonded, cut to a chip size at a cutting line 4 to obtain crude chips. Then, the laminated state of the obtained crude chip is inspected from its external appearance. After the inspection, the crude chip is baked, outer electrodes are formed on exposed end faces of the inner electrodes to obtain a laminated ceramic capacitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic capacitor capable of inspecting a laminated state by an easy means without lowering the yield and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a laminated ceramic capacitor has been manufactured by the following method. First, the ceramic green sheet 1 is manufactured by a doctor blade method or the like. Then, a rectangular internal electrode 2 is printed on the produced green sheet 1 by a screen printing method or the like (see FIG. 1).
0). Next, the green sheet 1 is cut into a predetermined size, a required number of sheets 1 having the internal electrodes 2 printed thereon are stacked (FIG. 11), and the internal electrodes 2 are not printed as protective layers above and below the green sheets 1. 1 is laminated. After the lamination, the obtained laminated body is thermocompression bonded and cut into a predetermined chip size by the cutting line 4 to obtain a raw chip (FIG. 12). Next, after firing the obtained raw chip, an external electrode is formed on the exposed end surface of the internal electrode.

The monolithic ceramic capacitor has internal electrode positions inside the dielectric, that is, side margins (portions where rectangular internal electrodes are not formed from the long piece to the side surface of the chip) of all internal electrodes, and ends. The size of the margin (the part where the electrode is not formed from the short piece of the rectangular internal electrode to the chip end surface) is an important factor for guaranteeing the characteristics such as withstand voltage and humidity.

Since the side margin and the end margin are greatly influenced by the stacking accuracy of the green sheets, if the stacking deviation occurs in the manufacturing process, the side margin and the end margin change greatly, and the reliability of the multilayer ceramic capacitor becomes high. Will fall. Therefore, when manufacturing a monolithic ceramic capacitor,
The stacking accuracy was inspected at the raw chip stage.

[0005]

However, according to the above-mentioned conventional monolithic ceramic capacitor, the raw chip must be cut with a blade or the like when inspecting the lamination accuracy. That is, as can be seen from FIG. 12, since only the size of the side margin due to the measurement of the exposed position of the internal electrode can be inspected from the appearance of the raw chip, in order to check the size of the end margin, the raw chip is measured. It was necessary to cut on the internal electrode in the longitudinal direction. Therefore, the inspection takes time and
There is a problem that the yield is reduced. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems of the conventional technique and to provide a multilayer ceramic capacitor capable of inspecting a multilayer deviation by a simple means without lowering the yield and a manufacturing method thereof. ..

[0006]

Means for Solving the Problems As a result of earnest research to achieve the above-mentioned object, the present inventors have found that the side margin of a ceramic green sheet having internal electrodes is
The inventors have found that the above object can be achieved by forming a pair of stacked state confirmation markers exposed on the exposed end surfaces of the internal electrodes one by one with the internal electrodes interposed therebetween, and have reached the present invention.

That is, according to the present invention, internal electrodes for obtaining capacitance are alternately provided inside a dielectric body so as to sandwich a thin dielectric layer, and external electrodes are formed on end faces where the internal electrodes are exposed. A multilayer ceramic capacitor having a basic structure that is provided, in the side margin between the internal electrode and the side surface of the chip, a stacking accuracy confirmation marker whose stacking accuracy is confirmed by the exposure state to the internal electrode exposed end surface, Multilayer ceramic capacitors, each of which is formed with an internal electrode interposed therebetween; and an internal electrode formed by using a conductive paste for an internal electrode on a ceramic green sheet, and the internal electrode is formed in a side margin of the sheet. The step of forming the stacking accuracy confirmation markers, one by one, with the internal electrodes sandwiched between them, in which the stacking accuracy is confirmed by the exposure condition on the exposed end surface. A step of laminating a required number of sheets, a step of laminating ceramic green sheets on which internal electrodes are not formed as protective layers above and below, a step of cutting the laminated body into a chip shape, and inspecting the lamination accuracy of the obtained raw chips, The present invention also provides a method for manufacturing a monolithic ceramic capacitor, which comprises a step of firing an inspected raw chip and forming an external electrode on an exposed end surface of the internal electrode.

[0008]

In the multilayer ceramic capacitor of the present invention, a stacking accuracy confirmation marker capable of inspecting the stacking accuracy is formed at the side margin between the internal electrode and the side surface of the chip so that the stacking accuracy can be inspected depending on the exposure condition of the internal electrode exposed end surface. It is characterized by being.

The stacking accuracy confirmation marker capable of confirming the stacking state by the state of exposure to the exposed end surface of the internal electrode is provided one by one with the internal electrode sandwiched in the side margin portion between the internal electrode and the side surface of the chip. More specifically, if the length of the marker in the direction (longitudinal direction) connecting the external electrodes is equal to or shorter than the size of the end margin required to maintain the quality of the capacitor, it is formed. There is no particular limitation on the shape, and the end surface on the electrode side of the marker is placed with a side margin required to maintain the quality of the capacitor, and the width of the marker may be formed outside that end. The electrode may be formed on the exposed end surface at a position where the end is exposed.

For example, the above-mentioned stacking accuracy confirmation marker 3
Can be formed independently of the rectangular or triangular internal electrode 2 using the same material as the internal electrode (FIGS. 1 and 8). On the contrary, except for the portion to be the marker, the surrounding portion is surrounded by the internal electrode 2 to form the white portion 7, and the white portion 7 can be used as the stacking accuracy confirmation marker ( (Figure 9).

By internally installing the above-mentioned stacking state confirmation marker, the stacking accuracy in the longitudinal direction of the raw chip and the direction orthogonal to the direction (excluding the stacking direction) can be inspected from the appearance of the raw chip. Will be able to. For example, when the ceramic green sheets 1 on which the rectangular stacked state confirmation markers 3 are formed are stacked (FIG. 5A),
One exposed end surface 5 of the internal electrode in the obtained raw chip
(Hereinafter, referred to as "end face A") and the other internal electrode exposed end face 6 (hereinafter referred to as "end face B") have appearances as shown in FIGS. 5B and 5C.

However, when stacking the sheets 1 on which the markers 3 are formed, as shown in FIG. 6A, a stacking deviation occurs in the longitudinal direction to the extent that the quality of the capacitor cannot be maintained (end face). The sheet A on the side A) has an appearance as shown in FIG. 6B for the end face A and the end face B of the obtained raw chip as shown in FIG. 6C. That is, when the stacking displacement occurs in the longitudinal direction, the stacking state confirmation markers 3 formed on both sides of the inner electrode 2 on both sides of the inner electrode exposed end face are not exposed at all.

The sheet 1 on which the above-mentioned marker 3 is formed
When the capacitors are laminated, as shown in FIG. 7 (a), when a lamination deviation occurs such that the quality of the capacitor cannot be maintained in the direction orthogonal to the longitudinal direction (excluding the lamination direction) (on the end face A side). (Sheet misalignment), the end face A of the obtained raw chip has an appearance as shown in FIG. 7 (b), and the end face B has an appearance as shown in FIG. 7 (c). That is, when a stacking deviation occurs in the direction orthogonal to the longitudinal direction (excluding the stacking direction), one of the stacked state confirmation markers 3 formed on both sides of the internal electrode 2 on one exposed end surface of the internal electrode The one-sided marker 3 is not exposed at all.

Hereinafter, the present invention will be described in more detail with reference to Examples. However, the scope of the present invention is not limited by the following examples.

[0015]

Example 1 An example of the monolithic ceramic capacitor of the present invention and a method for manufacturing the same will be described below.

First, a ceramic green sheet 1 was produced by the doctor blade method. Next, the internal electrode 2 and the rectangular laminated state confirmation marker 3 were printed on the produced green sheet 1 by a screen printing method using Ag paste (FIG. 1). The positional relationship between the stacked state confirmation marker 3 on the sheet 1 and the internal electrodes is as shown in FIG.

FIG. 4 is an enlarged view of a portion corresponding to two chips in the sheet 1, where a is a side margin which is absolutely necessary for maintaining the quality of the capacitor. The width h of the stacked state confirmation marker 3 is not particularly limited as long as it is smaller than the allowable margin b obtained by subtracting the minimum absolutely necessary margin a from the side margin c.
Further, f is the minimum end face margin required to maintain the quality of the capacitor, and the length d of the stacked state confirmation marker 3 is equal to the minimum end margin g from the end margin g. Or if it is short, it is good, and if it is short, high quality is guaranteed.

Next, the green sheet is cut into a predetermined size, a required number of sheets 1 having the internal electrodes 2 printed thereon are stacked (FIG. 2), and a green layer having no internal electrodes as protective layers is formed above and below the green sheets. Sheet 1 was laminated. After the lamination, this laminated body was thermocompression bonded and cut into a chip size with a cutting line 4 to obtain a raw chip (FIG. 3). Next, the stacked state of the obtained raw chips was visually inspected (judged from the exposed state of the stacked state confirmation marker). After the inspection, the raw chip was fired to form an external electrode on the exposed end surface of the internal electrode to obtain a monolithic ceramic capacitor.

In this embodiment, the rectangular laminated state confirmation marker 3 is formed on the green sheet 1. The marker 3 has the cutting line 4 at the top of the sheet for two chips as shown in FIG. It may be an isosceles triangle. By forming the stacking state confirmation marker in such a shape, by measuring the width of the stacking state confirmation marker exposed on the internal electrode exposed end surface, it becomes possible to determine how much the stacking misalignment occurs. It is possible to correct the position.

[0020]

Example 2 Another example of the laminated ceramic capacitor of the present invention is shown below. In the present embodiment, the laminated state confirmation marker is not formed on the ceramic green sheet independently of the internal electrodes, but as shown in FIG. 9, the rectangular internal electrode has a central portion (the internal electrode is exposed after cutting into a chip shape). A monolithic ceramic capacitor was manufactured in the same manner as in Example 1 except that a white portion 7 was formed by swelling (the end portion) to a frame shape and the white portion 7 was used as a laminated state confirmation marker.

In the multilayer ceramic capacitor of this embodiment, the stacking accuracy can be easily inspected as in the case where the stacking accuracy confirmation marker independent of the internal electrodes is formed, and the contact between the internal electrode and the external electrode is made. Since the area is increased, the strength is high and the contact resistance is lowered.

[0022]

With the development of the present invention, the stacking accuracy can be easily and accurately inspected from the appearance (exposed state of the stacking state confirmation marker) without cutting the raw chip obtained in the manufacturing process of the multilayer ceramic capacitor. I was able to do it. Therefore, the decrease in yield is prevented,
The time required for the stacking accuracy inspection process has been greatly reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of the method of the present invention step by step, and is a top view showing a ceramic green sheet on which internal electrodes and markers for confirming a laminated state are formed.

FIG. 2 is a diagram showing an example of the method of the present invention step by step, and is a top view showing a state in which the ceramic green sheets shown in FIG. 1 on which internal electrodes and markers for confirming the laminated state are formed are laminated.

FIG. 3 is a diagram showing an example of the method of the present invention step by step, and is a perspective view showing a raw chip obtained by laminating protective layers on the upper and lower sides of the sheet of FIG. 2 and cutting into a chip size.

FIG. 4 is a plan view showing a positional relationship between a laminated state confirmation marker and an internal electrode on a ceramic green sheet on which an internal electrode is formed in a manufacturing process of the laminated ceramic capacitor of the present invention.

FIG. 5 is a diagram showing an embodiment in the case where no stacking deviation occurs in the manufacturing process of the multilayer ceramic capacitor of the present invention, in which (a) is a stack of sheets on which internal electrodes and stacked state confirmation markers are formed. The top view which shows the aspect at the time, (b) is a side view which shows one internal electrode exposure end surface of a raw chip, (c) is a side view which shows the other internal electrode exposure end surface of a raw chip.

FIG. 6 is a diagram showing a mode in the case where a stacking deviation occurs in a direction connecting internal electrode exposed end faces in a manufacturing process of the multilayer ceramic capacitor of the present invention, wherein (a) is an internal electrode and a stacking state confirmation marker. Top view showing a mode when stacking the sheets on which is formed, (b) is a side view showing one internal electrode exposed end surface of the raw chip, and (c) is a side view showing the other internal electrode exposed end surface of the raw chip. Is.

FIG. 7 is a diagram showing an aspect in which a stacking deviation occurs in a direction (excluding the stacking direction) orthogonal to the direction connecting the internal electrode exposed end faces in the manufacturing process of the multilayer ceramic capacitor of the present invention, ) Is a top view showing a mode in which sheets having internal electrodes and markers for confirming the stacked state are stacked, (b) is a side view showing one internal electrode exposed end surface of the raw chip, and (c) is a raw chip. It is a side view which shows the other internal electrode exposed end surface.

FIG. 8 is a top view showing a ceramic green sheet on which internal electrodes and markers for confirming the laminated state are formed in the manufacturing process of another example of the laminated ceramic capacitor of the present invention.

FIG. 9 is a top view showing a ceramic green sheet on which internal electrodes and markers for confirming a laminated state are formed in a manufacturing process of still another example of the laminated ceramic capacitor of the present invention.

FIG. 10 is a diagram showing a stepwise manufacturing process of a conventional monolithic ceramic capacitor, which is a top view showing a ceramic green sheet having internal electrodes formed thereon.

FIG. 11 is a diagram showing a stepwise manufacturing process of a conventional monolithic ceramic capacitor, in which internal electrodes are formed.
FIG. 3 is a top view showing a mode in which the ceramic green sheets shown in FIG.

FIG. 12 is a diagram showing stepwise a manufacturing process of a conventional monolithic ceramic capacitor, which is a perspective view showing a raw chip obtained by laminating protective layers on the upper and lower sides of the sheet of FIG. 11 and cutting into a chip size. is there.

[Explanation of symbols]

 1 ・ ・ ・ Ceramic green sheet 2 ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥

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[Procedure amendment]

[Submission date] July 1, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

The stacking accuracy confirmation marker capable of confirming the stacking state by the exposure state to the exposed end surface of the internal electrode is provided one by one with the internal electrode sandwiched in the side margin portion between the internal electrode and the chip side surface. More specifically, the length of the marker in the direction of connecting the external electrodes (longitudinal direction) is determined in order to maintain the quality of the capacitor.
Equal to minimum margin size f or or its
It is longer than this and does not exceed the sum of the lengths of the allowable ranges e and f.
It is sufficient if the length is sufficient, and the end face on the electrode side of the marker is arranged with a side margin required to maintain the quality of the capacitor, and the width of the marker is formed outside that, and the marker is The electrode may be formed on the exposed end surface at a position where the end is exposed.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

FIG. 4 shows the chip 2 in the sheet 1.
FIG. 6 is an enlarged view of a portion corresponding to the number of parts, and a is a side margin that is absolutely necessary to maintain the quality of the capacitor. The width h of the stacked state confirmation marker 3 is
There is no particular limitation as long as it is smaller than the allowable margin b obtained by subtracting the minimum absolutely necessary margin a from the side margin c. Further, f is a margin of the end face that is absolutely necessary to maintain the quality of the capacitor, and the length d of the stacked state confirmation marker 3 is the same as the margin f that is absolutely necessary.
Equal or long, and do not exceed the sum of the lengths of allowable ranges e and f
If the length is short, the quality is guaranteed if the length is short.

Claims (2)

[Claims] 1. A basic structure in which internal electrodes for alternately accumulating a capacitance are sandwiched between thin dielectric layers and are internally provided inside the dielectric so as to alternately face each other, and external electrodes are formed on end faces where the internal electrodes are exposed. A multilayer ceramic capacitor having a structure,
In the side margin between the internal electrode and the chip side surface,
A stacking accuracy confirmation marker whose stacking accuracy is confirmed by the exposure condition to the exposed end surface of the internal electrode is 1
A monolithic ceramic capacitor characterized by being formed one by one. 2. A stacking accuracy confirmation in which an internal electrode is formed on a ceramic green sheet by using a conductive paste for an internal electrode, and a stacking accuracy is confirmed by an exposure state of an internal electrode exposed end surface at a side margin of the sheet. A step of forming the markers one by one with the internal electrode sandwiched therebetween, a step of stacking the required number of the above-mentioned sheets, and a step of stacking ceramic green sheets on which the internal electrodes are not formed as protective layers above and below the stacked body into a chip shape. A method of manufacturing a monolithic ceramic capacitor, comprising: a step of inspecting the stacking precision of the obtained raw chip after cutting, and a step of firing the inspected raw chip to form an external electrode on the exposed end surface of the internal electrode.