JPH05219037A - Independent synchronous type serial data communication device - Google Patents

Abstract

PURPOSE:To excellently preserve data sent in a network in any case by controlling the length of a preamble to proper length through only one buffer. CONSTITUTION:Serial data are inputted and a mode decision part 29 detects and decide a mode; when it is decided that the communication mode is a basic mode, a clock phase control part 28 increases or decreases the preamble length detected by a preamble length detection part 27 in response to a signal MODE indicating the decided mode according to buffer consumption B detected by a buffer consumption detection part 26. When the mode decision part 29 decides that the communication mode is a hybrid mode, on the other hand, the clock phase control part 28 does not adjust the preamble length detected by the preamble length detection part 27 according to the buffer consumption B detected by the buffer consumption detection part 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes serial data transmitted asynchronously or synchronously and asynchronously in a communication network independent synchronization based on an independent clock frequency for each station connected to the network. The present invention relates to an independent synchronous serial data communication device for communicating by means of a device for maintaining the transmitted data well by controlling the length of a preamble added as auxiliary data to the serial data in any case. Regarding implementation.

[0002]

2. Description of the Related Art Generally, since most transmission / reception circuits connected to a communication network take several bits time from the appearance of an input to the output of a valid output, it is usually preceded by each data constituting the serial data. A bit string called a preamble is added to perform time compensation until a steady state, that is, a state in which these transmitting and receiving circuits can send an effective output to the system.

Also, in such a communication network, as the transmission mode of the serial data, an asynchronous communication mode (hereinafter referred to as a basic mode) applied to the transmission of only packets, and an asynchronous mode related to the packet transmission are usually used. In addition to communication, it has two modes: a communication mode (hereinafter referred to as a hybrid mode) that enables real-time transmission of voice and images, that is, synchronous communication. The outline of each of these modes will be briefly described below.

First, in the case of the basic mode, as shown in FIG. 21, as a serial data, data having a length of 6 to 9000 symbols (1 symbol = 5 bits), which is usually called a frame, starts from a minimum of 16 symbols. With the preamble PA, the stations are connected to and connected to the communication network. That is, the station that wants to transmit the frame will acquire the token indicating the transmission right of the frame and then transmit the frame with the preamble of at least 16 symbols added. However, in transmitting this frame, the frame transmission is not started immediately after the token is acquired, and a time loss of about 3.5 μs at the maximum may occur during the transmission. This corresponds to about 86 symbols in the number of preambles. As shown in FIG. 21, the start position of the data (frame) is designated by the start code JK.

In particular, in the basic mode, the preamble is often called idle. In the case of this basic mode, the token in the network and the part other than the data (packet) transmitted from a certain station as the above frame are filled with this preamble (idle). For this reason, if the token disappears from the network for some reason, and there is no data (packet) being sent to the network at that time, this preamble has several million symbols. Sometimes reaches.

On the other hand, in the case of the hybrid mode, as shown in FIG. 22, as the same serial data, data having a length of 3120 symbols, which is usually called a cycle, is cycled together with a fixed length preamble PA. It will be transmitted from a specific station called the master.
According to the communication standard defined as FDDI-II (Fiber Distributed Data Interface-II), the length of the preamble PA is often set to 5 symbols. Then, each station other than the cycle master appropriately rewrites the data in the cycle to be transmitted and transmits it as data to multiple stations.

Also in this hybrid mode, the start position of the data (cycle) is the start code J.
Although designated by K, in the case of this hybrid mode in particular, as shown in FIG. 22, an identifier unique to the hybrid mode called a cycle header (CH) is also added.

By the way, in such a communication network, since the stations connected to the network operate independently in synchronization as described above, the frequencies of these stations are changed especially when in the hybrid mode. The cumulative phase difference of the transmission serial data caused by a subtle difference cannot be ignored. This state is shown in FIGS. 23 and 24.

That is, in FIG. 23, the first station to the n-th station
The station n is a station connected to the communication network, and it is assumed that the station n receives the serial data S0 transmitted at the transmission frequency f0 and temporarily stores the serial data S0 in the buffer memory. First station 1 to transfer to station
However, the internal frequency f is slightly lower than the transmission frequency f0.
At 1, the read (transfer) operation of the stored data is performed. The serial data S1 (transmission frequency f1) transferred from the first station 1 is received and temporarily stored in the buffer memory. The second station 2 which transfers the stored data to the next station performs the read (transfer) operation of the stored data at the internal frequency f2 slightly higher than the frequency f1. The third station 3, which receives the serial data S2 (transmission frequency f2) to be stored and temporarily stores it in the buffer memory, and further transfers the stored data to the next station, has an internal frequency slightly higher than the frequency f2. If the read (transfer) operation of the stored data is performed at f3, the phases of the serial data S0 to S3 will vary as shown in FIGS. 24 (a) to 24 (d). The things. And, when such phase difference is accumulated, in the connecting station in the latter stage,
Overflow or underflow occurs in the buffer memory for temporary data storage, and even normal operation cannot be guaranteed.

This situation is almost the same in the basic mode as well. However, in this basic mode, since it is not possible for each station to grasp how long the preamble is, it is not possible to grasp the buffer. The probability of memory overflow is further increased. And in the case of this basic mode,
Since the maximum data (frame) length may be almost three times the data (cycle) length in the hybrid mode, it is necessary to set a large buffer allowance itself of the buffer memory.

For this reason, conventionally, each station is provided with a device as shown in FIG. 25, and the length of the preamble is increased or decreased through the device, thereby eliminating these disadvantages in the hybrid mode and the basic mode. I am trying to resolve it.

Incidentally, in the device shown in FIG. 25, the internal clock source 11 is a part for generating a clock signal for determining the operating frequency of the station, and the elastic buffer 12 and the smoothing buffer 13 respectively store the serial data. The clock extracting unit 14 is a unit for temporarily storing in a FIFO (First-in First-out) format.
Is a part for extracting the transmission clock from the input serial data and writing the serial data in the elastic buffer 12 based on the extracted clock WC1. The clock phase control unit 16 detects the amount of data written in the buffer 12, that is, the buffer usage amount of the buffer 12 each time, and the clock phase control unit 16 shifts the data phase due to the frequency difference between the stations through the elastic buffer 12. Internal clock source 1 in order to absorb the
The phase of the clock generated from 1 is phase-shifted (advanced or delayed) based on the detection output of the buffer usage detector 15, and is stored in the elastic buffer 12 by the clock RC1 of the controlled phase. The preamble length detection unit 17 detects the length of the preamble PA included in the data from the serial data read from the elastic buffer 12 (for example, the preamble P).
A is a part for detecting A and counting its length), the buffer usage amount detecting part 18 is a part for detecting the buffer usage amount for each of the smoothing buffers 13, and the clock phase control part 19 is for smoothing. In order to increase or decrease the length of the preamble PA through the buffer 13, the phase of the clock generated from the internal clock source 11 is phase-shifted based on the detection outputs of the preamble length detection unit 17 and the buffer usage amount detection unit 18. This is a part for controlling and writing the serial data read from the elastic buffer 12 to the smoothing buffer 13 by the clock WC2 of the controlled phase. The data thus written in the smoothing buffer 13 is read out based on the clock RC2 generated from the internal clock source 11 and output from the station as transfer data to the next station.

Hereinafter, the smoothing buffer 1 of the apparatus shown in FIG. 25, particularly by the clock phase controller 19, will be described.
Regarding the control method of No. 3, two conventionally adopted methods are shown, and their control algorithms are listed respectively.

◆ First method (hereinafter, "limit smoother")
(1) (a) In hybrid mode, preamble PA
Is 4 symbols and the usage rate of the smoothing buffer 13 is 5
If it exceeds 0%, or (b) in the hybrid mode, the preamble PA is 6 symbols and the smoothing buffer 13 usage rate is 0% or more, or (c) in the basic mode, the preamble PA is 12 symbols. If the usage rate of the smoothing buffer 13 exceeds 50%, in the (d) basic mode,
If the preamble PA is 14 symbols and the usage rate of the smoothing buffer 13 is 0% or more, the preamble PA is read and discarded, and the start code JK is waited for. (2) In cases other than the above (a) to (d), idle (preamble PA) is output and the start code JK is waited for.

Second method (hereinafter referred to as "target smoother") (1) (a) In hybrid mode, preamble PA
Is 4 symbols and the usage rate of the smoothing buffer 13 is 5
If the preamble PA is 5 symbols or more and the usage rate of the smoothing buffer 13 exceeds 0% in the hybrid mode (b),
In (c) Basic mode, the preamble P
If A is 14 symbols or more and the usage rate of the smoothing buffer 13 exceeds 0%, the preamble PA is read and discarded, and the start code JK is waited for. (2) In cases other than the above (a) to (c), idle (preamble PA) is output and the start code JK is waited for.

These methods have been regarded as the most powerful preamble length adjusting methods in the past.

References relating to these preamble length adjustment methods include the American National Standards Institute (ANSI: Amer).
The following are known from the ican National Standards Institute working paper:

(A) Draft, Proposed, ANS "F
DDI Hybrid Ring Control ", 198
August 12, 1996, pp. 32-38 [DRAFT PROPOSED ANS
"FDDIHYBRID RING CONTROL" (Aug.12,1988) P.32-P.3
8] (B) David Dodds "Jitter Control in FDDI-II SYSTEMS", September 30, 1987 [David Dodds "JITTER CONTROL IN FDDI-II SYSTEMS"
(Sept.30,1987)] (C) David Dodds, "Jitter Control in FDDI-II Systems Progress Report," July 8, 1987 [David Dodds "JITTER CONT
ROL IN FDDI-II SYSTEMS Progress Report "(July 8,19
87)] (D) Working Draft Proposed American National Standard “FDDI Physical
Layer Protocol (PHY-2) ", March 1991
May 5th, pages 19-44 [WORKING DRAFT PROPOSED AME
RICAN NATIONALSTANDARD "FDDI PHYSICAL LAYER PROTOC
OL (PHY-2) "(March 5,1988) P.19-P.44]

[0019]

By the way, in any of the above-mentioned conventional preamble length adjusting methods, it is premised that at least two buffers such as an elastic buffer and a smoothing buffer are used, as is apparent from FIG. Then, the phase shift of the data due to the frequency difference between the stations is first absorbed through the elastic buffer, and the preamble length adjusted to be extremely short or extremely long by the absorption of this phase shift is then corrected through the smoothing buffer. ing.

Therefore, in this method, the smoothing buffer continuously restores the preamble length to its original value, especially when a short preamble data (cycle) arrives at a certain station in the hybrid mode. It is expected that the buffer capacity will be used up in a few cycles. That is, in this case, in the subsequent cycle of the serial data, the serial data must be sent to the next station without any correction. Therefore, when the serial data to be transmitted passes through a number of stations and the above adjustments are duplicated in the same cycle, the preamble length in that cycle becomes shorter and shorter and finally becomes 0 symbol (no preamble). It can happen.
This means that subsequent adjustments can reach the data portion and thus even cause data corruption.

Further, in order to eliminate such inconvenience in the hybrid mode, when the increase / decrease in the length of the preamble PA for the same data (cycle) is overlapped in the same direction in the increasing or decreasing direction, the preamble relating to the data is changed. It is not unthinkable to provide each station with a communication device that realizes a preamble length adjustment control that refrains from increasing or decreasing the length, but this makes it difficult to use the other basic mode.

That is, in the basic mode,
In the first place, the length of the preamble PA is not fixed, and the length of the preamble PA changes significantly even if the smoothing buffer is not controlled by the limit smoother or the target smoother. It is impossible to judge whether or not the increase or decrease of the size is duplicated in the same direction between the previous station and the own station.

For example, if one station transmits data (frame) with a preamble length of 20 symbols and the next station repeats the data by reducing the preamble by one symbol, the next station, that is, A 19-symbol preamble will be received from the original data transmission station to the second station, but at the station that has received this 19-symbol preamble, the original data transmission station actually transmits the number of symbols of the preamble. I can't tell if I was sending.

Therefore, in such a basic mode, even if the above-mentioned preamble length adjustment control is performed, the smoothing buffer may still overflow.

In any case, requiring at least two buffers such as an elastic buffer and a smoothing buffer is uneconomical in terms of equipment,
Further, the configuration and the above-mentioned buffer control are made more complicated.

The present invention has been made in view of the above circumstances, and preferably controls the length of the preamble through only one buffer, whether in the basic mode or the hybrid mode, and is transmitted through the network. It is an object of the present invention to provide an independent synchronous serial data communication device capable of satisfactorily preserving data in any case.

[0027]

In order to achieve such an object, according to the present invention, as an independent synchronous serial data communication device arranged at each connection station to a network, (a) a predetermined serial data transmission device is used. An internal clock source that generates a clock of frequency.

(B) Buffer means for temporarily storing serial data in the FIFO format.

(C) Clock extraction means for extracting the transmission clock from the input serial data.

(D) Write control means for writing the serial data in the buffer means based on the extracted clock.

(E) First detecting means for detecting the amount of data stored in the buffer means each time.

(F) Second detecting means for detecting the length of the preamble included in the input serial data.

(G) The transmitted serial data is in the first communication mode transmitted asynchronously (that is, the basic mode), or the second communication mode transmitted in the synchronous and asynchronous manner (that is, the basic mode). Hybrid mode)
The third detection means for detecting whether or not

(H) When the detection result of the third detection means is the first communication mode, the detection output of the first detection means is based on the detection outputs of the first and second detection means. When the detection output of the second detection means is below the reference value and below the maximum value of the detection range, and when the detection output of the first detection means is below the center predetermined range value of the detection range, the internal clock source is used. When the phase of the generated clock is delayed, the detection output of the first detection means exceeds the center predetermined range value of the detection range, and the detection output of the second detection means is equal to or greater than the reference value, the internal clock source The first clock for advancing the phase of the generated clock, and for controlling the phase of the clock generated from the internal clock source to the standard phase for serial data transmission otherwise. Lock phase control means.

(I) When the detection result of the third detecting means indicates the second communication mode, the detection output of the first detecting means is based on the detection outputs of the first and second detecting means. Is below the center predetermined range value of the detection range and the detection output of the second detecting means is equal to or less than the reference value,
When the phase of the clock generated from the internal clock source is delayed, the detection output of the first detection means exceeds the center predetermined range value of the detection range, and the detection output of the second detection means is greater than or equal to the reference value, Advances the phase of the clock generated from the internal clock source, otherwise,
Second clock phase control means for controlling the phase of the clock generated from the internal clock source to be a standard phase for serial data transmission.

(J) Read control means for reading the data stored in the buffer means as output serial data to the next station based on these phase-controlled clocks.

It is configured to include each.

[0038]

In such a device, first, the third detecting means is used.
By (g), it is detected whether the serial data input to the device is based on the first communication mode, that is, the basic mode or the second communication mode, that is, the hybrid mode. For this detection, for example, the presence or absence of the cycle header CH (see FIG. 22), which is the hybrid mode identifier, can be used.

As a result, when it is detected that the serial data is based on the basic mode, the first clock phase control means (h) is activated, and the first clock phase control means is operated through the first clock phase control means. First detection means
The clock phase control is executed based on the detection output of the buffer means (b) for each data storage amount by (e) and the detection output of the preamble length by the second detection means (f). That is, in this case, when it is determined that the detected buffer usage is smaller than the capacity of the buffer means (b) itself and the detected preamble length is shorter than the specified length, priority is given to preamble length correction. And the amount of buffer usage detected above is 50% of the capacity of the buffer means (b) itself.
Below, only the buffer utilization is a problem,
This is also in the direction of increasing the preamble length, and the detected buffer usage is 50% of the capacity of the buffer means (b) itself.
%, And when the detected preamble length is determined to be equal to or longer than the specified length, the buffer phase is prioritized, and the preamble length is controlled in the clock phase so as to reduce the preamble length. In other controls that maintain the standard phase, the preamble length does not increase or decrease.

When it is detected that the serial data is in the hybrid mode as a result of the detection by the third detecting means (g), the second clock phase controlling means (i) is The second clock phase control means is activated, and the detection output of the data storage amount of each buffer means (b) by the first detection means (e) and the preamble by the second detection means (f) are activated by the second clock phase control means. The above clock phase control based on the detected output for length is performed. That is, in this case, when the detected buffer usage amount is less than about 50% of the capacity of the buffer means (b) itself and the detected preamble length is determined to be the specified length or less, the preamble length is increased. In addition, the detected buffer usage is
(b) When it exceeds about 50% of its own capacity and it is determined that the detected preamble length is equal to or longer than the specified length, the clock phase is controlled to decrease the preamble length. However, when it is determined that the length of the input preamble has been previously adjusted in the same direction (this is included in “other times” in the second clock phase control means (i)). ), Refrain from adjusting the preamble length for the data (cycle),
To the next data, if it is determined that the preamble length adjustment has also been performed on the next data in the same direction,
Further, the adjustment of the preamble length is carried over to the next data.

Thus, according to this device, the basic
A single buffer, in either mode or hybrid mode, makes it possible in any case to have good preservation of the transmitted data.

In the phase control by the first and second clock phase control means (h) and (i), the control for advancing the phase of the clock corresponds to "reduction" of the preamble length, and conversely, the above The control to delay the phase of the clock (that is, put it in the stepping state) is to "increase" the preamble length.
Corresponding to.

In addition to the above configuration, (k) it is determined whether or not the transmitted serial data is predetermined data, and when the result of the determination is negative, at least the write control is performed. Means for deactivating the reading means and the reading control means.

By further comprising, it becomes possible to easily realize optimization of the buffer usage regardless of the presence or absence of received data at each occasion.

Incidentally, the "predefined data defined in advance" includes synchronous data and asynchronous data desired to be transferred, a preamble (PA), a start code (J).
K), etc. correspond to this.

Regarding at least the basic mode, the internal clock source of (a), the buffer means of (b), the clock extracting means of (c), the write control means of (d), and the first of (e) are used. Detection means, (f) second detection means, (
Even with the configuration including only the clock phase control means of (h) and the read control means of (j), it is possible to realize an apparatus for maintaining the serial data transmitted through only one buffer.

[0047]

1 shows an embodiment of an independent synchronous serial data communication device according to the present invention.

Similar to the device shown in FIG. 25, this communication device is also provided in each station (see FIG. 23) connected to the communication network.

First, the structure of this apparatus and the function of each section will be described.

In the device shown in FIG. 1, the internal clock source 21 is a portion for generating a clock signal for determining the operating frequency of the station. This clock frequency is basically set to the same frequency for all stations, but in reality, the accuracy varies due to variations in the components that make up the clock source 21, and between stations it is slightly different. The frequency difference is generated as described above. At present, such frequency deviation can be suppressed to a maximum of about ± 50 ppm.

Further, although the buffer register 22 corresponds to the elastic buffer 12 in the conventional device (FIG. 25), the smoothing buffer 13 in the same device is used.
Like the buffers 12 and 13, the serial data input to the authority is temporarily stored in a FIFO format. Figure 2
An example of the buffer register 22 is shown in FIG.

Incidentally, in FIG. 2, the buffer register 22 is configured to have three registers A, B, and C for reading / writing data in units of symbols (5 bits). Each of these registers stores input data based on each corresponding clock of a write clock WC (WCA, WCB, WCC) provided from a write clock distribution unit 24 described below, and provides it from a read clock distribution unit 25. Read clock RC
These stored data are output based on the corresponding clocks (RCA, RCB, RCC).

Further, in this apparatus (FIG. 1), the clock extraction section 23 is a section for extracting and reproducing the transmission clock from serial data input to the authority by a well-known PLL (phase locked loop) or the like, The write clock distribution unit 24 is a unit that generates a write clock WC based on the extracted clock and writes the serial data in the buffer register 22. FIG. 3 shows an example of the write clock distribution unit 24 corresponding to the buffer register configuration shown in FIG.

The write clock distributor 2 shown in FIG.
4, the transmission clock extracted and reproduced is W
It becomes possible to sequentially sort in the order of CA->WCB->WCC-> WCA .... In FIG. 3, DFF is D
Shows a type flip-flop.

In the same device (FIG. 1), the read clock distributor 25 generates the read clock RC based on the clock generated from the internal clock source 21, and the read clock RC is stored in the buffer register 22. This is a part for reading data as output serial data to the next station. However, when generating the read clock RC, a control signal (S0, S1) from a clock phase control unit 28, which will be described later, is referred to, and the clock whose phase is controlled according to the control content is read clock RC. Generate as. FIG. 4 shows an example of the read clock distribution unit 25 corresponding to the buffer register configuration also shown in FIG.

That is, this read clock distributor 25
Are read clocks RC (RCA, RCB, RCC) in the modes listed in FIG. 5 based on the contents of the control signals S0, S1 given from the clock phase controller 28.
Are distributed and generated. For example, the control signal S0 = L
When the "normal shift" operation is instructed based on (logic low level) and S1 = H (logic high level), each read clock is changed to "RCA-> RCC, RCB->".
In the case of outputting in the form of RCA, RCC-> RCB ", when the" read skip "operation is instructed under the control signals S0 = H, S1 = H, this read clock is RCA-> RCB, RCB-> RCC, RC
In the mode such as "C->RCA", the data is output after being shifted in the opposite direction, and when the "double reading" operation is instructed under the control signals S0 = L and S1 = L, "RCA- > RCA,
RCB-> RCB, RCC-> RCC ",
This read clock is set in the stepping state. FIG. 6 generally shows the operation of the write clock distribution unit 24 and the operation of the read clock distribution unit 25 including the buffering contents of the buffer register 22 based on the operation.

For example, suppose that the input data is written to the buffer register 22 through the write clock distribution unit 24 in the mode shown in FIG. 6 (a). Through the above-described normal shift operation (see FIG. 5) by the read clock distribution unit 25, the written content is output from the buffer register 22 in the form shown in FIG. 6B as it is. When the reading skip of the data symbol is instructed through the clock phase control section 28 or the double reading of the data symbol is instructed, the above-described reverse shift or stepping operation by the read clock distribution section 25 is performed. As shown in FIG. 6 (c), the buffered data is transmitted through (see FIG. 5). Skip symbol (to advance the phase), or 2 rereading each record (delaying the phase) is performed. That is, the data symbol length can be adjusted through the series of operations of the write clock distribution unit 24, the buffer register 22, and the read clock distribution unit 25. Incidentally, the target of this embodiment is the length of the preamble PA, the skip of reading the data symbols corresponds to the reduction of the preamble length, and the double reading of the data symbols increases the preamble length. Equivalent to that.

Further, in the apparatus of this embodiment (FIG. 1),
The buffer usage amount detector 26 uses the buffer register 2
2 is a portion for detecting the amount of data written in 2, that is, the buffer usage amount B of the same buffer register 22 each time. The buffer usage amount B is detected, for example, by detecting the phase difference between the write clock WC and the read clock RC for the buffer register 22 and encoding the start code JK when it is detected from the input serial data. It will be realized. In Figure 7,
An example of the buffer usage amount detector 26 is shown.

Incidentally, in FIG. 7, RCA, RC
B and RCC are the read clock distributor 2 respectively.
5 is a read clock of the buffer register 22 output from the signal No. 5, and a signal JKDT is a detection signal of the start code JK by the preamble length detection unit 27 described below.

In the same apparatus (FIG. 1), the preamble length detection unit 27 is a part for detecting the length of the preamble PA included in the data from the serial data input to the authority. The detection of the preamble length is realized, for example, by first detecting the start point of the preamble PA in the same serial data and counting the number of constituent symbols (the number of bits) with a counter. In FIG.
An example of such a preamble length detection unit 27 is shown.

That is, in FIG. 8, the signal MODE is
This is a communication mode instruction signal given from a mode control unit 29 which will be described later, and as shown in the figure, when the communication mode is the basic mode, the logic level of this signal MODE is "L (Low ) Level ”, and in the hybrid mode, the logic level of the signal MODE becomes“ H (High) level ”. Therefore, in the basic mode, the preamble (idle) of the input data detected by the preamble detection circuit 271 is directly counted by the counter 272, but in the hybrid mode, the preamble included in the input data (cycle) is included. For (idle), the count by the counter 272 is masked. The cycle length counter 273 is a logical level of its output during the counting period of 3120 symbols (see FIG. 22) corresponding to the cycle length of the hybrid mode data after the start code JK of the input data is detected. It is a circuit to hold. In addition, the above start code JK of the input data
Is detected by a JK detection circuit 274 which is a dedicated detection circuit, and the detection signal JKDT is detected by the counter 272.
And given to the cycle length counter 273,
It is given to the buffer usage amount detecting unit 26 which is an external circuit thereof. The start code detection signal JKDT is
It acts as a disable (inactive) signal to the counter 272.

Further, in the same apparatus (FIG. 1), the clock phase control unit 28 is responsive to a predetermined preamble length adjustment algorithm on the basis of the detection outputs from the buffer usage amount detection unit 26 and the preamble length detection unit 27 to generate the internal clock source. 21 is a part for executing control for advancing, delaying, or maintaining the phase of the clock generated from 21. As described above, the control signals S0 and S1 are given to the read clock distribution unit 25, and the read clock RC is generated through the read clock distribution unit 25 according to the control content of the control signals S0 and S1. On the street.

The mode determination unit 29 is a unit for detecting and determining whether the input serial data is in the basic mode or the hybrid mode. To detect such a communication mode, for example, it is possible to use whether or not the cycle header CH, which is the identifier for the hybrid mode shown in FIG. 22, is included in the serial data. When the mode determining unit 29 detects and determines the communication mode from the input data in this way, it outputs a signal MODE indicating whether the communication mode is the basic mode or the hybrid mode to the preamble length detecting unit 27 and the preamble length detecting unit 27. It outputs to each of the clock phase control units 28. Incidentally, in this example, the signal MODE becomes “L level” at the logical level when the communication mode is the basic mode, as described in FIG. 8 above.
In the hybrid mode, the logic level is "H level".

Next, the preamble length adjustment control executed in the clock phase control unit 28 based on the detection determination of the communication mode by the mode determination unit 29 will be described with reference to FIGS. The control algorithm will be described in detail.

First, in this embodiment, the (A) buffer register 22 has three buffers A to C for reading and writing the input serial data in units of 1 symbol (5 bits), as illustrated in FIG. Composed of a register.

(B) In the basic mode, the length of the reference preamble PA (hereinafter referred to as PA including this length for convenience) is set to 12 symbols.

(C) In the hybrid mode, the reference value of the preamble length PA is 5 symbols as described above, and the preamble length PA is adjusted within the range of 4≤PA≤6.

It is assumed that In this case, "0" of the buffer is the center of the buffer, and its "+" direction is considered as the output phase delay.

Under the above assumption, the length of the preamble input to the buffer register 22, that is, the preamble length detected by the preamble length detecting unit 27 is PAi, and the preamble adjusted by this device with respect to this preamble length PAi. PA is the length, that is, the length of the preamble actually output from the buffer register 22, and B is the buffer usage amount of each buffer register 22, that is, the buffer usage amount detected by the buffer usage amount detection unit 26. When the capacity of the buffer register 22 itself is C, the clock phase controller 28 reads the values generated by the read clock distributor 25 in the manner shown in FIG. 9 based on the obtained values. It controls the phase of the clock RC, and To adjust the tumble length PA.

That is, suppose now that the serial data is input to the authority, and it is determined that the communication mode is the basic mode as a result of the mode detection and determination by the mode determination unit 29 (FIG. 9, step ST1). In accordance with the signal MODE (= logical L level) indicating that, the clock phase control unit 28 executes the preprogrammed clock phase control in the modes listed below.

(1) First, looking at the buffer usage amount B detected by the buffer usage amount detection unit 26, this is "B <
0 ”(step ST10 in FIG. 9), the preamble length PAi detected by the preamble length detection unit 27
For the control signals S0 and S1
Are both set to "L level", and control is performed to increase the preamble length by one (step ST11 in FIG. 9). That is, "P
A = PAi + 1 ”. This corresponds to the double reading of the data described above (see FIG. 5).

(2) If the buffer usage amount B is "B = 0" instead of "B <0" (step ST12 in FIG. 9),
With reference to the preamble length PAi detected by the preamble length detection unit 27, this is “PAi <12”.
If the condition is not satisfied (step ST1 in FIG. 9).
3), control signal S0 to "L level", and control signal S
1 is set to "H level", and control for maintaining the preamble length is performed (step ST14 in FIG. 9). That is, "PA
= PAi ". This corresponds to the normal shift operation described above (see FIG. 5).

(3) Also, the buffer usage B is "B =
When it is "0", the detected preamble length PA
If i satisfies the condition "PAi <12", both control signals S0 and S1 are set to "L" as in the above (1).
As the "level", control is performed to increase the preamble length by one (step ST11 in FIG. 9).

(4) If the buffer usage B is neither "B <0" nor "B = 0", the preamble length PAi is "P".
On condition that Ai ≧ 12 ”(step S1 in FIG. 9).
5) Then, the control signals S0 and S1 are both set to "H level", and control is performed to reduce the preamble length by one (step ST16 in FIG. 9). That is, "PA = PAi-1". This corresponds to the skip of reading the data described above (see FIG. 5).

(5) When the buffer usage B is neither "B <0" nor "B = 0", this preamble length PAi
If the condition that “PAi ≧ 12” cannot be satisfied, the control signal S0 is set to “L level” as in (2) above.
Further, the control signal S1 is set to "H level" to perform control for maintaining the preamble length (step ST14 in FIG. 9).

The contents of the preamble length adjustment in this manner by the clock phase controller 28 are listed as a table in FIG.

In this basic mode, in particular, the condition "B <0" or the condition "B>0" for the buffer usage B does not exceed the capacity C of the buffer register 22 itself. It is set in the range. Therefore, the preamble length adjustment algorithm in the basic mode by the clock phase controller 28 is summarized as follows: (a) When PAi <12 and B <C (+ C), PA = PAi + 1 is adjusted. (b) When B <0, adjust PA = PAi + 1. (c) When PAi ≧ 12 and B> 0, PA = PAi−1 is adjusted. (d) In cases other than these (a) to (c), PA = PAi. It becomes a mode like this.

On the other hand, when the serial data is input to the authority and the result of the mode detection and judgment by the mode judgment unit 29 is that the communication mode is the hybrid mode,
If the determination is made (step ST1 in FIG. 9), the clock phase control unit 28 executes the preprogrammed clock phase control in the modes listed below in accordance with the signal MODE (= logical H level) indicating that fact. ..

(1) First, looking at the buffer usage amount B detected by the buffer usage amount detection unit 26, this is "B =
0 ”(step ST20 in FIG. 9), the preamble length PAi detected by the preamble length detection unit 27 is detected.
In regard to the above, without looking at this, the control signal S0 is set to "L level" and the control signal S1 is set to "H level" to perform control for maintaining the preamble length (step ST in FIG.
21). That is, “PA = PAi”. This corresponds to a normal shift operation (see FIG. 5).

(2) If the buffer usage B is "B <0" instead of "B = 0" (step ST22 in FIG. 9),
With reference to the preamble length PAi detected by the preamble length detection unit 27, the preamble length PAi does not satisfy “PAi ≧ 6” (step ST2 in FIG. 9).
3) Then, the control signals S0 and S1 are both set to "L level" to perform control to increase the preamble length by one (step ST24 in FIG. 9). That is, “PA = PAi + 1”. This corresponds to reading the data twice (see FIG. 5).

(3) Also, the buffer usage B is "B <
When it is "0", the detected preamble length PA
When i satisfies the condition of “PAi ≧ 6”, the preamble length is maintained by setting the control signal S0 to “L level” and the control signal S1 to “H level” as in the above (1). Control is performed (step ST21 in FIG. 9).

(4) If the buffer usage B is neither "B = 0" nor "B <0", the preamble length PAi is "P".
On condition that Ai ≦ 4 ”is not satisfied (step S2 in FIG. 9).
5) Then, the control signals S0 and S1 are both set to "H level", and control is performed to reduce the preamble length by one (step ST26 in FIG. 9). That is, "PA = PAi-1". This corresponds to skipping the reading of data (see FIG. 5).

(5) When the buffer usage B is neither "B = 0" nor "B <0", this preamble length PAi
When the condition that “PAi ≦ 4” is satisfied, the preamble length is also set by setting the control signal S0 to “L level” and the control signal S1 to “H level” as in (1) above. Control to maintain is performed (step ST21 in FIG. 9).

FIG. 11 is a table showing the contents of the preamble length adjustment by the clock phase controller 28 in this manner.

The preamble length adjustment algorithm in the hybrid mode by the clock phase controller 28 is summarized as follows: (a) PA = PAi when -1≤B≤ + 1. (b) When B <−1, if PAi ≦ 5, PA = PAi + 1, and if PAi = 6, PA = PAi (carry forward to the next cycle without adjustment).

(C) When B> +1, if PAi ≧ 5, PA = PAi−1. If PAi = 4, PA = PAi (carry forward to the next cycle without adjustment).

The above-mentioned mode is adopted.

FIG. 12 shows the transition of the preamble length PA adjusted based on the operation in each of these stations, particularly in the hybrid mode, assuming three consecutive stations in which the apparatus of such an embodiment is arranged. Corresponding to the buffer amount B at each time.

As shown in FIG. 12, the preamble length P adjusted by the first station based on the above algorithm.
A (see FIG. 12 (a)) is taken over as the input preamble length PAi to the second station for each cycle (frame), and this second station is further subjected to adjustment based on the above algorithm. However, as shown by adding "* 2" mark (corresponding to "* 2" mark in FIG. 11) in FIG. 12 (b), the buffer amount B exceeds the upper limit threshold, and In this embodiment, where the adjustment should be made from “4 symbols” to “3 symbols”, the data (cycle) of the relevant data is recognized based on the knowledge that “before that, adjustment is also made in the same reduction direction”. It becomes possible to refrain from further reduction adjustment for the preamble length. Then, the preamble length reduction adjustment is performed on the next data (cycle) satisfying the condition that the buffer amount B exceeds the upper limit threshold and the input preamble length PAi is not adjusted in the direction to be reduced before that. It will be carried over. Therefore, the preamble length is unnecessarily short (for example, 3 symbols or less),
Alternatively, it is extremely unlikely to be adjusted for a long time (for example, 7 symbols or more). Of course, if the preamble length is not adjusted shorter than necessary, there is no concern that the above-mentioned data destruction will occur.

In FIG. 12, the buffer amount B
The transition angle θ of the line showing the transition of corresponds to the frequency difference with the station at the preceding stage (frequency difference of the clock generated from each internal clock source), and the smaller this angle θ, the more The smaller the frequency difference and the larger the angle θ,
The frequency difference between these stations is large. Incidentally, FIG. 12C in which the angle θ is in the negative direction indicates that the frequency of the third station is higher than the frequency of the second station. Also, m1 and m added to each of the lines showing the transition of the buffer amount
2 and m3 indicate the buffer consumption per cycle due to the frequency difference between the stations.

Even when these stations operate in the basic mode, the detected preamble length PAi is longer than the specified length (12 symbols in this example) by the preamble length adjustment algorithm. In this case, the usage rate of the buffer register 22 is prioritized, and the preamble length PA is adjusted so that the usage rate approaches 50%. That is, in this case, the preamble (idle) is actively discarded. When the detected preamble length PAi is shorter than the specified length, the usage rate of the buffer register 22 is brought close to 50% as much as possible within the range while giving priority to the correction of the preamble length. That is, in this case, the rate of discarding the preamble (idle) is reduced as much as possible. Since such control is basically executed, overflow or underflow of the buffer register 22 is extremely unlikely to occur.

Thus, according to the apparatus of this embodiment,
Regardless of the data structure that is different in these communication modes, whether in the basic mode or the hybrid mode, the data can be transmitted / received satisfactorily through only one buffer, that is, the buffer register 22, and the resistance to data destruction, etc. Compared with the conventional device, it is remarkably improved.

In the above embodiment, as described above, the (A) buffer register 22 reads / writes input serial data in units of 1 symbol (5 bits), as illustrated in FIG. It is configured by including three registers C to C.

(B) In the basic mode, the length of the reference preamble PA (hereinafter referred to as PA including this length for convenience) is set to 12 symbols.

(C) In the hybrid mode, the reference value of the preamble length PA is 5 symbols as described above, and the preamble length PA is adjusted within the range of 4≤PA≤6.

However, the number of symbols or the number of bits defined as the reference value of these preamble lengths,
The setting of the adjustment range of the preamble length, the buffer capacity of the buffer to be used, and the threshold for performing the adjustment of the preamble length, etc. are not limited to this, and are applied to the network or applied. It can be arbitrarily set according to the actual situation of the station.

Further, the device itself illustrated in FIG. 1 may have any implementation method, and may be implemented by hardware.
Alternatively, as long as the above-mentioned functions of the respective parts are basically satisfied, even if it is software, as shown in FIG.
-It is not limited to the example shown in FIG. 4, FIG. 7, or FIG. 8, and this may be realized in any way.

Further, in the device as shown in FIG. 1, normally, when there is no data received from another station, or when, for example, the test data is sent from the own station to the network and the data fed back is sent. If there is no data reception in the so-called loopback mode such as analysis, clock recovery cannot be performed by the clock extraction unit 23. Therefore, during that time, the frame may be written to the buffer register 22 through the write clock distribution unit 24. Can not.

A saw-tooth wave filter (Saw Filter) is often used for clock reproduction.
In that case, noise is output as the recovered clock when no data is received. This causes the write clock distribution unit 24 to run out of control.

After that, even if the data is received and the frame is normally written to the buffer register 22, it is impossible to properly control the buffer usage of the buffer register 22 until then. Therefore, in some cases, it may not be possible to read this frame normally. That is, the buffer register 22 may become empty while reading a frame.

Although there are concerns about such problems, in such a case, by adopting the structure shown in FIG. 13 as the communication device, it becomes possible to avoid such inconvenience very easily. ..

That is, in the apparatus shown in FIG. 13, the data judging section 30 is a section for judging whether or not the data inputted each time is the prescribed data defined in advance, and the data is the prescribed data. When judged, the write clock distribution unit 24, the read clock distribution unit 25, and the clock phase control unit 28 are enabled (active).
Operates to assert the signal CNTENBL. In other words, the data determination unit 30 is configured such that the write clock distribution unit 24, the read clock distribution unit 25, and the clock phase control unit 2 while the specified data is not input.
Controls 8 inactive.

Here, as the above-mentioned prescribed data, for example, "FDDI-II" introduced above is used.
In the communication standard defined as, the following symbols included in the transmitted serial data are listed.

◇ J symbol ("11100"): Starting delimiter (forming start code together with K symbol) ◇ K symbol ("10011"): Starting delimiter (forming start code together with J symbol) ◇ I symbol (" 10111 "): Idle (preamble) ◇ H symbol (" 10100 "): Holt symbol (symbol for confirming logical connection on network) ◇ R symbol (" 11001 "): Reset symbol (symbol for confirming data transfer) ) ◇ S symbol ("10001"): Set symbol (symbol for confirmation of data transfer) ◇ T symbol ("11101"): Ending delimiter (forming stop code) ◇ n symbol ("0xxxx"): Data symbol By the way, The J symbol to T symbol are data symbols. "Control symbol" for the n symbol is
Sometimes also collectively referred to.

If each such symbol is defined in advance as the above-mentioned prescribed data, the data judgment unit 30
Then, for example, based on the following algorithm, determine whether the input data is these specified data,
The state of the enable signal CNTENBL is determined.

IfDATA = (J # K # I # H # R # S # T # n) Then CNTENBL = “1” Else CNTENBL = “0” Incidentally, this is because the input data is J symbol or K symbol, Alternatively, if the I symbol, the H symbol, the R symbol, the S symbol, the T symbol, or the n symbol, the signal CNTENBL is set to a logical “1 (High) level”, and otherwise.
The signal CNTENBL is set to the logic "0 (Low) level". Of course, this can also be configured as hardware by combining well-known logic circuits.

Specific examples of the write clock distribution unit 24 and the read clock distribution unit 25 in the case where the structure shown in FIG. 13 is adopted are shown in FIGS. 3 and 4, respectively. 14 and FIG.

Particularly, in the read clock distribution section 25, as shown in FIG.
In addition to its active / inactive control by BL, its configuration is changed so that in response to assertion of the signal CNTENBL, the distribution clock RCB is sequentially output. This is because the write clock distribution unit 24 outputs the distribution clock W by asserting the signal CNTENBL.
This is a consideration for setting the buffer usage amount in the buffer register 22 to “1” in the relationship of sequentially outputting from CA.

In the read clock distribution unit 25,
FIG. 1 illustrates state transitions based on the signal CNTENBL.
It becomes like 6.

That is, the signal CNTENBL changes to logic "L".
From the reset state RST in "level", the same signal CNT
The first read control state R by asserting ENBL
It becomes D1, and at the timing of the next reproduction clock, it becomes the second read control state RD2 corresponding to the read control in the normal communication state. That is, when the first read control state RD1 is reached, the distribution clock RCB is started to be output, and thereafter RCC->RCA->RCB-> RCC.
The generated read distribution clocks are output in this order. Incidentally, these first and second
In any of the read control states RD1 and RD2, when the signal CNTENBL becomes the logic "L level", the reset state RST is again set, and all the distribution clocks (RCA, RCB, RCC) are output. Stop.

FIG. 17 is a table summarizing the operation characteristics of the read clock distribution unit 25. The columns of RST, RD1 and RD2 in FIG. 17 are the reset state and the first read, respectively. This corresponds to the state of each distributed clock (RCA, RCB, RCC) in the control state and the second read control state.

FIG. 18 shows the signal CN of the write clock distributor 24 and the read clock distributor 25.
The operation timing based on TENBL is summarized as a timing chart. Note that in FIG. 18, for the sake of convenience, it is assumed that the data is received in the loopback mode described above, and the clock generated from the internal clock source 21 and the clock extracted and reproduced by the clock extraction unit 23 are the same. Are assumed to have frequencies.

Further, FIG. 19 shows the state transition of the clock phase control unit 28 when the configuration shown in FIG. 13 is adopted.

That is, as shown in FIG. 19, the clock phase control unit 28 is in a communicable state by asserting the signal CNTENBL from the reset state RST in which the signal CNTENBL is at the logic "L level" (on the network). Logical connection status of) HISYMBL
Then, at the timing when the start code (JK symbol) is detected, the normal communication state FRAME / C
Transition to YCLE. And this normal communication state FR
In AME / CYCLE, the above signal CNTENBL
Is reset to the logic "L level" immediately, the reset state RST
When the H symbol (holt symbol) is received, the communicable state becomes HISYMBL again, and if the start code (JK symbol) is detected, the communication state changes to FRAME / CYCLE, and the signal CNT
If ENBL becomes logic "L level", reset state RS
Move to T.

Moreover, in the clock phase controller 28,
When the communication-enabled state HISYMBL is set, the buffer register 22 overflows from the buffer usage amount B of the buffer register 22 detected by the buffer usage amount detection unit 26 based on the algorithm shown in FIG. The contents of the control signals S0 and S1 are set and controlled so that underflow does not occur. Also in FIG. 20, the contents of these control signals “S0, S1 = LH” mean a normal shift operation, and “S0, S1 = LL” means a double reading (stepping) operation of the buffer storage content, And "S0, S
The fact that "1 = HH" means a read (reverse shift) operation for reading the stored contents of the same buffer is the same as before. After that, after shifting to the normal communication state FRAME / CYCLE based on the detection of the start code (JK symbol), based on the determination result of the basic mode or the hybrid mode by the mode determination unit 29, The preamble length adjustment control in the mode shown in FIG.

According to the configuration described above, even if the received data does not arrive, the buffer register 22
It is possible to always maintain the state of (4) in an appropriate state.
Moreover, as a configuration therefor, it can be basically realized by a very simple configuration as shown in FIG. 13 (although the background is different, for example, Japanese Patent Laid-Open No. 3-66239, the title of the invention is “ Compared with the device described in "Slip control circuit of elastic store", its configuration and operational effect are enormous).

In the above example, the data judging section 30
The content of the serial data is judged directly from the input serial data. However, for example, a serial / parallel converter for converting the serial data into parallel data is provided in the preceding stage of the data judging section 30 and the data is converted. It may be configured such that the determination by the above algorithm is executed based on the parallel data.

Further, at least the write clock distribution unit 24 and the read clock distribution unit 25 are controlled by the data judging unit 30 so that their operation states are controlled, so that the minimum buffer usage amount of the buffer register 22 can be reduced. Can be optimized.

[0119]

As described above, according to the present invention, in the basic mode, when the length of the input preamble is longer than the specified length, the buffer usage rate is prioritized to 50%. If the preamble length is shorter than the specified length, the preamble length is prioritized for correction, and the buffer usage rate approaches 50% within that range.
The preamble is increased or the ratio is reduced even if the preamble is read out. In the hybrid mode, it is adjusted in the same direction to increase or decrease the length of the input preamble. If it is determined that the preamble length for the relevant data (cycle) is not adjusted, the next data,
If it is determined that the preamble length has been adjusted in the same direction for the next data as well, to the next data,
Since the adjustment of the preamble length is carried over so that the adjustment of the preamble length for the same data is not duplicated, in any of these communication modes, the overflow and underflow as well as the data are passed through only one buffer. Stable serial data transmission without any damage will be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an independent synchronous serial data communication device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration example of a buffer register shown in FIG.

FIG. 3 is a block diagram showing a specific configuration example of a write clock distribution unit shown in FIG.

FIG. 4 is a block diagram showing a specific configuration example of the read clock distribution unit shown in FIG.

5 is a table showing operation characteristics of the read clock distribution unit shown in FIG.

FIG. 6 is a timing chart showing an operation example of the buffer register, the write clock distribution unit, and the read clock distribution unit shown in FIGS.

FIG. 7 is a block diagram showing a specific configuration example of a buffer usage amount detection unit shown in FIG. 1.

8 is a block diagram illustrating a specific configuration example of a preamble length detection unit illustrated in FIG.

9 is a flowchart showing the adjustment procedure of the preamble length adjustment algorithm executed by the clock phase controller shown in FIG.

FIG. 10 is a chart showing a list of preamble length adjustment modes by the same clock phase control unit when the communication mode is the basic mode.

FIG. 11 is a table listing preamble length adjustment modes by the same clock phase control unit when the communication mode is a hybrid mode.

FIG. 12 is a time chart showing a transition of preamble length adjustment among three consecutive stations when the device shown in FIG. 1 is applied to each connecting station to the network, particularly in the case of communication in a hybrid mode as an example. It is a chart.

FIG. 13 is a block diagram showing another embodiment of the independent synchronous serial data communication device according to the present invention.

FIG. 14 is a block diagram showing a specific configuration example of a write clock distribution unit in the embodiment shown in FIG.

FIG. 15 is a block diagram showing a specific configuration example of a read clock distribution unit in the embodiment shown in FIG.

16 is a state transition diagram showing an example of state transition based on a signal CNTENBL in the read clock distribution unit shown in FIG.

FIG. 17 is a table showing operation characteristics of the read clock distribution unit shown in FIG.

18 is a write clock distribution unit shown in FIG.
16 is a timing chart showing an operation example of the read clock distribution unit shown in FIG. 15 based on a signal CNTENBL.

FIG. 19 is a state transition diagram showing an example of state transition based on a signal CNTENBL in the clock phase controller in the embodiment shown in FIG.

FIG. 20 is a flowchart showing a buffer control algorithm of the clock phase control unit, particularly in a communicable state.

FIG. 21 is a schematic diagram showing an example of the structure of serial data (frame) in the basic mode.

FIG. 22 is a schematic diagram showing an example of a serial data (cycle) structure in a hybrid mode.

FIG. 23 is a block diagram illustrating an actual situation where the station frequencies of the stations do not completely match in a communication network in which the stations operate independently.

FIG. 24 is a time chart exemplifying that a phase shift occurs in transmission serial data between stations due to the station frequencies that do not match.

FIG. 25 is a block diagram showing a configuration example of a conventional independent synchronous serial data communication device.

[Explanation of symbols]

1 to n ... Communication station, 21 ... Internal clock source, 22 ... Buffer register, 23 ... Clock extraction unit, 24 ... Write clock distribution unit, 25 ... Read clock distribution unit, 26 ...
Buffer usage detector 27, preamble length detector,
28 ... Clock phase control unit, 29 ... Mode determination unit, 30
... Data judgment section

Claims (3)

[Claims] 1. An internal clock source for generating a clock of a predetermined frequency for serial data transmission, a buffer means for temporarily storing serial data in a FIFO format, and a clock for extracting the transmission clock from input serial data. Extraction means, write control means for writing the serial data into the buffer means based on the extracted clock, and first data detection amount for each of the buffer means
Detecting means, second detecting means for detecting the length of a preamble included in the input serial data, and whether the transmitted serial data is in a first communication mode in which it is asynchronously transmitted. , A third detection means for detecting whether the second communication mode is transmitted synchronously or asynchronously, and the detection result by the third detection means is the first communication mode, the first detection means And when the detection output of the first detection means is below the maximum value of its detection range and the detection output of the second detection means is below the reference value based on the detection output by the second detection means, and the first detection When the detection output of the means falls below the center predetermined range value of the detection range, the phase of the clock generated from the internal clock source is delayed, and the detection output of the first detection means exceeds the center predetermined range value of the detection range. And the detection output of the second detecting means is equal to or greater than the reference value, the phase of the clock generated from the internal clock source is advanced, and otherwise, the phase of the clock generated from the internal clock source is increased. First clock phase control means for controlling to maintain the standard phase for serial data transmission, and when the detection result by the third detection means indicates the second communication mode, the first and second When the detection output of the first detection means is below the center predetermined range value of the detection range and the detection output of the second detection means is less than or equal to the reference value based on the detection output by the detection means of The phase of the generated clock is delayed, the detection output of the first detection means exceeds the center predetermined range value of the detection range, and the detection output of the second detection means is the reference value or more. In this case, the phase of the clock generated from the internal clock source is advanced, and at other times, control is performed to maintain the phase of the clock generated from the internal clock source at the standard phase for serial data transmission. An independent synchronous serial device comprising: second clock phase control means; and read control means for reading out data stored in the buffer means as output serial data to the next station based on these phase-controlled clocks. Data communication device. 2. The independent synchronous serial data communication device according to claim 1, wherein it is determined whether or not the serial data to be transmitted is defined data defined in advance, and when the determination result is a negative determination, An independent synchronous serial data communication device further comprising at least a data judgment means for deactivating the write control means and the read control means. 3. An internal clock source for generating a clock of a predetermined frequency for serial data transmission, buffer means for temporarily storing serial data transmitted asynchronously in a FIFO format, and input serial data A clock extraction unit that extracts a transmission clock, a write control unit that writes the serial data into the buffer unit based on the extracted clock, and a first data detection amount for each of the buffer units.
Detecting means, second detecting means for detecting the length of the preamble included in the input serial data, and detection outputs from the first and second detecting means,
When the detection output of the first detection means is below the maximum value of the detection range and the detection output of the second detection means is below the reference value, and when the detection output of the first detection means is the center of the detection range When it is below the value, the phase of the clock generated from the internal clock source is delayed, the detection output of the first detection means exceeds the center predetermined range value of the detection range, and the detection output of the second detection means is the reference value. When the above is the case, the phase of the clock generated from the internal clock source is advanced, and at other times, control for maintaining the phase of the clock generated from the internal clock source at the standard phase for serial data transmission is performed. Clock phase control means for performing, and based on this phase-controlled clock, the data stored in the buffer means as output serial data to the next station. An independent synchronous serial data communication device comprising: read control means for reading.