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JPH05218564A - Manufacture of light semiconductor element - Google Patents

Manufacture of light semiconductor element

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Publication number
JPH05218564A
JPH05218564A JP1606592A JP1606592A JPH05218564A JP H05218564 A JPH05218564 A JP H05218564A JP 1606592 A JP1606592 A JP 1606592A JP 1606592 A JP1606592 A JP 1606592A JP H05218564 A JPH05218564 A JP H05218564A
Authority
JP
Japan
Prior art keywords
layer
active layer
current block
selective growth
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1606592A
Other languages
Japanese (ja)
Inventor
Takahiro Nakamura
隆宏 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1606592A priority Critical patent/JPH05218564A/en
Publication of JPH05218564A publication Critical patent/JPH05218564A/en
Pending legal-status Critical Current

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To provide the method of collective growth/process for manufacturing a current block layer and an active layer by selective growth so as to get a light semiconductor element being a large-area wafer and excellent in uniformity and reproducibility. CONSTITUTION:In the first place, a pair of current block layers are manufactured by MOVPE selective growth, and then only the SiO2 film 21 between the current block layers is removed to make an n-InP clad layer 4, an active layer 5, a p-InP clad layer 6, and a p-InGaAs cap layer 7. Hereby, a light semiconductor element of large area and highly uniform can be gotten since the light semiconductor is not etched. Moreover, a high-performance element can be materialized since the current block layer is made.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、光通信,光情報処理な
どに用いられる、光半導体素子の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an optical semiconductor device used for optical communication, optical information processing and the like.

【0002】[0002]

【従来の技術】光通信や光情報処理に用いられる半導体
レーザには、より一層の高性能化が必要になってきてい
る。一方で加入者系光通信用などの需要が多く、低価格
が要求される用途に対応するためには、歩留まりの高い
素子を大面積ウェハを用いて作製する必要がある。こう
した要求を満たすためには、大面積高均一成長が可能な
有機金属気相成長法(MOVPE)などの気相成長法に
より結晶成長を行うことが必要である。また、気相成長
を用いれば、低しきい値,高効率動作,狭スペクトル線
幅動作など数々の特徴を有する量子井戸半導体レーザの
作製も可能である。図3,図4にMOVPEを用いた光
通信用半導体レーザの典型的な製造方法を示す。ここで
は単一モード動作する分布帰還型(DFB)レーザであ
り、埋め込みリッジ構造により電流狭窄を行っている。
まず、n型インジウム・リン(InP)基板1上にグレ
ーティングを形成した後、n型インジウム・ガリウム・
砒素・燐(InGaAsP)ガイド層8、InGaAs
P活性層5、p型InPクラッド層6を積層し(図3
(a))、次にSiO2 膜21を幅2μmのストライプ
状に形成し(図3(b))、基板1に達するまでメサエ
ッチングを行う(図3(c))。その後、全面にp型I
nP層2、p+ 型InGaAsPキャップ層7を成長し
(図4(d))、活性層の周囲にプロトンを打ち込んだ
高抵抗領域31を形成するなどして電流を狭窄している
(図4(e))。
2. Description of the Related Art Semiconductor lasers used for optical communication and optical information processing are required to have higher performance. On the other hand, in order to meet the demands for optical communication for subscribers and the demands for low cost, it is necessary to fabricate high yield devices using large area wafers. In order to meet these requirements, it is necessary to perform crystal growth by a vapor phase growth method such as a metal organic vapor phase epitaxy method (MOVPE) capable of high-area and uniform growth. Further, by using vapor phase growth, it is possible to fabricate a quantum well semiconductor laser having various characteristics such as low threshold, high efficiency operation, and narrow spectral line width operation. 3 and 4 show a typical method of manufacturing a semiconductor laser for optical communication using MOVPE. Here, it is a distributed feedback (DFB) laser that operates in a single mode, and current confinement is performed by a buried ridge structure.
First, after forming a grating on the n-type indium phosphorus (InP) substrate 1, n-type indium gallium
Arsenic / phosphorus (InGaAsP) guide layer 8, InGaAs
The P active layer 5 and the p-type InP clad layer 6 are laminated (see FIG.
(A)) Next, the SiO 2 film 21 is formed in a stripe shape having a width of 2 μm (FIG. 3B), and mesa etching is performed until the substrate 1 is reached (FIG. 3C). After that, p-type I on the entire surface
The nP layer 2 and the p + -type InGaAsP cap layer 7 are grown (FIG. 4D), and the high resistance region 31 in which protons are implanted is formed around the active layer to confine the current (FIG. 4). (E)).

【0003】[0003]

【発明が解決しようとする課題】このように多数の半導
体レーザを製造するためには、大面積のウェハを用い
て、しかも層構造を精密に制御することが重要である。
層厚はMOVPEなどの気相成長法を用いれば十分に制
御が可能であるが、導波路幅は従来SiO2 などをマス
クとして用いたメサエッチングにより制御しており、サ
イドエッチングなどにより十分な制御性が得られないな
どの問題があった。例えば図3(c)に示したメサエッ
チングにおいて、SiO2 膜21の幅が正確に2μmに
なっていても、メサ構造のばらつきや活性層エッチング
時のサイドエッチングにより、活性層幅がばらついてし
まう。特に2インチ基板などの大口径ウェハを用いたプ
ロセスではウェハ面内のばらつきはかなり大きくなる。
また、制御性の良いドライエッチングによる方法におい
ても活性層にダメージを与えるという問題があった。活
性層、導波路幅のばらつきや活性層内の欠陥はしきい値
電流、発振波長、ビームパターン、信頼性などの素子特
性に影響を与えるため、素子の歩留まりを低下させるだ
けでなく、設計通りの動作が得られにくいなどの問題が
あり改善の必要があった。
In order to manufacture a large number of semiconductor lasers as described above, it is important to use a large-area wafer and to precisely control the layer structure.
The layer thickness can be sufficiently controlled by using a vapor growth method such as MOVPE, but the waveguide width is conventionally controlled by mesa etching using SiO 2 as a mask, and is sufficiently controlled by side etching or the like. There was a problem such as not being able to obtain sex. For example, in the mesa etching shown in FIG. 3C, even if the width of the SiO 2 film 21 is exactly 2 μm, the width of the active layer varies due to the variation of the mesa structure and the side etching during the etching of the active layer. .. In particular, in a process using a large-diameter wafer such as a 2-inch substrate, the variation within the wafer surface becomes considerably large.
In addition, there is a problem that the active layer is damaged even by the dry etching method with good controllability. Variations in the active layer and waveguide width and defects in the active layer affect device characteristics such as threshold current, oscillation wavelength, beam pattern, and reliability, so not only does the yield of the device decrease, but There was a problem that it was difficult to obtain the action of and there was a need for improvement.

【0004】本発明の目的は、上記の問題点を解決し、
高性能,高歩留まりな光半導体素子の製造方法を提供す
ることにある。
The object of the present invention is to solve the above problems,
An object of the present invention is to provide a method for manufacturing an optical semiconductor device with high performance and high yield.

【0005】[0005]

【課題を解決するための手段】本発明は、半導体基板上
に、間に光導波路形成領域を挟んで対向する2本の誘電
体薄膜ストライプを形成する工程と、前記誘電体薄膜ス
トライプ以外の前記半導体基板上に活性層を含む半導体
多層膜を積層する選択成長工程とを含む光半導体素子の
製造方法において、前記光導波路形成領域の中央に誘電
体薄膜ストライプを形成し、一対の電流ブロック層を選
択成長により形成する工程と、この工程に引き続き、前
記光導波路形成領域の中央に形成した誘電体薄膜ストラ
イプを除去し、前記半導体基板の一部を露出させる工程
と、この工程に引き続き、前記誘電体ストライプ以外に
活性層を含む半導体多層膜を積層する選択成長工程とを
さらに含むことを特徴とする。
According to the present invention, a step of forming two dielectric thin film stripes facing each other with an optical waveguide forming region interposed therebetween on a semiconductor substrate, and the above-mentioned method other than the dielectric thin film stripes are provided. In a method of manufacturing an optical semiconductor device, which comprises a selective growth step of laminating a semiconductor multilayer film including an active layer on a semiconductor substrate, a dielectric thin film stripe is formed in the center of the optical waveguide forming region, and a pair of current block layers is formed. The step of forming by selective growth, the step of removing the dielectric thin film stripe formed in the center of the optical waveguide formation region and the step of exposing a part of the semiconductor substrate subsequent to this step, A selective growth step of stacking a semiconductor multilayer film including an active layer in addition to the body stripe is further included.

【0006】[0006]

【作用】本発明の方法では活性層を形成する前に、電流
ブロック層の形成を選択成長により行う。この電流ブロ
ック層は(100)方向の半導体基板表面の[011]
方向に2本のSiO2 膜などの誘電体薄膜ストライプを
形成し、MOVPEにより選択成長するため、ストライ
プに挟まれた部分は表面が平坦な(100)面、側面が
平滑な(111)面であるリッジ状に成長する。このた
め、活性層幅をメサエッチングなどの均一性に欠ける手
法を用いずにSiO2 膜のパターニングだけで決定で
き、制御性及び再現性に優れ、また、電流ブロック層の
形成後に活性層を形成するため界面再結合成分の少ない
良好な特性を有した半導体レーザの作製が可能となる。
In the method of the present invention, the current blocking layer is formed by selective growth before forming the active layer. This current blocking layer is [011] on the surface of the semiconductor substrate in the (100) direction.
Since two dielectric thin film stripes such as SiO 2 films are formed in the direction and are selectively grown by MOVPE, the part sandwiched between the stripes has a flat surface (100) surface and a smooth side surface (111) surface. It grows like a ridge. Therefore, the width of the active layer can be determined only by patterning the SiO 2 film without using a technique such as mesa etching that lacks uniformity, and the controllability and reproducibility are excellent, and the active layer is formed after the current block layer is formed. Therefore, it is possible to manufacture a semiconductor laser having good characteristics with few interface recombination components.

【0007】また、本発明の方法ではp−InPクラッ
ド層及びp+ −InGaAsキャップ層の形成も選択成
長により行う。このため、素子作製プロセスがSiO2
などの誘電体薄膜のパターニング及び選択成長のみによ
って構成され、諸問題の根源となる半導体のエッチング
を全く用いる必要がない。こうして、大面積ウェハを用
いた均一性,再現性に優れた一括成長/プロセスにより
素子を作製でき、活性層を選択成長で形成することによ
る利点を最大限引き出すことができる。
In the method of the present invention, the p-InP cladding layer and the p + -InGaAs cap layer are also formed by selective growth. Thus, the device fabrication process SiO 2
It is constituted only by patterning and selective growth of a dielectric thin film such as, and there is no need to use etching of a semiconductor which is the root of various problems. In this way, devices can be manufactured by batch growth / process with excellent uniformity and reproducibility using a large-area wafer, and the advantages of forming active layers by selective growth can be maximized.

【0008】[0008]

【実施例】図1,図2に本発明による方法を用いた埋め
込みリッジ構造半導体レーザの製造方法を示す。(10
0)方位のn−InP基板1の表面にCVD法を用いて
SiO2 膜21(厚さ約2000オングストローム)を
堆積し、フォトリソグラフィの手法を用いて幅10μ
m,間隔5μmの2本のストライプと、2本のストライ
プの中央に幅1μmのストライプを形成した(図1
(a))。そして、減圧MOVPEによりZnドープp
−InP層2(層厚1μm,キャリア濃度5×1017
-3)、Si−ドープn−InP層3(層厚0.5μ
m,キャリア濃度1×1018cm-3)を選択成長した
(図1(b))。層厚はSiO2 膜に挟まれた電流ブロ
ック層における値である。次に、一対の電流ブロック層
に挟まれた領域の幅1μmのストライプ状のSiO2
21を除去し(図1(c))、残されたSiO2 膜21
を用いて、n−InPクラッド層4(層厚1μm,キャ
リア濃度1×1018cm-3)、InGaAsP活性層5
(1.55μm組成,層厚800オングストローム)、
p−InPクラッド層6(層厚1.5μm,キャリア濃
度5×1017cm-3)、p+ −InGaAsキャップ層
7(層厚0.3μm,キャリア濃度1×1019cm-3
を選択成長し(図2(d))、再び全面に形成したSi
2 膜21の活性領域上部のみを幅2μmのストライプ
状に除去して(図2(e))、p側電極32及びn側電
極33を形成してレーザを完成した(図2(f))。こ
のレーザを共振器長300μmで評価したところ、しき
い値電流は平均10mA、標準偏差0.2mA、スロー
プ効率は平均0.3W/A、標準偏差0.04W/Aで
あった。活性層幅は平均2.0μm、標準偏差0.12
μmであった。この結果は従来例の結果に比べ改善され
ており、本発明を用いることにより、素子特性の均一性
が向上することが確認された。こうした大面積高均一成
長が可能なMOVPE成長を用いることにより、特性歩
留まりの高い、低価格な半導体レーザを製造することが
可能となる。なお本実施例では活性層にバルクInGa
AsPを用いたが、量子井戸構造(MQW)を用いるこ
とにより一層の特性改善が図れる。また、電流ブロック
層の構造もpnpnのサイリスタ構造の他、InGaA
sのワイドギャップ層やFeドープInPなどの高抵抗
層を用いることにより一層の特性改善が図れる。
1 and 2 show a method of manufacturing a buried ridge structure semiconductor laser using the method according to the present invention. (10
A SiO 2 film 21 (thickness: about 2000 Å) is deposited on the surface of the n-InP substrate 1 having the 0) orientation by the CVD method, and the width is 10 μm by the photolithography method.
m, and two stripes with an interval of 5 μm, and a stripe with a width of 1 μm in the center of the two stripes (see FIG. 1).
(A)). Then, Zn-doped p is formed by reduced pressure MOVPE.
-InP layer 2 (layer thickness 1 μm, carrier concentration 5 × 10 17 c
m −3 ), Si-doped n-InP layer 3 (layer thickness 0.5 μm
m, carrier concentration 1 × 10 18 cm −3 ) was selectively grown (FIG. 1B). The layer thickness is a value in the current block layer sandwiched between SiO 2 films. Then, to remove the stripe-shaped SiO 2 film 21 having a width 1μm of the region sandwiched between the pair of current blocking layers (Fig. 1 (c)), SiO left 2 film 21
N-InP clad layer 4 (layer thickness 1 μm, carrier concentration 1 × 10 18 cm −3 ), InGaAsP active layer 5
(1.55 μm composition, layer thickness 800 Å),
p-InP clad layer 6 (layer thickness 1.5 μm, carrier concentration 5 × 10 17 cm −3 ), p + -InGaAs cap layer 7 (layer thickness 0.3 μm, carrier concentration 1 × 10 19 cm −3 ).
Selectively grown (FIG. 2 (d)), and Si formed on the entire surface again
Only the upper part of the active region of the O 2 film 21 is removed in a stripe shape having a width of 2 μm (FIG. 2 (e)), and the p-side electrode 32 and the n-side electrode 33 are formed to complete the laser (FIG. 2 (f)). ). When this laser was evaluated with a cavity length of 300 μm, the threshold current was 10 mA on average, the standard deviation was 0.2 mA, and the slope efficiency was 0.3 W / A on average and 0.04 W / A on standard deviation. Active layer width is 2.0 μm on average, standard deviation 0.12
was μm. This result is improved as compared with the result of the conventional example, and it was confirmed that the uniformity of device characteristics is improved by using the present invention. By using MOVPE growth capable of such large-area and high-uniform growth, it becomes possible to manufacture a low-priced semiconductor laser with a high characteristic yield. In this embodiment, bulk InGa is used as the active layer.
Although AsP was used, the characteristics can be further improved by using a quantum well structure (MQW). In addition to the pnpn thyristor structure, the structure of the current block layer is InGaA.
Further improvement in characteristics can be achieved by using a wide-gap layer of s or a high resistance layer such as Fe-doped InP.

【0009】[0009]

【発明の効果】以上説明したように、本発明の光半導体
素子の作製方法を用いれば、均一性,再現性に乏しい半
導体のエッチングが全く不要となり、均一な活性層,導
波路幅を有する素子を制御性よく作製できる。この方法
を大面積ウェハを用いた一括成長/プロセスにより行う
ことにより、高特性の低価格半導体レーザを高歩留まり
で作製することが可能となった。
As described above, when the method for manufacturing an optical semiconductor device of the present invention is used, etching of a semiconductor having poor uniformity and reproducibility is completely unnecessary, and a device having a uniform active layer and a uniform waveguide width. Can be manufactured with good controllability. By carrying out this method by batch growth / process using a large-area wafer, it has become possible to manufacture low-priced semiconductor lasers of high characteristics with high yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体レーザの製造方法の一実施
例を示す断面図である。
FIG. 1 is a sectional view showing an embodiment of a method for manufacturing a semiconductor laser according to the present invention.

【図2】本発明による半導体レーザの製造方法の一実施
例を示す断面図である。
FIG. 2 is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor laser according to the present invention.

【図3】従来の半導体レーザの製造方法を説明するため
の図である。
FIG. 3 is a diagram for explaining a conventional method for manufacturing a semiconductor laser.

【図4】従来の半導体レーザの製造方法を説明するため
の図である。
FIG. 4 is a diagram for explaining a conventional method for manufacturing a semiconductor laser.

【符号の説明】[Explanation of symbols]

1 n−InP基板 2 p−InP層 3 n−InP層 4 n−InPクラッド層 5 活性層(量子井戸構造を含む) 6 p−InPクラッド層 7 p−InGaAsキャップ層 8 n−InGaAsPガイド層 21 SiO2 膜 31 プロトン注入領域 32 p側電極 33 n側電極1 n-InP substrate 2 p-InP layer 3 n-InP layer 4 n-InP clad layer 5 active layer (including quantum well structure) 6 p-InP clad layer 7 p-InGaAs cap layer 8 n-InGaAsP guide layer 21 SiO 2 film 31 Proton injection region 32 p-side electrode 33 n-side electrode

【手続補正書】[Procedure amendment]

【提出日】平成4年3月18日[Submission date] March 18, 1992

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0006[Correction target item name] 0006

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0006】[0006]

【作用】本発明の方法では活性層を形成する前に、電流
ブロック層の形成を選択成長により行う。この電流ブロ
ック層は(100)方向の半導体基板表面の[011]
方向に2本のSiO2 膜などの誘電体薄膜ストライプを
形成し、MOVPEにより選択成長するため、ストライ
プに挟まれた部分は表面が平坦な(100)面、側面が
平滑な(111)面であるリッジ状に成長する。この
ため、活性層幅をメサエッチングなどの均一性に欠ける
手法を用いずにSiO2 膜のパターニングだけで決定で
き、制御性及び再現性に優れ、また、電流ブロック層の
形成後に活性層を形成するため界面再結合成分の少ない
良好な特性を有した半導体レーザの作製が可能となる。
In the method of the present invention, the current blocking layer is formed by selective growth before forming the active layer. This current blocking layer is [011] on the surface of the semiconductor substrate in the (100) direction.
Two dielectric thin film stripes such as SiO 2 film are formed in the direction, and selective growth is performed by MOVPE. Therefore, the surface sandwiched between the stripes is a (100) surface with a flat surface and a smooth (111) B surface. It grows like a ridge. Therefore, the width of the active layer can be determined only by patterning the SiO 2 film without using a technique such as mesa etching that lacks uniformity, and the controllability and reproducibility are excellent, and the active layer is formed after the current block layer is formed. Therefore, it is possible to manufacture a semiconductor laser having good characteristics with few interface recombination components.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0008[Correction target item name] 0008

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0008】[0008]

【実施例】図1,図2に本発明による方法を用いた埋め
込みリッジ構造半導体レーザの製造方法を示す。(10
0)方位のn−InP基板1の表面にCVD法を用いて
SiO2 膜21(厚さ約2000オングストローム)を
堆積し、フォトリソグラフィの手法を用いて幅10μ
間隔5μmの2本のストライプと、2本のストライ
プの中央に幅1μmのストライプを形成した(図1
(a))。そして、減圧MOVPEによりZnドープp
−InP層2(層厚1μm,キャリア濃度5×1017
-3)、Siドープn−InP層3(層厚0.5μm,
キャリア濃度1×1018cm-3)を選択成長した(図1
(b))。層厚はSiO2 膜に挟まれた電流ブロック層
における値である。次に、一対の電流ブロック層に挟ま
れた領域の幅1μmのストライプ状のSiO2 膜21を
除去し(図1(c))、残されたSiO2 膜21を用い
て、n−InPクラッド層4(層厚1μm,キャリア濃
度1×1018cm-3)、InGaAsP活性層5(1.
55μm組成,層厚800オングストローム)、p−I
nPクラッド層6(層厚1.5μm,キャリア濃度5×
1017cm-3)、p+ −InGaAsキャップ層7(層
厚0.3μm,キャリア濃度1×1019cm-3)を選択
成長し(図2(d))、再び全面に形成したSiO2
21の活性領域上部のみを幅2μmのストライプ状に除
去して(図2(e))、p側電極32及びn側電極33
を形成してレーザを完成した(図2(f))。このレー
ザを共振器長300μmで評価したところ、しきい値電
流は平均10mA、標準偏差0.2mA、スロープ効率
は平均0.3W/A、標準偏差0.04W/Aであっ
た。活性層幅は平均2.0μm、標準偏差0.12μm
であった。この結果は従来例の結果に比べ改善されてお
り、本発明を用いることにより、素子特性の均一性が向
上することが確認された。こうした大面積高均一成長が
可能なMOVPE成長を用いることにより、特性歩留ま
りの高い、低価格な半導体レーザを製造することが可能
となる。なお本実施例では活性層にバルクInGaAs
Pを用いたが、量子井戸構造(MQW)を用いることに
より一層の特性改善が図れる。また、電流ブロック層の
構造もpnpnのサイリスタ構造の他、InGaAsの
ワイドギャップ層やFeドープInPなどの高抵抗層を
用いることにより一層の特性改善が図れる。
1 and 2 show a method of manufacturing a buried ridge structure semiconductor laser using the method according to the present invention. (10
A SiO 2 film 21 (thickness: about 2000 Å) is deposited on the surface of the n-InP substrate 1 having the 0) orientation by the CVD method, and the width is 10 μm by the photolithography method.
m 2 and two stripes with an interval of 5 μm, and a stripe with a width of 1 μm was formed at the center of the two stripes (FIG.
(A)). Then, Zn-doped p is formed by reduced pressure MOVPE.
-InP layer 2 (layer thickness 1 μm, carrier concentration 5 × 10 17 c
m -3 ), Si-doped n-InP layer 3 (layer thickness 0.5 μm,
A carrier concentration of 1 × 10 18 cm -3 ) was selectively grown (Fig. 1).
(B)). The layer thickness is a value in the current block layer sandwiched between SiO 2 films. Next, the stripe-shaped SiO 2 film 21 having a width of 1 μm in the region sandwiched between the pair of current block layers is removed (FIG. 1C), and the remaining SiO 2 film 21 is used to form the n-InP clad. Layer 4 (layer thickness 1 μm, carrier concentration 1 × 10 18 cm −3 ), InGaAsP active layer 5 (1.
55 μm composition, layer thickness 800 Å), p-I
nP clad layer 6 (layer thickness 1.5 μm, carrier concentration 5 ×
10 17 cm -3 ), a p + -InGaAs cap layer 7 (layer thickness 0.3 μm, carrier concentration 1 × 10 19 cm -3 ) was selectively grown (FIG. 2D), and SiO 2 formed again on the entire surface. Only the upper part of the active region of the film 21 is removed in a stripe shape having a width of 2 μm (FIG. 2E), and the p-side electrode 32 and the n-side electrode 33 are removed.
Was formed to complete the laser (FIG. 2 (f)). When this laser was evaluated with a cavity length of 300 μm, the threshold current was 10 mA on average, the standard deviation was 0.2 mA, and the slope efficiency was 0.3 W / A on average and 0.04 W / A on standard deviation. The average width of the active layer is 2.0 μm with a standard deviation of 0.12 μm
Met. This result is improved as compared with the result of the conventional example, and it was confirmed that the uniformity of device characteristics is improved by using the present invention. By using MOVPE growth capable of such large-area and high-uniform growth, it becomes possible to manufacture a low-priced semiconductor laser with a high characteristic yield. In this embodiment, bulk InGaAs is used for the active layer.
Although P is used, the characteristics can be further improved by using a quantum well structure (MQW). In addition to the pnpn thyristor structure as the structure of the current block layer, the characteristics can be further improved by using a wide-gap layer of InGaAs or a high resistance layer such as Fe-doped InP.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に、間に光導波路形成領域を
挟んで対向する2本の誘電体薄膜ストライプを形成する
工程と、前記誘電体薄膜ストライプ以外の前記半導体基
板上に活性層を含む半導体多層膜を積層する選択成長工
程とを含む光半導体素子の製造方法において、 前記光導波路形成領域の中央に誘電体薄膜ストライプを
形成し、一対の電流ブロック層を選択成長により形成す
る工程と、 この工程に引き続き、前記光導波路形成領域の中央に形
成した誘電体薄膜ストライプを除去し、前記半導体基板
の一部を露出させる工程と、 この工程に引き続き、前記誘電体ストライプ以外に活性
層を含む半導体多層膜を積層する選択成長工程とをさら
に含むことを特徴とする光半導体素子の製造方法。
1. A step of forming, on a semiconductor substrate, two dielectric thin film stripes opposed to each other with an optical waveguide forming region interposed therebetween, and an active layer is included on the semiconductor substrate other than the dielectric thin film stripes. In a method for manufacturing an optical semiconductor element, which comprises a selective growth step of laminating a semiconductor multilayer film, a step of forming a dielectric thin film stripe in the center of the optical waveguide formation region, and forming a pair of current block layers by selective growth, Subsequent to this step, a step of removing the dielectric thin film stripe formed in the center of the optical waveguide forming region to expose a part of the semiconductor substrate, and, following this step, including an active layer in addition to the dielectric stripe. A method of manufacturing an optical semiconductor device, further comprising a selective growth step of stacking semiconductor multilayer films.
JP1606592A 1992-01-31 1992-01-31 Manufacture of light semiconductor element Pending JPH05218564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1606592A JPH05218564A (en) 1992-01-31 1992-01-31 Manufacture of light semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1606592A JPH05218564A (en) 1992-01-31 1992-01-31 Manufacture of light semiconductor element

Publications (1)

Publication Number Publication Date
JPH05218564A true JPH05218564A (en) 1993-08-27

Family

ID=11906176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1606592A Pending JPH05218564A (en) 1992-01-31 1992-01-31 Manufacture of light semiconductor element

Country Status (1)

Country Link
JP (1) JPH05218564A (en)

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