JPH05215818A - Semiconductor testing device and testing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] In semiconductor test equipment, by connecting a switch circuit to the multiple reflection prevention circuit, it is possible to apply the multiple reflection prevention circuit at the I / O pin of the device under test and measure the response waveform. Improve time accuracy. [Structure] When outputting a driver, the I / O switch is turned on and the switch circuit of the multiple reflection preventing circuit is turned off. The output becomes a test waveform 6a via the driver 6 and is given to the device under test 11 by the transmission line 10. To receive the output signal 11a from the device under test 11 as a response to the test waveform 6a, the I / O switch 7 is turned off.
Then, the switch circuit 8 of the multiple reflection preventing circuit is turned on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly to TTL, CMOS, NMOS, PMOS and BI.
-A semiconductor test apparatus suitable for testing non-terminal devices such as CMOS.

[0002]

2. Description of the Related Art A conventional semiconductor test apparatus is the Institute of Electronics and Communication Engineers Technical Report 189, No. 384, ICD 89-17.
0 (1989), pp. 51-58, waveform characteristics between TTL and CMOS devices and pin electronics without termination resistors designed on the assumption that the transmission line is not driven. That is, the ringing waveform due to the multiple reflection of the response waveform from the device under test is injected and removed from the dynamic load that is standardly equipped in the test apparatus, thereby preventing erroneous determination due to the ringing waveform.

[0003]

The above-mentioned conventional method has the following problems.

That is, at the I / O pin of the device under test, the output waveform of the driver is distorted by the multiple reflection preventing circuit and the prescribed test waveform cannot be input to the device under test. This is because the output state of the driver and the output state of the device under test are switched in real time during the test at the I / O pin. Therefore, when the output voltage range of the driver overlaps with the low input impedance voltage range of the multiple reflection prevention circuit, This is because the output voltage of is divided. Further, when the voltage range in which the input impedance of the multiple reflection prevention circuit is low is set outside the output voltage range of the driver, the reflected voltage cannot be sufficiently absorbed, resulting in erroneous determination.

As described above, according to the conventional method, the I
There is a problem that the multiple antireflection circuit cannot be used for the / O pin.

An object of the present invention is to provide a semiconductor test apparatus and method capable of using multiple antireflection circuits for I / O pins.

[0007]

According to the present invention, by connecting a high-speed switch circuit to a multiple antireflection circuit, the input impedance of the multiple antireflection circuit can be maintained at a high impedance with respect to any input voltage at the time of driver output. It is designed to switch between the output state of the device under test that effectively uses the antireflection circuit and the output state of the driver that can input the specified waveform to the device under test without interrupting the test. is there.

Further, the switch circuit of the multiple reflection preventing circuit and the drive circuit of the I / O switch of the driver are made common,
Connect to different output terminals.

Further, according to the present invention, by connecting a high-speed variable voltage source or the like to the multiple antireflection circuit, the voltage range in which the input impedance of the multiple antireflection circuit becomes low at the time of driver output and the driver output voltage range overlap. , And effectively use the multiple anti-reflection circuit to switch between the output state of the device under test and the output state of the driver capable of inputting the specified waveform to the device under test without interrupting the test. It is the one.

[0010]

The function of effectively using the multiple reflection prevention circuit is switched between the output state of the device under test and the output state of the driver capable of inputting the prescribed waveform to the device under test without interrupting the test. Of the device under test
It is possible to perform a test in which a specified input voltage is applied from the driver to the / O pin as well, and a misjudgment does not occur.

Further, by making the switch circuit of the multiple reflection prevention circuit and the drive circuit of the I / O switch of the driver in common, the output state of the device under test that effectively uses the multiple reflection prevention circuit and the prescribed waveform It is possible to simplify the control circuit that switches the state at the time of output of the driver capable of inputting to the device under test.

[0012]

1 is a block diagram showing an embodiment of a semiconductor test apparatus according to the present invention. In FIG. 1, the semiconductor test apparatus includes a timing generator 1, a pattern generator 2, a waveform formatter 3, a digital comparator 4, a driver 6, an I / O changeover switch 7, an analog comparator 5, and a device under test. A transmission line 10 for electrically connecting 11 to each other, a multiple reflection preventing circuit 9 provided in the vicinity of the analog comparator 5, and I of the device under test connected between the multiple reflection preventing circuit 9 and the input of the analog comparator 5.
The switch circuit 8 has a switching time shorter than the / O switching time.

In the above structure, first, the I / O switch 7 is turned on, and the switch circuit of the multiple reflection preventing circuit is turned off.
F Timing signal 1a created by timing generator 1 and test pattern 2 created by pattern generator 2
It is combined with a by the waveform formatter 3, and its output is given to the device under test 11 by the transmission line 10 as the test waveform 6a via the driver 6.

To receive the output signal 11a from the device under test 11 as a response to the test waveform 6a, the I / O switch 7 is turned off and the switch circuit 8 of the multiple reflection preventing circuit is turned on. The output signal 11a from the device under test 11 is voltage converted by the analog comparator 5
After conversion into digital values of 0 "and" 1 ", a comparison test is performed at a time indicated by the timing signal 1b with the expected value 2b which is the response of the non-defective element created by the pattern generator 2 by the digital comparator 4. At this time, the multiple reflection prevention circuit 9 provided near the analog comparator 5 improves the measurement accuracy of the response time of the device under test 11.

FIG. 2 is a response waveform diagram received from the device under test of the semiconductor test apparatus of FIG. 2A shows a reflection diagram, the horizontal axis shows current and the vertical axis shows voltage, and FIG. 2B shows the response waveform of the device under test 11. The characteristic 12 of the multiple reflection preventing circuit is bent at points a and b, and the impedance becomes low. The low impedance portion is made equal to the characteristic impedance Z0 of the transmission line, the point a is the point where the high-level output characteristic 13 of the device under test has a current of 0, and the point b is the low-level output characteristic 14 of the device under test is the current. The operation of the multiple reflection preventing circuit will be described below with reference to FIG.

As shown in FIG. 2B, when the output signal 11a of the device under test 11 changes from low level to high level at time t0, the potential of the output waveform 11a at the end of the device under test becomes as follows. In the reflection diagram of FIG. 2A, the straight line 15 having the slope of the characteristic impedance Z0 of the transmission line 10 and the high-level output of the device under test 11 from the point where both the voltage and the current, which are low-level values of the device under test 11, are zero. It rises up to the potential at the intersection c with the characteristic 13. Therefore, FIG.
Output waveform 11 at the end of the device under test as indicated by the dotted line B
a rises to the voltage V1 at time t0. When this waveform 11a propagates through the transmission line 10 having an electrical length of τ seconds and reaches the multiple reflection preventing circuit 9, the straight line 16 having a slope −Z0 from the point c in FIG. Characteristic 12
The potential V at the end of the multiple reflection preventing circuit 9 rises up to the point d of the intersection with. When this is observed at the end of the multiple reflection prevention circuit 9,
As indicated by the solid line of B, the potential rises to the potential V2 at time t + τ. When this waveform 11b is reflected and reaches the end of the device under test, in FIG. 2A, a straight line 12 having a slope Z0 from the point a and a high-level output characteristic 13 of the device under test 11 are obtained.
Move to point a, which is the intersection of. Therefore, the output waveform 11a of the device under test 11 at the output end of the device under test is time t0 +
At 2τ, the output voltage V0H is obtained when there is no load. This waveform is reflected again, and at time t0 + 3τ, the output waveform 11b of the device under test 11 at the end of the multiple reflection preventing circuit 9 also becomes the output voltage V0H under no load. At this time, since the electric potentials of all parts of the transmission line 10 become equal to V0H, the time t0 +
After 3τ, the reflection phenomenon does not occur and the potential becomes constant. Therefore, the waveform at the input terminal of the analog comparator 5 arranged near the multiple antireflection circuit 9 is also equal to the output waveform 11b of the device under test 11 in the multiple antireflection circuit shown in FIG. At the input terminal of the analog comparator 5 for comparing the voltage of the output waveform from the element 11,
Accurate timing of rising can be measured without generating a portion of the device under test 11 having a high level or lower. Even in the case of the fall, accurate timing measurement can be performed similarly.

According to this embodiment, when the driver 6 outputs,
Since the switch circuit 8 of the multiple reflection preventing circuit is OFF, the driver output waveform 6a that is equal to or higher than the voltage at the point a or lower than the voltage at the point b of the characteristic 12 of the multiple reflection preventing circuit is divided by the impedance of the multiple reflection preventing circuit 9. There is nothing. Therefore, it becomes possible to input a test waveform defined in advance to the device under test. Further, when the device under test 11 outputs, the I / O switch 7 is OFF and the switch circuit 8 of the multiple reflection preventing circuit is ON, so that the output waveform 11a of the device under test is divided by the output impedance of the driver 6. It is not pressed, and multiple reflection can be prevented, and the timing accuracy is improved. Moreover, by using a switch circuit having a switching time shorter than the I / O switching time of the device under test 11 as the switch circuit 8 of the multiple reflection preventing circuit, the output state of the driver 6 and the device under test 11 can be tested without interrupting the test. The output state can be switched. By these, a specified input voltage from the driver can be applied to the I / O pin of the device under test 11,
And accurate timing can be measured.

FIG. 3 is a circuit diagram showing an embodiment of the semiconductor test apparatus of FIG. In FIG. 3, the I / O switch 7 is composed of diodes 7a, 7b, 7c and 7d, and the switch circuit 8 of the multiple reflection prevention circuit is composed of diodes 8a and 8a.
b, 8c, 8d. The multiple reflection prevention circuit 9 has a resistor 9
a, 9d, diodes 9b, 9e, and voltage sources 9c, 9
The sum of the resistance values of the resistors 9a and 9d and the internal resistance of the diode is equal to the characteristic impedance Z0 of the transmission line. Further, the voltage source 9c of the multiple reflection preventing circuit 9 is set so that the point b of the characteristic 12 of the multiple reflection preventing circuit matches the voltage at which the low-level characteristic current of the device under test becomes zero. The voltage source 9f is set so that the point a of the characteristic 12 matches the voltage at which the high-level characteristic current of the device under test becomes zero.

With the above structure, the switch control circuit 28a controls the transistors 19a of the current switches 19 and 20,
20a is turned on, a current is passed through the I / O switch 7, and the switch control circuit 28b turns off the transistors 21b and 22b of the current switches 21 and 22 to turn off the current of the switch circuit 8 of the multiple reflection preventing circuit. At this time, the I / O switch 7 is turned on and the switch circuit 8 of the multiple reflection prevention circuit is turned off. The test waveform 6a output from the driver 6 is applied to the device under test 11 through the transmission line 10.

To receive the output signal 11a from the device under test 11 as a response to the test waveform 6a, the switch control circuit 28a turns off the transistors 19a and 20a of the current switches 19 and 20, and the I / O switch 7 Current of the current switches 21 and 22 by the switch control circuit 28b,
22b is turned on and the switch circuit 8 of the multiple reflection preventing circuit
Apply current to. At this time, the I / O switch 7 is set to O.
The switch circuit 8 of the multiple reflection prevention circuit is turned on to the FF. The output signal 11a from the device under test 11 is converted into a voltage by the analog comparator 5 into a digital value of "0" or "1". The voltage-current characteristic of the multiple antireflection circuit is equal to the characteristic 12 of FIG. 2, and an extra reflected wave is absorbed by the multiple antireflection circuit.

In the above-mentioned embodiment, the switch circuit 8 of the multiple reflection preventing circuit is constituted by the diode bridge.
It may be replaced by a switch circuit or element having a switching time shorter than the I / O switching time, such as a switching circuit configured by T.

Although the switch circuit is connected between the input of the analog comparator and the multiple antireflection circuit, the switch circuit may be connected between the diode of the multiple antireflection circuit and the voltage source.

FIG. 4 is a block diagram showing another embodiment of the semiconductor test apparatus according to the present invention. In FIG. 4, the semiconductor test apparatus includes a timing generator 1 and a pattern generator 2.
, Waveform formatter 3, digital comparator 4
A driver 6, a driver / multiple reflection prevention circuit changeover switch 8, an analog comparator 5, a transmission line 10 electrically connecting the device under test 41, and a multiple reflection prevention circuit 9 provided near the analog comparator 5. Consists of.

With the above structure, the driver / multiple reflection prevention circuit changeover switch 8 is connected to the driver side. The timing signal 1a generated by the timing generator 1 and the test pattern 1a generated by the pattern generator 2 are combined by the waveform formatter 3, and the output thereof becomes the test waveform 6a via the driver 6 by the transmission line 10. It is applied to the device under test 11.

To receive the output signal 11a from the device under test 11 as a response to the test waveform 6a, the driver / multiple antireflection circuit switching stitch 8 is connected to the multiple antireflection circuit side. The output signal 11a from the device under test 11 is converted into a voltage by the analog comparator 5 to be "0", "1".
After being converted to the digital value of, the comparison test is performed at the time indicated by the timing signal 1b with the expected value 2b which is the response of the non-defective element created by the pattern generator 2 by the digital comparator 4. At this time, the multiple reflection prevention circuit provided near the analog comparator 5 improves the measurement accuracy of the response time of the device under test 11.

In the case of this embodiment, there is an advantage that the circuit for switching the driver and the multiple reflection preventing circuit can be simplified.

FIG. 5 is a circuit diagram showing an embodiment of the semiconductor test apparatus of FIG. In FIG. 5, the I / O switch 7 is composed of diodes 7a, 7b, 7c and 7d, and the switch 8 of the multiple reflection preventing circuit is composed of diodes 8a and 8b.
It consists of 8c and 8d. Each switch is current switch 1
Driven by 9 and 20, one transistor 19a, 20a of the current switch is connected to the I / O switch 7, and the other transistor 19b, 20b is connected to the switch 8 of the multiple reflection preventing circuit. Resistance value of resistor 49 and driver 6
The sum of the output impedances of the two is equal to the transmission line Z0. The multiple reflection prevention circuit 9 includes diodes 9b and 9e and a voltage source 9
The voltage source 9c is set so that the point b of the characteristic 12 of the multiple reflection preventing circuit coincides with the voltage at which the low-level characteristic current of the device under test becomes 0, and the voltage source 9f is subjected to multiple reflection. The point a of the characteristic 12 of the prevention circuit is set so as to match the voltage at which the high-level characteristic current of the device under test becomes zero.

With the above configuration, the switch control circuit 28 controls the transistors 19b and 2 of the current switches 19 and 20.
0b is turned on, a current is passed through the I / O switch 7, and the transistors 19 of the current switches 19 and 20 are connected.
By turning off b and 20b, the current of the switch circuit 8 of the multiple reflection preventing circuit is cut off. At this time, the I / O switch 7 is turned on, and the switch circuit 8 of the multiple reflection preventing circuit is turned off.
It becomes F. The test waveform 6a output from the driver 6 is applied to the device under test 11 through the transmission line 10. The test waveform 6a output from the driver 6 does not cause multiple reflection because it is terminated at the sending end by the resistor 49.

In order to receive the output signal 11a from the device under test 11 as a response to the test waveform 6a, the switch control circuit 28 turns off the transistors 19a and 20a of the current switches 19 and 20 to turn off the I / O switch. The current is cut off, the transistors 19b and 20b of the current switches 19 and 20 are turned on, and the current is passed through the switch circuit of the multiple reflection preventing circuit. At this time, the I / O switch is turned off and the switch circuit of the multiple reflection prevention circuit is turned on. Output signal 11a from device under test 11
Is converted to a voltage by the analog comparator 5 and is "0", "
The voltage-current characteristic obtained by combining the resistor 49 and the multiple antireflection circuit 9 is equal to the characteristic 12 of FIG. 2, and the extra reflected wave is the resistor 49 and the multiple antireflection circuit 9.
Absorbed by.

FIG. 6 is a block diagram showing still another embodiment of the semiconductor test apparatus according to the present invention. In FIG.
The semiconductor test apparatus includes a timing generator 1, a pattern generator 2, a waveform formatter 3, a digital comparator 4, a driver 6, an I / O changeover switch 7,
The analog comparator 5, the transmission line 10 electrically connecting the device under test 1, two sets of multiple antireflection circuits 9a and 9b provided in the vicinity of the analog comparator 5, and a switch circuit for switching between these multiple antireflection circuits. It consists of eight. Regarding the characteristics of the multiple reflection preventing circuit 9a, the characteristics are bent, at points a and b in FIG. 2, point a is the point at which the high-level output characteristic 13 of the device under test has a current of 0, and point b is the sample under test. It is adjusted to the point where the low-level output characteristic 14 of the element becomes zero current. Regarding the characteristics of the multiple reflection preventing circuit 9b, at points where the characteristics are bent, points a and b in FIG. 2, point a is set to the high level voltage of the driver 6 and point b is set to the low level voltage of the driver.

In the above structure, first, the I / O switch 7 is turned on, and the switch circuit 8 of the multiple reflection preventing circuit is connected to the multiple reflection preventing circuit 9b. Timing signal 1a generated by timing generator 1 and pattern generator 2
The test pattern 2a created in step 1 is synthesized by the waveform formatter 3, and its output is supplied to the device under test 71 by the transmission line 10 as the test waveform 6a via the driver 6. At this time, the low impedance voltage range of the multiple reflection prevention circuit 9b and the voltage range of the driver output waveform 6a do not overlap, and the driver output waveform 6a is not divided by the impedance of the multiple reflection prevention circuit. Therefore, it becomes possible to input a test waveform defined in advance to the device under test 11.

To receive the output signal 11a from the device under test 11 as a response to the test waveform 6a, the I / O switch is turned off and the switch circuit of the multiple reflection preventing circuit is connected to the multiple reflection preventing circuit 9a. To do. The output signal 11a from the device under test 11 is the analog comparator 5
After converting the voltage into a digital value of "0" or "1", the time indicated by the timing signal 1b between the digital comparator 4 and the expected value 2b which is the response of the non-defective element created by the pattern generator 2 Conduct a comparative test.
At this time, the multiple reflection prevention circuit 9a provided near the analog comparator 5 improves the measurement accuracy of the response time of the device under test 11.

In the above embodiment, the characteristic of the multiple reflection preventing circuit is bent, and the voltages at points a and b in FIG. 2 are changed at the time of driver output and at the time of output of the device under test. , The two sets of multiple antireflection circuits in which the voltage at the point b is set separately are switched, but the characteristic of the multiple antireflection circuit is bent, the settling time is set to the voltage source that determines the voltage at the points a and b in FIG. However, a variable voltage source shorter than the I / O switching time of the device under test may be used.

Further, the points where the characteristics are bent, points a and b in FIG.
The multiple antireflection circuit in which the voltages at the points are set separately is not limited to two sets. For example, several sets may be prepared according to the type of power supply voltage applied to the device under test.

[0035]

As described above, according to the present invention, a prescribed test waveform can be input to the device under test in order to disconnect the multiple reflection preventing circuit by the switch circuit at the time of driver output. Further, since the multiple reflection preventing circuit is connected when outputting the device under test, multiple reflection does not occur, and accurate timing measurement can be performed. Furthermore, since a switch circuit having a switching time shorter than the I / O switching time of the device under test is used for the switch circuit, the state of the driver output and the state of the device under test can be switched without interrupting the test. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor test apparatus of the present invention.

FIG. 2 is a response waveform diagram of the device under test in the semiconductor test apparatus.

3 is a circuit diagram of the semiconductor test device in FIG.

FIG. 4 is a block diagram of a semiconductor test apparatus according to another embodiment.

5 is a circuit diagram of the semiconductor test device in FIG.

FIG. 6 is a block diagram of a semiconductor test apparatus according to still another embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Timing generator, 2 ... Pattern generator, 3 ... Waveform formatter, 4 ... Digital comparator, 5 ... Analog comparator, 6 ... Driver, 7 ... I / O changeover switch, 8 ... Switch circuit, 9 ... Multiple antireflection circuit ,
10 ... Transmission line, 11 ... Device under test.

Claims (12)

[Claims] 1. A timing generator, a pattern generator,
A waveform formatter that combines the timing signal created by the timing generator and the test pattern created by the pattern generator, and the output waveform of the waveform formatter is input and the output impedance becomes high impedance when the device under test outputs. A driver equipped with an O changeover switch, a transmission line for applying a test waveform of the driver output to the device under test, and an analog comparator for inputting an output signal from the device under test as a response of the test waveform through the transmission line for voltage comparison. In the semiconductor test equipment consisting of the output of the analog comparator and the expected value created by the pattern generator for logical comparison test at the time indicated by the signal from the timing generator, the semiconductor test equipment is set in advance near the input of the analog comparator. Input impedance at voltage There semiconductor test apparatus characterized in that a multiple reflection prevention circuit to decrease. 2. A semiconductor test method, wherein the multiple antireflection circuit according to claim 1 is made to function at the time of outputting an element under test, and is not made to function at the time of outputting to a driver. 3. The semiconductor test apparatus according to claim 1, wherein a switch circuit having a switching time shorter than the I / O switching time of the device under test is connected between the multiple antireflection circuit and the input of the analog comparator. .. 4. A multiple antireflection circuit comprising a resistor and I of a device under test.
2. The semiconductor test apparatus according to claim 1, wherein a switch circuit having a switching time shorter than the / O switching time, a diode and a voltage source are connected in series in this order. 5. A multiple antireflection circuit is configured by connecting a resistor, a diode, a switch circuit having a switching time shorter than an I / O switching time of a device under test, and a voltage source in series in this order. Item 1. The semiconductor testing device according to item 1. 6. A multiple antireflection circuit comprising a resistor and I of a device under test.
A switch circuit having a switching time shorter than the / O switching time, a diode and a voltage source are connected in series in this order, and the sum of the resistance of the multiple reflection prevention circuit and the output impedance of the driver is made equal to the characteristic impedance of the transmission line. The semiconductor test apparatus according to claim 1, further comprising an I / O switch connected between the resistor and the driver circuit. 7. The semiconductor test apparatus according to claim 3, wherein the input of the multiple reflection preventing circuit or the switch circuit of the multiple reflection preventing circuit is turned on when the device under test outputs, and when the driver outputs. A semiconductor test method characterized by turning off. 8. A current switch circuit is used for driving an input of the multiple antireflection circuit or a switch circuit of the multiple antireflection circuit, and one of the current switch circuits is an I / O of a driver.
4. The changeover switch circuit is connected, and the switch circuit of the multiple reflection preventing circuit is connected to the other side.
7. The semiconductor test device according to any one of items 1 to 6. 9. The semiconductor test apparatus according to claim 1, wherein a variable voltage source whose settling time is shorter than the I / O switching time of the device under test is used as the voltage source of the multiple reflection preventing circuit. 10. The semiconductor testing apparatus according to claim 9, wherein the output impedance of the device under test is lowered by the high level voltage of the device under test output or the low level voltage of the device under test output. The semiconductor test method is characterized in that, during driver output, the input impedance of the multiple reflection preventing circuit is lowered at a voltage higher than the driver output high level or lower than the driver output low level voltage. 11. A multi-reflection preventing circuit having two or more pairs of diodes having the same polarities.
The semiconductor test device according to claim 1. 12. The semiconductor test apparatus according to claim 11, wherein the voltage of one of the voltage sources is the high level voltage of the device under test output or the low level voltage of the device under test output and the input impedance of the multiple reflection preventing circuit. Set so that the voltage drops are the same, and set the voltage of the other voltage source to the voltage at which the input impedance of the multiple reflection prevention circuit drops above the high level voltage of the driver output or below the low level voltage of the driver output. , When the device under test outputs, turn on the switch circuit of the voltage source that matches the output of the device under test,
Turn off the switch circuit of the voltage source according to the driver output
The semiconductor test method is characterized in that the switch circuit of the voltage source according to the output of the device under test is turned off and the switch circuit of the voltage source according to the driver output is turned on during driver output.