JPH05203682A - Semiconductor sensor - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to accurately set the operation starting point of a simple semiconductor sensor with an A / D conversion circuit using a CMOS inverter and to integrate the whole into one chip. An A / D that converts the output of the sensor unit into a digital value by connecting in parallel a sensor unit that responds to external changes and a plurality of CMOS inverters having different logic threshold values
It has a conversion circuit and a load CMOS inverter whose logic threshold value is controlled for setting the operation start point of this A / D conversion circuit,
The sensor section includes an operation start point setting section formed by sharing at least one element transistor, and the sensor section, the A / D conversion circuit, and the operation start point setting section are formed on the same semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor sensor with an A / D conversion circuit using a CMOS inverter, and more particularly to A
The present invention relates to a semiconductor sensor in which an operation start point setting unit for setting a start point of a / D conversion operation is formed on the same substrate.

[0002]

2. Description of the Related Art In a system using a semiconductor sensor such as a pressure sensor or an acceleration sensor, for example, a measurement control system,
The miniaturization and low power consumption of the sensor have been remarkably advanced, and recently, not only the sensor main body but also the peripheral circuit thereof has been mounted on the same substrate. Furthermore, a sensor with an A / D conversion function that directly obtains a digital output has been developed in order to improve the function and reduce the cost of this type module by miniaturizing it, and to facilitate the connection to a computer. There is.

If the existing A / D converter structure is adopted for the above-mentioned digital output type sensor, it is difficult to reduce the size. Therefore, a simple A / D converter structure using a plurality of CMOS inverters having different logic threshold values is proposed. (See, for example, Japanese Patent Application No. 2-284681). Although this A / D converter has a simple circuit configuration, it is necessary to adjust the operation start point corresponding to the zero point of the input / output relation.

[0004]

Conventional mechanical pressure sensors such as semiconductor pressure sensors and acceleration sensors require laser trimming or the like for zero point adjustment, but this must be done individually, which causes an increase in manufacturing cost. Was becoming. The present invention improves such a point, and can set the operation start point of a simple semiconductor sensor with an A / D conversion circuit using a CMOS inverter accurately, and can integrate the whole into one chip. The purpose is to do.

[0005]

In order to achieve the above object, according to the present invention, a sensor unit that responds to an external change and a plurality of CMOS inverters having different logic threshold values are connected in parallel to each other. A / that converts the output to a digital value
A D conversion circuit and a load CMOS inverter having a logic threshold value for setting an operation starting point of the A / D conversion circuit are provided, and the operation starting point setting is formed by the sensor unit sharing at least one element transistor. And a sensor section, an A / D conversion circuit, and an operation start point setting section are formed on the same semiconductor substrate.

[0006]

The operation start point setting portion formed on the same semiconductor substrate as the sensor with the A / D conversion circuit is formed in the same process as the A / D conversion circuit and is formed at an extremely close position, so The characteristics (gate oxide film thickness, threshold voltage of MOS transistor, carrier mobility of channel portion, etc.) become uniform. Therefore, the operation start point setting section can expect an operation close to the design specification, and an accurate operation start point can be automatically set.

If this operation start point setting section is constructed by a load CMOS inverter formed in the same process as the A / D conversion circuit, an accurate operation start point can be set only by controlling its logic threshold value. This is because even if the characteristics of the respective parts of the element are absolutely changed due to manufacturing technology, since the respective parts of the circuit are formed on the same substrate, the change in the relative difference between the logical threshold values in the respective CMOS inverters is small. Because. In particular, if this load CMOS inverter is connected to the input / output terminals with a feedback resistor, the most stable operation can be expected.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of a one-chip semiconductor sensor showing an embodiment of the present invention. In this figure, 1 is a pressure sensor which is one of the mechanical quantity sensors, 2 is a CMOS inverter type A / D conversion circuit for converting the output to a digital value, and 3 is a load CMOS inverter for setting the operation starting point.

The pressure sensor 1 is not independent, but actually uses the element transistor of the load CMOS inverter 3. That is, the inverter 3 uses the P-channel MOS transistor PMOS and the N-channel MOS transistor NMOS as element transistors, but one or both of them are shared as the pressure sensor 1.
In this example, the PMOS is used as the sensor. That is, as shown in FIG. 2, the Si chip 50 having the (100) surface as its surface is used.
A circular thin diaphragm portion 51 is formed in the central portion of the above, and the A / D conversion circuit 2 and the NMOS of the load CMOS inverter 3 are formed in the peripheral portion thereof so that they are not subjected to pressure change. At this time, the PMOS shared as the sensor 1
Is formed on the diaphragm portion 51 side so as to receive a pressure change. Reference numeral 52 is a glass pedestal on which the Si chip 50 is mounted. In the pressure sensor 1 using the PMOS, the carrier mobility μ _{p of the} channel portion changes when pressure is applied. Since β _R changes when μ _p changes, Δ in Equation 1
V _T changes temporarily. This temporary change is a differential output of the sensor in response to the pressure, unlike the steady-state logical threshold control described later.

[0010]

[Equation 1]

The A / D conversion circuit 2 includes CMOS inverters 11 to 14 at the input stage and CMOS inverters 21 to 21 at the intermediate stage.
24 and output stage gates 31 to 34, and has a resolution of 5 gradations. The inverters 11 to 14 at the input stage are shown in FIG.
In order to show its input / output transfer characteristics, each is a group of inverters designed to have different logic threshold voltages at substantially equal intervals. Intermediate stage inverters 21-24
Is for inverting each output of the inverters 11 to 14,
Each is designed to have the same channel size as the inverter 11. This makes it possible to digitize the analog sensor output. Output stage gates 31-34
Is an inverter that inverts the output of the inverter 21, and 32-34 are EXOR gates that input the outputs of the inverters 21-24 two by two. Among the 5-bit digital outputs V _{1 to} V ₅ , V ₁ is the output of the inverter 31, V
_{2 to} V ₄ are outputs of the EXOR gates 32 to 34, and V ₅ is an output of the inverter 24.

In this embodiment, by making the ratio W / L of the channel length L and the channel width W of the MOS transistors constituting each inverter different, the logical threshold voltage V _T of each inverter is equal by ΔV _T. It has been shifted. As an example, the PMOS on the pull-up side of the inverter 11
(P channel MOS) transistor has a channel width Wp of 11.7 μm and a channel length Lp of 3.6 μm.
It is as m. At this time, the pair of pull-down NMs
Channel width W of OS (N channel MOS) transistor
n is 7.1 μm, and its channel length Ln is 3.6.
μm. With respect to the other inverters 12, 13, 14, without changing Lp, Wn, Ln, only Wp is increased by 0.8 μm as shown in FIG.
Doubled to 1.6 μm), 12.5 μm, 14.1 μm
m, 14.9 μm. In this way, Wp is 0.8
By increasing by μm, when V _DD = 10V, the logic threshold voltage V _T of each inverter can be increased by about 60 mV.

The load CMOS inverter 3 has a feedback resistor R _F having an appropriate value connected between its output terminal and input terminal. This feedback resistor R _F can be formed by using polycrystalline silicon, and if it is set to about several KΩ, it becomes a countermeasure against transient current. However, if there is no problem in this point, it may be 0Ω. This load CM
The same Wp control is also performed for the OS inverter 3. In this case, the logical threshold value is set to an intermediate value between the inverters 12 and 13 of the A / D conversion circuit 2. That is, Wp of the load CMOS inverter 3 is set to 13.3 μm,
The logic threshold voltage V _T is placed in the middle of the inverters 12 and 13. FIG. 3 shows the input / output transfer characteristics of each inverter whose threshold is controlled in this way when the pressure is zero.

By designing the logic threshold value of the load CMOS inverter 3 in this way, the operation starting point of the A / D conversion circuit 2 can be automatically set. That is, the load CMO
The potential of the output terminal S of the S inverter 3 has a feedback resistance R _F between the input and output terminals in the zero state where no pressure is applied.
Since they are connected (about 10 KΩ), they are biased to the logical threshold voltage of the inverter 3. Therefore,
When the logical threshold is adjusted as shown in FIG. 3,
The output voltage of the inverters 11 and 12 becomes lower than V _DD / 2, and the output voltage of the inverters 13 and 14 becomes higher than V _DD / 2. Therefore, the digital output is V ₃ indicating this zero point.
= 1 (V _DD ), V ₁ = V ₂ = V ₄ = V ₅ = 0 (GND)
Becomes

On the other hand, when pressure is applied to the pressure sensor 1, the output changes as follows depending on the direction and the size thereof. First, assuming that downward pressure is applied as shown in FIG. 2B, the PM used as the pressure sensor 1
The carrier mobility of OS is lowered and the potential at the point S is lowered. As a result, the inverter 1 is initially set according to the amount of decrease.
The output voltage of the second and then the inverters 11 and 12 becomes larger than V _DD / 2, and in the former case V ₂ = 1, V
_A digital output of ₁ = V ₃ = V ₄ = V ₅ = 0 is obtained,
In the latter case, V ₁ = 1, V ₂ = V ₃ = V ₄ = V ₅ =
An output of 0 is obtained.

Contrary to this case, if upward pressure is applied, the PMO used as the pressure sensor 1 is used.
Since the carrier mobility of S increases, the potential at the point S increases. As a result, the inverter 1 is initially set according to the amount of increase.
The output voltage of inverters 13 and 14 of 3 and then becomes smaller than V _DD / 2. Therefore, in the former case, V
_{4 = 1, V 1 = V} 2 = V 3 = V 5 = 0 becomes a digital output is obtained, also in the latter case _{V 5 = 1, V 1 =} V 2 = V
_A digital output of ₃ = V ₄ = 0 is obtained.

As described above, the load CMOS inverter and the CMOS inverter for A / D conversion are associated with the dimensions of the PMOS and NMOS transistors forming them, and are relatively changed, so that the respective logic thresholds are changed. By controlling the voltage, the operation start point can be set accurately. This depends on other parameters that affect the characteristics of the CMOS inverter, such as the gate oxide film thickness and the MOS.
It is considered that the threshold voltage of the transistor and the carrier mobility of the channel are almost the same in the very vicinity of the integrated chip. This is because the change in the relative difference between the threshold values can be made extremely small.

FIG. 4 is a block diagram showing another embodiment of the present invention. In this embodiment, the load CMOS inverter 3 and A
An amplifier circuit 4 is interposed between the A / D conversion circuit 2 and the / D conversion circuit 2.
The amplifier circuit 4 is a CMOS inverter formed by the same design as the load CMOS inverter 3, and its logic threshold value is equal to the logic threshold value of the inverter 3. Therefore,
The zero point of the voltage at the input terminal T of the A / D conversion circuit 2 is automatically set to the logical threshold value of the inverter 3.

Such an amplifier circuit 4 has a load CM of the preceding stage.
Only the change in the voltage at the output terminal S of the OS inverter 3 is amplified and reflected in the voltage at the output terminal T. Therefore, even if the output of the sensor unit 1 is small, a sufficiently large input can be given to the A / D conversion circuit 2. The amplification degree of the amplifier circuit 4 is determined by the ratio R _G / R _S of the input resistance Rs and the feedback resistance R _G.
However, in order to reduce the influence of manufacturing variations of the inverters 3 and 4, it is preferable to set the amplification degree to about 20 dB. In particular, if the gain is reduced by feedback, the linearity can be expanded, and there is also an advantage that variations in element characteristics can be absorbed.

It is convenient to apply such an amplifier circuit 4 to the minute output acceleration sensor shown in FIG. The structure of this acceleration sensor is similar to that of a pressure sensor, but a weight body 53 is provided at the center of the lower surface of the diaphragm portion 50 so that it can respond to a small acceleration. However, even with such a sensor structure, the potential at the point S does not increase so much when an acceleration of about ± 1 G is applied (several mV).
degree). Therefore, this change is amplified by the amplifier circuit 4 and A
Input to the / D conversion circuit 2.

The present invention is not limited to the above embodiment. That is, in the embodiment, Wp that does not cause the short channel effect is changed to change ΔV _T in the above equation, but Lp, Wn, and Ln may be changed in some cases. In addition, although the sensor used only the PMOS transistor which constitutes the load CMOS inverter in the embodiment, the sensor type and the sensor can be changed as long as the sensitivity can be obtained by using only the NMOS transistor or both the PMOS and NMOS transistors. The method does not matter.

[0022]

As described above, according to the present invention, CM
It is possible to accurately set the operation start point of a simple semiconductor sensor with an A / D conversion circuit using an OS inverter, and further to make it possible to integrate the whole into one chip. Specifically, (1) a compact digital output type pressure sensor or acceleration sensor having a function of automatically adjusting the zero point can be realized by one chip. (2) The characteristics of the signal processing circuit are not significantly affected by manufacturing variations because the relative relationship is determined by changing only the channel width of the CMOS inverter that constitutes the signal processing circuit. (3) Therefore, improvement in production yield can be expected, and the temperature characteristics of the signal processing unit are also good. (4) Zero adjustment by laser trimming, which is conventionally required, is not necessary, and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a structural diagram of a pressure sensor.

FIG. 3 is an input / output transfer characteristic diagram of each inverter.

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

FIG. 5 is a structural diagram of an acceleration sensor.

[Explanation of symbols]

1 ... Mechanical quantity sensor (sensor section), 2 ... A / D conversion circuit,
3 ... Load CMOS inverter (operation start point setting unit), 4 ...
Amplifier circuits 11 to 14 ... CMOS inverters at the input stage,
21-24 ... CMOS inverters at intermediate stages, 31-34
... Output stage gate, 50 ... Si chip, 51 ... Diaphragm, _RF ... Feedback resistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication location H03M 1/34 9065-5J (72) Inventor Toshinbayashi 1-5-1, Kiba, Koto-ku, Tokyo No. Fujikura Electric Wire Co., Ltd. (72) Inventor Katsuno Shono 5-45-12 Shirane, Asahi-ku, Yokohama-shi, Kanagawa

Claims (3)

[Claims] 1. A sensor unit that responds to an external change, and an A / D conversion circuit that connects a plurality of CMOS inverters having different logic threshold values in parallel to convert the output of the sensor unit into a digital value. A load CMOS inverter having a logic threshold value controlled for setting an operation start point of the A / D conversion circuit, and the sensor section includes an operation start point setting section formed by sharing at least one element transistor, A semiconductor sensor characterized in that the sensor section, the A / D conversion circuit, and the operation start point setting section are formed on the same semiconductor substrate. 2. The semiconductor sensor according to claim 1, wherein the load CMOS inverter has input and output terminals connected by a feedback resistor. 3. An amplifier circuit composed of a CMOS inverter having the same logical threshold value as that of the operation start point setting section is interposed between the operation start point setting section and the A / D conversion circuit. The semiconductor sensor according to claim 1 or 2, which is characterized in that.