JPH05206002A - Alignment method and reduction projection - Google Patents

Abstract

PURPOSE:To reduce the error of alignment, by previously forming an alignment mark on the rear of a semiconductor substrate and applying an irradiation light to the mark and receiving the reflected light and the scattered light and aligning a mask with the semiconductor substrate. CONSTITUTION:The outer circumference of the rear of a semiconductor substrate 5 is attracted using a vacuum with a wafer chuck 10. A laser beam from an alignment optical system 7 is applied to an alignment mark 6 previously formed on the rear of the semiconductor substrate 5. The light reflected and scattered on the alignment mark 6 is received with the alignment optical system 7 and an alignment is performed by an alignment mechanism 9 through the output from the optical system 7. Then, when the alignment is completed and the semiconductor substrate 5 is positioned to a given place, a wafer stage 8 is fixed by attracting the wafer chuck 10 using a vacuum. Thus, the alignment can be performed accurately without a break of the edge of the alignment mark 6 or an unsymmetry.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for aligning a mask and a semiconductor substrate using an exposure apparatus used in the manufacturing process of LSI and the like, and a reduction projection exposure apparatus.

[0002]

2. Description of the Related Art FIG. 3 shows the construction of a conventional reduction projection exposure apparatus used in the manufacture of semiconductor devices.

The reduction projection exposure apparatus is an alignment optical system for detecting the positions of a light source 1 using a high pressure mercury lamp, a condenser lens 2, a reticle 3, a reduction projection lens 4, and an alignment mark 6 formed on the surface of a semiconductor substrate 5. 7
And a wafer stage 8, and an alignment mechanism 9 for performing alignment based on alignment data.

In the conventional alignment method used in the reduction projection exposure apparatus, the alignment mark 6 formed on the surface of the semiconductor substrate 5 is irradiated with illumination light, and the position of the alignment mark 6 is detected by image processing of the bright and dark image thereof. .

Alternatively, the alignment mark 6 is scanned with illumination light, and the position of the alignment mark is detected by the change in the reflected light intensity at the mark edge portion.

[0006]

In the above-mentioned conventional reduction projection exposure apparatus (hereinafter referred to as stepper), the alignment mark 6 is formed every time the semiconductor manufacturing process progresses and various films are formed on the semiconductor substrate 5. The edges are asymmetrical, which makes accurate alignment difficult.

Further, there is a case where alignment is performed at a position deviated from the original alignment position. As described above, there is a problem in alignment accuracy.

Further, due to the difference in the thermal expansion coefficient between the semiconductor substrate 5 during exposure and the stage 8 of the stepper, a scaling error occurs when exposing the vicinity of the outside of the semiconductor substrate. Therefore, there is a problem in that the alignment accuracy is deteriorated.

When the alignment mark 6 is formed on the surface of the semiconductor substrate 5, it is necessary to select a position or a blank area having a limited range which does not affect the performance of the semiconductor device manufactured on the surface of the semiconductor substrate 5. Or, it was necessary to newly provide a blank part.

[0010]

The present invention comprises a step of forming an alignment mark in advance on the back surface of a semiconductor substrate in the step of exposing a semiconductor substrate coated with a resist by aligning the mask with the semiconductor substrate coated with a resist. An alignment method is characterized by including a step of irradiating a mark with illumination light, receiving reflected light and scattering of the light, and performing alignment between a mask and a semiconductor substrate by a difference in brightness and the like.

Further, the reduction projection exposure apparatus of the present invention includes a light source for irradiating an alignment mark formed in advance on the back surface of a semiconductor substrate with illumination light, a light receiving element for receiving the reflected light or scattered light, and a difference in brightness between the light and the light. It is a reduction projection exposure apparatus having a function of aligning a mask and a semiconductor substrate by means of the above.

[0012]

By using the alignment method and the reduced projection exposure apparatus of the present invention, it is possible to reduce the misalignment of the alignment mark and the misalignment due to the difference in the thermal expansion coefficient between the semiconductor substrate and the wafer stage.

[0013]

1 shows the structure of a reduction projection exposure apparatus used in the manufacture of a semiconductor device of the present invention.

The exposure apparatus of the present invention uses the position data detected from the light source 1 using a high pressure mercury lamp, the condenser lens 2, the reticle 3, the reduction projection lens 4, the wafer stage 8, the alignment optical system 7 and its optical elements. It is composed of an alignment mechanism 9 for performing accurate alignment.

The wafer stage 8 is fixed to the exposure optical system, and the alignment optical system 7 for detecting the position of the alignment mark 6 on the back surface of the semiconductor substrate is fixed to the wafer stage 8.

The wafer chuck 10 has a mechanism that moves horizontally with respect to the exposure optical system and a mechanism that vacuum-sucks the semiconductor substrate 5.

FIG. 2 shows a conceptual diagram of an alignment method using the back surface of the semiconductor substrate of the present invention.

The wafer chuck 10 vacuum-sucks the outer peripheral portion of the back surface of the semiconductor substrate 5. Then, using the alignment mark 6 created in advance on the back surface of the semiconductor substrate, laser light is emitted from the alignment optical system 7 and the light reflected and scattered by the alignment mark 6 is received by the optical system 7.
The alignment mechanism 9 performs alignment based on the output. At this time, the vacuum suction of the wafer stage 8 is not performed, and the semiconductor substrate 5 is fixed by the wafer chuck 10. Here, the wafer chuck 10 is moved and the alignment optical system 7 performs alignment.

After the alignment is completed and the semiconductor substrate 5 is positioned at the fixed position, the wafer stage 8 fixes the wafer chuck 10 by vacuum suction.

In this alignment method, after exposure, the wafer stage 8 is evacuated to release the suction of the semiconductor substrate 5.

The semiconductor substrate 5 adsorbed on the wafer chuck 10 is sent to the next step, where the alignment is similarly performed, and the semiconductor substrate is adsorbed and exposed.

By repeating this, the entire surface of the semiconductor substrate 5 is exposed. Alignment mark 6 on the back surface of the semiconductor substrate 5
The alignment accuracy of the semiconductor substrate 5 that has undergone the semiconductor manufacturing process is
The occurrence of alignment errors due to edge marks on the alignment marks and asymmetry on the left and right sides is eliminated.

Further, since the alignment is performed for each shot, the scaling error amount due to the difference in thermal expansion coefficient between the semiconductor substrate and the wafer stage is reduced to 1/2.

In addition, in the above-described embodiment, when the alignment mark is formed on the surface of the semiconductor substrate, a margin with a limited position or range that does not affect the performance of the semiconductor device manufactured on the surface of the semiconductor substrate. It was necessary to select the part or set the margin part,
By using the back surface of the semiconductor substrate, the degree of freedom in creating the alignment mark increases.

[0025]

When the reduction projection exposure apparatus of the present invention and the alignment method using the alignment mark formed on the back surface of the semiconductor are used, the edge of the alignment mark and the left-right asymmetry are not affected by the thin film formed by the semiconductor manufacturing process. Without it, alignment can be done very accurately.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an alignment mechanism of a reduction projection exposure apparatus of the present invention.

FIG. 2 is a flowchart showing an alignment method of the present invention.

FIG. 3 is a configuration diagram showing an alignment mechanism of a conventional reduction projection exposure apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Light source (mercury lamp) 2 Condenser lens 3 Reticle 4 Reduction projection lens 5 Semiconductor substrate 6 Alignment mark 7 Alignment optical system 8 Wafer stage 9 Alignment mechanism 10 Wafer chuck

Claims (2)

[Claims] 1. A semiconductor substrate and an alignment mark formed on the back surface of the semiconductor substrate, irradiating the mark with illumination light and receiving reflected light and scattered light, and the mask and the semiconductor substrate due to the difference in brightness. An alignment method comprising the step of performing alignment with. 2. A semiconductor substrate having an alignment mark on its back surface, a light source for exposing the semiconductor substrate, a condenser lens through which light from the light source passes, and a reticle through which light passing through the condenser lens passes. A reduction projection lens that reduces the light passing through the reticle, a wafer stage that supports the semiconductor substrate, an alignment detection system that detects the alignment mark, and an alignment mechanism that operates based on the data of the alignment detection system. And a reduction projection exposure apparatus.