JPH05190816A - Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the logic correction of a semiconductor integrated circuit device. CONSTITUTION:When the wiring layout of a semiconductor integrated circuit device having a multilayer wiring layer is designed, the following steps are performed. At first, all input/output terminals of all logic gates, which are laid out in each chip region of a semiconductor wafer by a plurality of numbers, are lifted up to the uppermost signal wiring layer or to the signal wiring layer immediately beneath the uppermost layer by way of through holes under the state wherein the terminals are arranged in the vertical state as much as possible 101. Then, the layout of the wiring for connecting the logic gates is performed 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technology, and more particularly,
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a multilayer wiring layer.

[0002]

2. Description of the Related Art A logic LSI such as a microprocessor or a gate array is often modified in its logic configuration (logic modification) during its development.

The logic correction is performed by changing the route of the wiring connecting the logic gates or the logic blocks, or interposing a spare gate between the logic gates.

However, if the logic correction is performed by changing the wiring mask pattern, the LSI development period becomes long,
The delivery date will be significantly delayed.

Therefore, in recent years, a so-called on-chip correction technique for correcting logic or the like on a completed semiconductor chip by using a focused ion beam or the like and laser CVD or the like has been developed and put into practical use (for example, Japanese Laid-Open Patent Publication Sho 62-22995
No. 6).

This is because a part of the insulating film on the semiconductor wafer is removed by a focused ion beam or the like to expose a wiring portion to be cut, and the wiring cut portion is cut by a focused ion beam or the like, and a new Laser line C
This is a technique for performing logical correction by forming it by VD or the like.

By the way, in the on-chip repair, it is physically impossible to process or it is difficult to secure the yield due to the presence of adjacent wiring, upper wiring and electrodes. There is.

Therefore, there is a technique for facilitating on-chip correction processing by previously providing a spare wiring between the wirings connecting the logic gates (for example, Japanese Patent Laid-Open No. 62-2).
98134).

Further, when designing the layout of the wiring, for example, the spacing between the wiring patterns in a predetermined area can be expanded (wiring pattern spacing expansion function), or the wiring pattern portion in the predetermined area can be pulled up to the upper layer (wiring pattern upper layer pulling up). There is a technology for facilitating processing at the time of on-chip correction by performing the function.

Regarding the wiring pattern interval expanding function and the wiring pattern pulling up function, for example, the 42nd (the first half of 1991) National Convention of the Information Processing Society of Japan 5J-6 "L"
SI repair pattern shaping system "P224 to P225.

[0011]

However, in the prior art for providing the above-mentioned preliminary wiring and the prior art for expanding the wiring pattern interval in designing the wiring layout and for pulling up the wiring pattern portion to the upper layer, on-chip Although the easiness of correction is improved, there is a problem that the channel is wasted.

Further, for example, in a logic LSI such as a gate array, there is a demand for using a terminal that has been set as an unused terminal of the logic gate when correcting the logic after the wafer process. May occur.

However, since the setting of conditions for making unused terminals is performed in the lower wiring layer on the semiconductor substrate, it is impossible to switch the unused terminals to usable by the conventional on-chip correction. There was a problem that there was.

Conventionally, as a method of coping with such a demand, there is a method of incorporating a spare gate into a semiconductor integrated circuit by an on-chip correction technique instead of a logic gate having an unused terminal. There is a problem that the processing amount required for the processing increases and processing takes time.

Further, in the case of this method, since it also leads to an increase in the number of spare gates, it hinders high integration and also causes a problem that the power consumption of the semiconductor integrated circuit device increases. The reason for increasing the power consumption is that the spare gates that are not used are usually supplied with power.

The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of facilitating logic correction in a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of reducing the logic correction time of a semiconductor integrated circuit device and improving the processing yield.

Another object of the present invention is to provide a technique for reducing the waste of channels in the technique for facilitating the logic modification of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of easily setting unused terminals of logic cells constituting a semiconductor integrated circuit device to a usable state even after a wafer process.

Another object of the present invention is to provide a technique capable of improving the degree of element integration of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of reducing the power consumption of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0023]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the first aspect of the invention, when designing a wiring layout of a semiconductor integrated circuit device having a multilayer wiring layer,
Priority was given to the layout process of pulling up to the uppermost signal wiring layer or the signal wiring layer immediately below it with all terminals of all logic cells laid out in the chip area being as vertical as possible by the connection hole paths. After that, it is a method of manufacturing a semiconductor integrated circuit device, which performs a layout process of wiring for connecting the logic cells.

According to a second aspect of the present invention, all terminals of all logic cells formed on a semiconductor substrate are arranged on the uppermost signal wiring layer or the signal wiring layer immediately below the uppermost signal wiring layer in a state as vertical as possible by the connection hole paths. The pull-up input terminal is used by short-circuiting or opening a predetermined pull-up input terminal among the pull-up terminals formed by pulling up and a wiring of a predetermined potential formed on the uppermost signal wiring layer or the layers immediately above and below it. A method of manufacturing a semiconductor integrated circuit device, which switches to an impossible state or a usable state.

A third aspect of the invention is to cut the conductor pattern for electrically connecting the predetermined pull-up input terminal of the second invention and the wiring of the predetermined potential with an energy beam, thereby the predetermined pull-up input terminal. Is a method for manufacturing a semiconductor integrated circuit device, which switches a state from an unusable state to an usable state.

A fourth aspect of the invention is to electrically connect the predetermined pull-up input terminal of the second aspect of the invention and the wiring of the predetermined potential by a conductor pattern formed by a photo-CVD method, to thereby perform the predetermined pull-up. A method for manufacturing a semiconductor integrated circuit device, which switches an input terminal from a usable state to an unusable state.

According to a fifth aspect of the invention, all the terminals of all the logic cells formed on the semiconductor substrate are arranged in the uppermost signal wiring layer or the signal wiring layer immediately below the signal wiring layer as vertically as possible by the connection hole paths. A semiconductor for switching a predetermined pull-up output terminal to a usable state or a non-usable state by short-circuiting or opening a predetermined pull-up output terminal and a pull-up terminal having a predetermined potential among pull-up terminals formed by pulling up A method for manufacturing an integrated circuit device.

According to a sixth aspect of the invention, all the terminals of all the logic cells formed in plural on the semiconductor substrate are arranged in the uppermost signal wiring layer or the signal wiring layer immediately below the signal wiring layer as vertically as possible by the connection hole paths. Of the pull-up terminals formed by pulling up, select the short-circuit / open between the pull-up control terminal that controls the operation / non-operation of the logic cell and the wiring of a predetermined potential formed on the uppermost signal wiring layer or the layers directly above and below it. By doing so, it is a method of manufacturing a semiconductor integrated circuit device, which switches between operation and non-operation of the logic cell.

[0030]

According to the above-mentioned first invention, since the terminals of the logic cell are pulled up to the uppermost signal wiring layer, processing for changing the connection path between the logic cells by on-chip modification, for example, the logic cell It is possible to easily open a hole reaching the terminal and to embed the hole with a conductor, and in a short time.

Further, since the terminals of the logic cell are pulled up in a substantially vertical state, a conventional wiring is provided, a wiring pattern interval is enlarged in wiring layout processing, or a predetermined wiring pattern portion is pulled up. It is possible to reduce the waste of channels as compared with.

According to the above-mentioned second and third inventions, for example, a predetermined input terminal set as an unused terminal of a logic cell can be easily and quickly processed by the on-chip correction technique even after the wafer process is completed. It is possible to switch to a usable state with.

According to the above-mentioned fourth invention, for example, it becomes possible to switch the usable input terminals of the logic cells to the unusable state easily and in a short time even after the wafer process is completed.

According to the above fifth invention, for example, a predetermined output terminal set as an unused terminal of a logic cell can be used easily and in a short time by the on-chip correction technique even after the wafer process is completed. It is possible to switch to a different state.

According to the above-described sixth invention, for example, by switching the unused spare gate to the non-operating state by the on-chip correction technique, it becomes possible to stop the power supply to the spare gate.

[0036]

First Embodiment FIG. 1 is a flow chart showing a layout process in a wiring layout design of a semiconductor integrated circuit device which is an embodiment of the present invention, and FIG. 2 is a wiring layout design created by the wiring layout process of FIG. Explanatory drawing which shows typically the principal part cross section of the semiconductor integrated circuit device formed based on the data, FIG. 3 is explanatory drawing which shows typically the upper surface of FIG. 2, FIG. 4 is the semiconductor integrated circuit device after the logic correction process. 5 is an explanatory view schematically showing the upper surface of FIG. 5, FIG. 5 is a sectional view taken along the line AA of FIG. 4, and FIG. 6 is an explanatory view schematically showing a sectional view of a main part of the semiconductor integrated circuit device after the logic correction processing. ..

The method of manufacturing the semiconductor integrated circuit device of the first embodiment will be described below by taking the manufacture of a semi-custom product such as a gate array as an example.

First, the wiring layout process will be described. The wiring layout processing is a layout processing on a computer for wiring that connects between logic gates (logic cells) laid out in a chip area of a semiconductor wafer (semiconductor substrate) described later.

The logic gate is, for example, an AND circuit, NAN.
D circuits, OR circuits, NOR circuits, etc., which are basic logic circuits constituting a gate array to be manufactured,
A plurality of integrated circuit elements, such as transistors and resistors, in a plurality of basic cells regularly laid out in the chip area are formed by being connected by in-cell wiring.

In the first embodiment, the wiring layout process is performed along steps 101 and 102 of FIG.

First, all the input / output terminals of all the logic gates laid out in the lowermost layer are as vertical as possible by through holes (connection hole paths), and the uppermost signal wiring layer or the signal wiring immediately below it. The layers are preferentially raised (step 101).

Subsequently, wiring for connecting the logic gates is
For example, the layout is performed by a maze method, a channel method, a route search method, or the like, and wiring layout design data of a gate array having a predetermined logical configuration is created (step 102).

Next, the logic correction of the gate array formed in the chip area of the semiconductor wafer based on the wiring layout design data will be described with reference to FIGS.

In the first embodiment, as shown in FIG. 2, for example, six wiring layers 1 to 6 are formed on the semiconductor wafer W.

The wiring layer 1 is a signal wiring layer for in-cell wiring forming the logic gate 7, and the wiring layer 1 is also formed with an input terminal 8a ₁ and an output terminal 8b ₁ of the logic gate 7.

The wiring layers 2 to 5 are wiring layers for power supply wiring for supplying a power supply voltage to the signal wiring or the logic gate 7 for connecting the logic gates 7 to each other. 2 and 3
In order to make the drawing easy to see, only the signal wiring 9a connecting between the logic gates 7a and 7b is schematically shown in FIG.

The wiring layer 6 is a wiring layer dedicated to power supply wiring. FIG. 3 shows the power supply wiring 10 of the wiring layer 6. Power supply wiring 1
0 is almost a solid pattern. In addition, 1 in FIG.
Reference numeral 1 indicates an empty area where the power supply wiring 10 does not exist.

In the first embodiment, all the input terminals 8a ₁ and the output terminals 8b _{1 of} all the logic gates 7 are formed in the wiring layer 5 which is the uppermost signal wiring layer through the through holes (connection hole paths) 12. Pulled up input terminal 8a ₂
And is electrically connected to the pull-up output terminal 8b ₂ . That is, the input terminal 8a ₁ and the output terminal 8b ₁ of the logic gate 7 are pulled up to the wiring layer 5 by the through holes 12 in a substantially vertical state.

In order to make the drawing easier to see, FIG.
Predetermined input terminal 8a ₁ and output terminal 8 of logic gate 7
Only the raised state of b ₁ is shown.

The wirings and input / output terminals of the wiring layers 1 to 6 are made of aluminum (Al) or Al alloy such as Al-silicon (Si) -copper (Cu).

An interlayer insulating film 13 is formed between the wiring layers 1-6. Further, in the upper layer of the wiring layer 6,
The surface protection film 14 is formed. The interlayer insulating film 13 and the surface protective film 14 are made of, for example, silicon dioxide (SiO ₂ ).
Consists of.

In the first embodiment, for example, the wiring path between the logic gates 7a and 7b is cut by using a focused ion beam (hereinafter, referred to as FIB), and the logic gates 7a and 7c are used instead. Laser CVD between
The logical correction for connecting by the conductor pattern formed by will be described.

The entire structure of the on-chip wiring correction technique using FIB and laser CVD is disclosed in, for example, Japanese Unexamined Patent Publication No. 3-25956, and it is made a part of the description of the present application.

First, as shown in FIGS. 4 and 6, the signal wiring 9a connecting between the logic gates 7a and 7b is cut by FIB or the like. At this time, the irradiation position of the FIB is the empty area 1 between the power supply wirings 10 formed in the wiring layer 6.
Set to 1.

Then, as shown in FIG. 4 and FIG.
The groove 15 is formed by IB or the like.

Thus, the power supply wiring 10 is positioned above the pull-up output terminal 8b ₂ from the logic gate 7a and the pull-up input terminal 8a ₂ from the logic gate 7c (not shown in FIGS. 4 and 5). The isolated pattern 10a is formed in the portion to be used.

This is to prevent a short circuit defect between the signal wiring newly formed by laser CVD described later and the power supply wiring 10 formed in the wiring layer 6.

Thereafter, the pull-up output terminal 8b ₂ of the logic gate 7a and the logic gate 7 are provided from above the semiconductor wafer W.
FIB is irradiated to the position of the pull-up input terminal 8a ₂ of c,
The surface protection film 14, the isolated pattern 10a and the interlayer insulating film 13 in the irradiated portion are removed and the output terminal 8b ₂ is pulled up.
And holes 16a, 1 through which the pull-up input terminal 8a ₂ is exposed
6b (see FIG. 6) is formed.

Next, a conductor 17a made of tungsten or the like is embedded in the one hole 16a by, for example, laser CVD, and then a conductor pattern 17b is formed on the surface protective film 14 along the scanning line of the laser beam, and further. The conductor 17a is continuously embedded in the other hole 16b in the same manner as the hole 16a, and a new signal wiring 17 for electrically connecting the logic gates 7a and 7c is formed to complete the logic correction work.

As described above, in the first embodiment, the following effects can be obtained.

(1). All input terminals 8a ₁ of the logic gate 7
Since the output terminal 8b ₁ and the output terminal 8b ₁ are pulled up to the uppermost wiring layer 5, the logic gates 7,
Processing for changing the connection path between them, for example, the hole 1 reaching the pull-up input terminal 8a ₂ and the pull-up output terminal 8b _2.
Formation of 6a and 16b and conductor 17 of the holes 16a and 16b
It becomes possible to easily embed with a, etc. in a short time.

Therefore, it is possible to shorten the development period of a gate array having a predetermined logic circuit configuration without causing a reduction in yield due to logic correction.

(2). Since the input terminal 8a ₁ and the output terminal 8b ₁ of the logic gate 7 are pulled up in a substantially vertical state,
It is possible to reduce the waste of channels as compared with the prior art in which a preliminary wiring is provided, a wiring pattern interval is enlarged in the wiring layout process, or a predetermined wiring pattern portion is pulled up.

[0064]

Second Embodiment FIG. 7 is an explanatory view schematically showing a cross section of a main part of a semiconductor integrated circuit device formed based on wiring layout design data created by a wiring layout process according to another embodiment of the present invention. FIG. 8 is an explanatory view schematically showing a cross-sectional view of a main part of the semiconductor integrated circuit device of FIG. 7 after the logic correction processing.

In the second embodiment, the wiring layout process is performed as follows.

First, a pair of terminals from all the input / output terminal positions of all the logic gates laid out on the lowermost layer and the positions in the vicinity thereof are arranged as vertically as possible by through holes, and the uppermost signal wiring layer or directly under it. Priority is given to the signal wiring layer.

Subsequently, wiring for connecting the logic gates is
For example, the layout is performed by a maze method, a channel method, a route search method, or the like, and wiring layout design data of a gate array having a predetermined logical configuration is created.

Next, the logic correction of the gate array formed in the chip area of the semiconductor wafer based on the wiring layout design data will be described with reference to FIGS.

In the second embodiment, as shown in FIG. 7, the output terminal 8b ₁ of the logic gate 7a and the terminal 8c _{1 in the} vicinity of the output terminal 8b ₁ are pulled up by the through holes 12 in a substantially vertical state, and the wiring layers are respectively formed. 5 are electrically connected to the lifting terminals 8a ₂ and 8c ₂ .

The input terminal 8a ₁ of the logic gate 7b and the terminal 8d _{1 in the} vicinity thereof are also pulled up by the through hole 12 in a substantially vertical state, and are electrically connected to the pulling terminals 8b ₂ and 8d ₂ of the wiring layer 5, respectively. It is connected to the.

In the second embodiment, the pull-up terminals 8b ₂ and 8c ₂ are electrically connected by the signal wiring 9b, and the terminals 8c ₁ and 8d ₁ are electrically connected by the signal wiring 9c. , Lifting terminal 8d ₂ , 8
The signal line 9d electrically connects a ₂ and the logic gates 7a and 7b are electrically connected.

Here, as in the first embodiment, the wiring path between the logic gates 7a and 7b is cut off and the logic gates 7a and 7b are disconnected.
The logic modification for connecting 7c will be described.

The method of logic correction is the same as in the first embodiment. That is, as shown in FIG.
After disconnecting each d by FIB, logic gate 7
The holes 16a and 16b through which the pull-up output terminal 8b _{2 of a} and the pull-up input terminal 8a ₂ of the logic gate 7c are exposed are F.
It is formed by IB or the like.

Subsequently, the conductor 17a is embedded in the one hole 16a by laser CVD, and subsequently, the conductor pattern 17b is formed on the surface protection film 14 along the scanning line of the laser beam, and the other hole 16b is formed. Is embedded by the conductor 17a, a new signal wiring 17 is formed, and the logic correction work is completed.

Therefore, also in the second embodiment, the same effect as that of the first embodiment can be obtained.

Further, in the case of the second embodiment, it is possible to modify the logic by changing the wiring pattern of the wiring layer 5. In this case, only the mask pattern forming the wiring pattern of the wiring layer 5 needs to be changed in the logic correction.

Therefore, in the logic correction, the wiring layer 2
The logic correction can be performed more easily and in a shorter time than in the case where the mask patterns of 5 to 5 are changed.

[0078]

[Embodiment 3] FIG. 9 is an explanatory view schematically showing a cross section of a main part of a semiconductor integrated circuit device formed on the basis of wiring layout design data created by a wiring layout process according to another embodiment of the present invention. FIG. 10 shows FIG. 9 after the logic correction processing.
FIG. 3 is an explanatory view schematically showing a cross-sectional view of a main part of the semiconductor integrated circuit device of FIG.

In the third embodiment, the wiring layout process is performed as follows.

First, the wiring connecting the logic gates is laid out by, for example, the maze method, the channel method or the route search method.

Next, of the signal wiring between the logic gates,
In the middle position of the signal wiring laid out below the wiring layer 5, one terminal is set at a position where there is no obstruction, and the terminal is made almost vertical by a through hole, or the uppermost signal wiring layer or directly under it. To the signal wiring layer. In this way, the wiring layout design data of the gate array having the predetermined logical configuration is created.

Next, logic correction of the gate array formed in the chip area of the semiconductor wafer based on the wiring layout design data will be described with reference to FIGS.

In the third embodiment, as shown in FIG. 9, the terminal 8e _{1 is provided in} the middle of each of the signal wiring 9e connecting the logic gates 7a and 7b and the signal wiring 9f connecting the logic gates 7c and 7d. , 8f ₁ are formed, and their terminals 8e ₁ , 8f ₁ are pulled up by the through holes 12 in a substantially vertical state and electrically connected to the pulling terminals 8e ₂ , 8f ₂ of the wiring layer 5.

Here, in the third embodiment, the wiring paths between the logic gates 7a and 7b and between the logic gates 7c and 7d are cut, and instead, the logic gates 7a and 7d.
The on-chip correction for connecting the two will be described.

First, as shown in FIG. 10, a signal wiring 9e between the terminal 8e ₁ and the input terminal 8a ₁ of the logic gate 7b.
Part and terminal 8f ₁ and input terminal 8f of logic gate 7d
The signal wiring 9f portion between ₁ and ₁ is cut by FIB or the like.

Subsequently, holes 16a and 16b through which the pull-up terminals 8e ₂ and 8f ₂ are exposed are formed by FIB or the like, and then a new signal wiring 17 is formed by laser CVD as in the case of the first embodiment, and a logic signal is formed. Finish the correction work.

Therefore, also in the third embodiment, the same effect as that of the first embodiment can be obtained.

[0088]

[Fourth Embodiment] FIG. 11 is an explanatory view showing logic symbols of logic gates constituting a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 12 is an explanatory view schematically showing the logic gates of FIG. 13 is a plan view of the semiconductor integrated circuit device of FIG. 12, FIG. 14 is a cross-sectional view of an essential part of a semiconductor substrate, FIG. 15 is an explanatory view schematically showing the logic gate of FIG. 12, and FIG. 16 is a logic after on-chip modification. FIG. 17 is an explanatory view schematically showing the gate, and FIG. 17 is a cross-sectional view of a main part of the semiconductor substrate of FIG. 14 after on-chip correction.

In the fourth embodiment, a method of switching a 2-input / unipolar-output logic gate to a 3-input / bipolar-output logic gate by on-chip modification will be described with reference to FIGS. 11 to 17.

FIG. 11 is a logic symbol of the logic gate 7 for explaining the fourth embodiment. The logic gate 7, for example, the input terminal IN ₁ to IN ₃ and the output terminal OR, is provided with the NOR, 11, the input terminal IN ₃ of which
And the output terminal OR is in an unusable state, that is,
Indicates that it is set as an unused pin.

A schematic diagram of the logic gate 7 for setting as shown in FIG. 11 is shown in FIG. Further, a plan view of FIG. 12 is shown in FIG. Further, FIG. 14 shows a cross-sectional view of the main part of FIG.

The logic gate 7 is an ECL (Emitter Coupled Logi) having bipolar transistors Q _{1 to} Q _7.
c) It is composed of circuits.

In FIG. 12, the input of the logic gate 7 (that is, the bases of the transistors Q _{1 to} Q ₃ ) and the logic gate 7 are shown.
Output (i.e., the emitter of the transistor Q _6, Q ₇₎
, The terminal of the predetermined potential V _TT and the base of the transistor Q ₅ are pulled up to the uppermost signal wiring layer by the through hole 12 (see FIG. 2) in a substantially vertical state, and the pull-up input terminals 8 _IN1 to 8 _IN3 are pulled up, respectively. It is shown that the output terminals 8 _OR and 8 _NOR are electrically connected to the pull-up terminals 8 _E1 and 8 _E2 and the pull-up terminal (pull-up control terminal) 8 _CS .

Of the pull-up input terminals 8 _IN1 to 8 _IN3 ,
Pull-up input terminal 8 _IN3 is wiring (conductor pattern) 18
Is electrically connected to the low level wiring (wiring of a predetermined potential) 19 through. As a result, the input terminal IN ₃ of the logic gate 7 is set as an unused terminal.

[0095] The pulling input terminal 8 _IN3, without open, reasons connected to the Low-level interconnect 19, when left open the pulling input terminal 8 _IN3, the collector of the transistor Q ₃ - leakage current flows between the base, This is because the transistor Q _3, which should not be used, operates.

Conventionally, when the input terminal IN ₃ is an unused terminal, for example, the base-emitter of the transistor Q ₃ is connected by a lower layer wiring.

The low-level wiring 19 is made of, for example, Al or Al-Si-Cu alloy, and is formed in the wiring layer 4 immediately below the wiring layer 5 having the pull-up input terminal 8 _IN3 , as shown in FIG. ing. The low level wiring 19 is set to about -1.5V, for example.

The wiring 18 connecting the low level wiring 19 and the pull-up input terminal 8 _IN3 is made of, for example, Al or Al-Si-Cu alloy, and is formed on the wiring layer in which the pull-up input terminal 8 _{IN 3} is formed. It is formed at the same time when the wiring of the wiring layer is patterned.

On the other hand, of the pull-up output terminals 8 _OR and 8 _NOR , the pull-up output terminal 8 _NOR is electrically connected to the pull-up terminal 8 _E1 of the predetermined potential V _TT through the wiring 20. As a result, the output terminal NOR of the logic gate 7 is set in a usable state.

The wiring (conductor pattern) 20 is made of, for example, Al.
Alternatively, it is made of an Al-Si-Cu alloy and has a lifting terminal 8
_In the wiring layer in which _E1 is formed, it is formed at the same time when the wiring of the wiring layer is patterned. The predetermined potential V
_TT is set to about -2V, for example.

The pull-up output terminal _8OR is open. As a result, the output terminal O of the logic gate 7
R is set to an unused terminal.

The pull-up terminal (pull-up control terminal) 8 _CS pulled up from the base of the transistor Q ₅ is electrically connected to the wiring V _CS having a predetermined potential through the wiring (conductor pattern) 21. As a result, the transistor Q ₅
Is set to be operable.

The pull-up terminal 8 _CS and the wiring V _{CS of a} predetermined potential
The wiring 21 for connecting with, for example, Al or Al-Si
It is made of a Cu alloy and is formed at the same time when the wiring of the wiring layer is formed on the wiring layer in which the pulling terminal 8 _CS is formed.

It should be noted that R _{C1 to} R in FIGS.
_C4 is a collector resistance. Further, R _E1 , R _E2 and R ₁ are resistors. V _CC is a collector potential, for example, GN
It is set to the D potential (0V). V _EE is an emitter potential and is set to, for example, about -4V. Also,
V _BB is the reference potential.

The semiconductor wafer W shown in FIG. 14 is made of, for example, p-type Si single crystal. The transistor Q ₃ has a collector buried layer 22, a collector layer 23, and a base layer 24.
And an emitter layer 25. The collector buried layer 22 contains, for example, antimony (S
b) or arsenic (As) has been introduced. The collector layer 23 is an n-type S formed by an epitaxial method or the like.
i consisting of a single crystal. Boron or the like, which is a p-type impurity, is introduced into the base layer 24. For example, As or phosphorus, which is an n-type impurity, is introduced into the emitter layer 25.

FIG. 15 schematically shows the three-dimensional structure of the logic gate 7 which is set to have such two inputs and one pole output.
In order to switch from this state to a logic gate with three inputs and bipolar outputs by the on-chip correction technique, the following is done.

First, in order to switch the input terminal IN ₃ of the logic gate 7 to the usable state, as shown in FIGS. 16 and 17, the wiring 18 connecting the pull-up input terminal 8 _IN3 and the low level wiring 19 is connected. Cut by FIB etc. As a result, the input terminal IN ₃ of the logic gate 7 is switched to the usable state.

Then, after forming a hole 16c (see FIG. 17) through which the pull-up input terminal 8 _IN3 is exposed, the first embodiment described above is used.
Similarly, the hole 16c is formed in the conductor 17a by laser CVD.
Then, the conductor pattern 17b is formed along the scanning line of the laser beam, and a new signal wiring 17 is formed.

Further, the output terminal O of the logic gate 7 in FIG.
To switch R to a usable state, as shown in FIG. 16, after forming a hole (not shown) through which the pull-up output terminal 8 _OR and the pull-up terminal 8 _E2 are exposed, between the terminals 8 _OR and 8 _E2. The wiring 21 made of tungsten or the like may be formed on the substrate by laser CVD and the terminals 8 _OR and 8 _E2 may be connected to each other.

In the fourth embodiment, the logic gate 7 is set to the inactive state by cutting the wiring 21 connecting the pull-up terminal 8 _CS and the wiring V _CS having a predetermined potential with FIB or the like. Is possible.

By applying this to an unused spare gate (not shown) formed on the semiconductor wafer W, the power consumption of the gate array can be reduced.

Conventionally, since power is also supplied to spare gates that are not used, there is a problem that the power consumption of the gate array also increases as the number of spare gates increases. This is because the power supply to the gate can be stopped.

As described above, according to the fourth embodiment, the following effects can be obtained.

(1). The predetermined input terminal IN ₃ set to the unused terminal of the logic gate 7 is easily switched to the usable state in a short time by the on-chip correction technique even after the end of the wafer process. It becomes possible.

(2) The predetermined output terminal OR set to the unused terminal of the logic gate 7 can be easily switched to the usable state in a short time by the on-chip correction technique even after the completion of the wafer process. Is possible.

(3). Since the number of spare gates can be reduced by the above (1) and (2), the degree of element integration of the semiconductor integrated circuit device can be improved.

(4). By switching the unused spare gate to the non-operating state by the on-chip correction technique, the power supply to the spare gate can be stopped.
It is possible to reduce the power consumption of the semiconductor integrated circuit device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments 1 to 4 and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, although the case where one input terminal of the logic gate is set as an unused terminal from the beginning has been described in the fourth embodiment, the present invention is not limited to this.
For example, in the steps up to the wafer process, all the input terminals of the logic gate are made available, and after the completion of the wafer process, a predetermined pull-up input terminal of the logic gate and L
The ow level wiring may be connected by an on-chip correction technique using FIB and laser CVD, and its input terminal may be switched to an unused terminal.

Further, in the fourth embodiment, the case where only one output terminal of the logic gate is set to the unused terminal from the beginning has been described, but the present invention is not limited to this, and for example, up to the wafer process. In the stage, all output terminals of the logic gate were set to unused terminals, and after the wafer process was completed, a predetermined pull-up input terminal of the logic gate and a wiring of a predetermined potential were formed by FIB and laser CVD. It is also possible to connect by on-chip correction technology and switch the output terminal to a usable state.

In the steps up to the wafer process, the pull-up terminal for controlling the operation / non-operation of the logic gate is opened, that is, the logic gate 7 is set in the non-operation state, and after the wafer process is completed, the FIB and the laser C are
By connecting the pull-up terminal for control and the wiring of a predetermined potential by the on-chip correction technique using VD,
It is also possible to switch the logic gate to an operable state.

In the fourth embodiment, the case where the present invention is applied to the method for manufacturing the semiconductor integrated circuit device having the logic gate constituted by the ECL circuit has been described. However, the present invention is not limited to this and can be variously applied. It is also possible to apply the present invention to other semiconductor integrated circuit device manufacturing methods such as a semiconductor integrated circuit device manufacturing method having a logic gate configured by a CMOS circuit.

In the first to fourth embodiments, one logic gate is described as one logic cell, but the present invention is not limited to this, and various modifications are possible, for example, four logic cells. The gate may be set as one logic cell.

In the above description, the case where the invention made by the present inventor is mainly applied to the method of manufacturing a semi-custom product such as a gate array, which is the field of application in the background, has been described, but the invention is not limited to this. However, the present invention can be applied to various methods, for example, a method of manufacturing a standard cell, a method of manufacturing a general-purpose logic LSI such as a microprocessor, and the like, and a method of manufacturing another semiconductor integrated circuit device.

In this case, such as a register array, flip-flop, adder or ALU (Arithmetic Logic Unit) in which basic logic gates such as AND, NAND, OR etc. are assembled to form a predetermined logic function. One logic cell is used as a logic block, and all the input / output terminals of the logic cell are vertically raised to the uppermost signal wiring layer or the signal wiring layer immediately below it.

[0126]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) According to the first invention, since the terminal of the logic cell is pulled up to the uppermost signal wiring layer, processing for changing the connection path between the logic cells by on-chip modification, for example, It is possible to easily open a hole reaching the terminal of the logic cell and to embed the hole with a conductor, and in a short time. Therefore, it is possible to shorten the development period of a semiconductor integrated circuit device having a predetermined logic circuit configuration without lowering the yield due to logic modification.

Further, since the terminals of the logic cell are pulled up in a substantially vertical state, a conventional technique of providing a preliminary wiring, expanding a wiring pattern interval during wiring layout processing, or pulling up a predetermined wiring pattern portion It is possible to reduce the waste of channels as compared with.

(2) According to the second and third inventions, for example, a predetermined input terminal set as an unused terminal of a logic cell can be easily and easily applied by the on-chip correction technique even after the wafer process is completed. It becomes possible to switch to a usable state in a short time.

Further, since the unused input terminal of the logic cell can be made available by on-chip modification, the number of spare gates can be reduced and the degree of element integration of the semiconductor integrated circuit device can be improved.

(3) According to the fourth invention, for example, it becomes possible to switch the usable input terminals of the logic cell to the unusable state easily and in a short time even after the wafer process is completed. .

(4) According to the fifth invention, for example, a predetermined output terminal set as an unused terminal of a logic cell can be easily and quickly processed by the on-chip correction technique even after the wafer process is completed. It becomes possible to switch to a usable state.

(5) According to the sixth aspect of the invention, for example, by switching the unused spare gate to the non-operating state by the on-chip correction technique, the power supply to the spare gate can be stopped. It is possible to reduce the power consumption of the circuit device.

Further, the usable output terminal of the logic cell can be easily switched to the unusable state in a short time.

Further, since the unused output terminal of the logic cell can be used by on-chip modification, the number of spare gates can be reduced and the degree of element integration of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a flowchart showing a layout process in designing a wiring layout of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is an explanatory diagram schematically showing a cross section of a main part of a semiconductor integrated circuit device formed based on wiring layout design data created by the wiring layout process of FIG.

FIG. 3 is an explanatory view schematically showing the upper surface of FIG.

FIG. 4 is an explanatory diagram schematically showing the upper surface of the semiconductor integrated circuit device after the logic correction processing.

5 is a cross-sectional view taken along the line AA of FIG.

FIG. 6 is an explanatory diagram schematically showing a cross-sectional view of a main part of the semiconductor integrated circuit device after logic correction processing.

FIG. 7 is an explanatory view schematically showing a cross section of a main part of a semiconductor integrated circuit device formed based on wiring layout design data created by a wiring layout process which is another embodiment of the present invention.

8 is an explanatory view schematically showing a cross-sectional view of a main part of the semiconductor integrated circuit device of FIG. 7 after logic correction processing.

FIG. 9 is an explanatory view schematically showing a cross section of a main part of a semiconductor integrated circuit device formed based on wiring layout design data created by a wiring layout process which is another embodiment of the present invention.

10 is an explanatory diagram schematically showing a cross-sectional view of a main part of the semiconductor integrated circuit device of FIG. 9 after logic correction processing.

FIG. 11 is an explanatory diagram showing logic symbols of logic gates constituting a semiconductor integrated circuit device which is another embodiment of the present invention.

12 is an explanatory diagram schematically showing the logic gate of FIG.

13 is a plan view of the semiconductor integrated circuit device of FIG.

FIG. 14 is a cross-sectional view of essential parts of a semiconductor substrate.

15 is an explanatory diagram schematically showing the logic gate of FIG.

FIG. 16 is an explanatory diagram schematically showing a logic gate after on-chip modification.

17 is a fragmentary cross-sectional view of the semiconductor substrate of FIG. 14 after on-chip modification.

[Explanation of symbols]

1 wiring layer 2 wiring layer 3 wiring layer 4 wiring layer 5 wiring layer 6 wiring layer 7 logic gate (logic cell) 7a logic gate (logic cell) 7b logic gate (logic cell) 7c logic gate (logic cell) 7d logic gate ( Logic cell) 8a ₁ input terminal 8a ₂ pull-up input terminal 8b ₁ output terminal 8b ₂ pull-up output terminal 8c ₁ terminal 8c ₂ pull-up terminal 8d ₁ terminal 8d ₂ pull-up terminal 8e ₁ terminal 8e ₂ pull-up terminal 8f ₁ terminal 8f ₂ pull-up terminal 8 _IN1 pull-up input terminal 8 _IN2 pull-up input terminal 8 _IN3 pull-up input terminal 8 _OR pull-up output terminal 8 _NOR pull-up output terminal 8 _E1 pull-up terminal 8 _E2 pull-up terminal 8 _CS pull-up terminal (pull-up control terminal) 9a signal wiring 9b signal wiring 9c signal wiring 9d signal wiring 9e signal wiring 9f signal wiring 10 power wiring 10a isolated pattern 1 Vacant area 12 Through hole (connection hole path) 13 Interlayer insulating film 14 Surface protection film 15 Groove 16a hole 16b hole 16c Hole 17 Signal wiring 17a Conductor 17b Conductor pattern 18 Wiring (conductor pattern) 19 Low level wiring (wiring of a predetermined potential) 20 wiring (conductor pattern) 21 wiring (conductor pattern) 22 collector buried layer 23 collector layer 24 base layer 25 emitter layer W semiconductor wafer (semiconductor substrate) V _BB reference potential V _CC collector potential V _EE emitter potential V _CS wiring of predetermined potential IN ₁ input terminal IN ₂ input terminal IN ₃ input terminal OR output terminal NOR output terminal Q ₁ transistor Q ₂ transistor Q ₃ transistor Q ₄ transistor Q ₅ transistor Q ₆ transistor Q ₇ transistor R _C1 collector resistor R _C2 collector resistor R _C3 collector Resistance R _C4 Rectifier resistance R ₁ resistance R _E1 resistance R _E2 resistance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI technical display location 9169-4M H01L 21/82 F 7735-4M 21/88 A (72) Inventor Takeo Yamada Ome, Tokyo 2326 Imai, Hitachi Ltd. Device Development Center, Hitachi, Ltd. (72) Inventor Toru Kobayashi 2326 Imai Imai, Ome, Tokyo Inside Hitachi, Ltd. Device Development Center

Claims (11)

[Claims] 1. When designing a wiring layout of a semiconductor integrated circuit device having a multilayer wiring layer, all terminals of all logic cells laid out in a plurality of chip regions are made as vertical as possible by connection hole paths. A method of manufacturing a semiconductor integrated circuit device, characterized in that a layout process of pulling up to an uppermost signal wiring layer or a signal wiring layer immediately below it is preferentially performed, and then a layout process of wirings connecting the logic cells is performed. 2. When designing a wiring layout of a semiconductor integrated circuit device having a multi-layered wiring layer, a pair of terminals are connected to a pair of terminals from all terminal positions of all logic cells laid out in a chip area and positions in the vicinity thereof. The layout process of pulling up to the uppermost signal wiring layer or the signal wiring layer immediately below it is preferentially performed in a state where it is as vertical as possible by the route, and then the layout processing of the wiring connecting the logic cells is performed. A method for manufacturing a semiconductor integrated circuit device. 3. When designing a wiring layout of a semiconductor integrated circuit device having a multi-layered wiring layer, after performing a layout process of wiring for connecting a plurality of logic cells laid out in a chip area, the logic cells are connected to each other. Among the wiring to be connected, set one terminal at a place where there is no obstacle above in the wiring laid out under the uppermost signal wiring layer or the signal wiring layer immediately below it, and make that terminal as vertical as possible by the connection hole route. A method for manufacturing a semiconductor integrated circuit device, comprising: performing a layout process of pulling up to an uppermost signal wiring layer or a signal wiring layer immediately below in the state. 4. All the logic cells formed on the semiconductor substrate are formed by pulling up all the terminals of the logic cell in the uppermost signal wiring layer or the signal wiring layer immediately below it in a state as vertical as possible by the connection hole path. The predetermined pull-up input terminal cannot be used by short-circuiting or opening the predetermined pull-up input terminal and the wiring of the predetermined potential formed on the uppermost signal wiring layer or the layers immediately above and below it. A method for manufacturing a semiconductor integrated circuit device, characterized by switching to a normal state or a usable state. 5. The predetermined pull-up input terminal is used from an unusable state by cutting a conductor pattern for electrically connecting the wiring of the predetermined potential and the predetermined pull-up input terminal with an energy beam. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the state is switched to a possible state. 6. The logic circuit is formed by pulling up all terminals of all logic cells formed on a semiconductor substrate to the uppermost signal wiring layer or the signal wiring layer immediately below it in a state as vertical as possible by a connection hole path. Among the pull-up terminals, a predetermined pull-up output terminal and a pull-up terminal having a predetermined potential are short-circuited or opened to switch the predetermined pull-up output terminal to a usable state or an unusable state. Manufacturing method of semiconductor integrated circuit device. 7. A plurality of logic cells formed on a semiconductor substrate are formed by pulling up all the terminals of a plurality of logic cells to the uppermost signal wiring layer or the signal wiring layer immediately thereunder in a state as vertical as possible by a connection hole path. By selecting a short circuit / open circuit between the pull-up control terminal for controlling the operation / non-operation of the logic cell among the pull-up terminals and the wiring of a predetermined potential formed on the uppermost signal wiring layer or the layers immediately above and below it, A method of manufacturing a semiconductor integrated circuit device, comprising switching between operation and non-operation of the logic cell. 8. The logic cell is switched from a non-operating state to an operating state by cutting a conductor pattern for electrically connecting the pull-up control terminal and the wiring of the predetermined potential with an energy beam. The method for manufacturing a semiconductor integrated circuit device according to claim 7. 9. A plurality of logic cells formed on a semiconductor substrate are formed by pulling all terminals of the logic cells in the uppermost signal wiring layer or the signal wiring layer immediately thereunder in a state as vertical as possible by a connection hole path. A semiconductor integrated circuit device characterized in that a predetermined pull-up input terminal among pull-up terminals is electrically connected to a wiring of a predetermined potential formed on the uppermost signal wiring layer or the layers immediately above and below it. 10. A plurality of logic cells formed on a semiconductor substrate are formed by pulling up all the terminals of a plurality of logic cells to the uppermost signal wiring layer or the signal wiring layer immediately thereunder in a state as vertical as possible by a connection hole path. A semiconductor integrated circuit device comprising a pull-up terminal electrically connected to a predetermined pull-up output terminal and a predetermined pull-up terminal. 11. A plurality of logic cells formed on a semiconductor substrate are formed by pulling up all the terminals of a plurality of logic cells to the uppermost signal wiring layer or the signal wiring layer immediately below it in a state as vertical as possible by a connection hole path. The pull-up control terminal for controlling the operation / non-operation of the logic cell among the pull-up terminals and the wiring of a predetermined potential formed on the uppermost signal wiring layer or the layers immediately above and below the signal wiring layer are electrically connected. Integrated circuit device.