JPH05199398A - Image processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] The image quality of the output image is improved and the size and position of the image are clarified by performing automatic non-rectangular frame erasure on the image signal and forming a frame at the same time. A line sensor 13 for inputting an image signal representing an image and its peripheral portion, and a frame detection circuit 24 for detecting a boundary between the image and the peripheral portion based on the input image signal.
And an image processing circuit 26 that converts an image signal outside the detected boundary into a specific signal and forms an image signal representing a frame corresponding to the boundary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method, and more particularly to an image processing method for processing an image signal having a frame on the periphery of an image.

[0002]

2. Description of the Related Art Conventionally, in a microfilm having a negative image, a negative image is recorded in a frame f of the microfilm F as shown in FIG. 28A, and the periphery of each frame f is transparent. There is. When this microfilm F is printed out by a negative-positive reversal information recording device, the transparent portion around the frame f is developed. As a result, as shown in FIG. 28B, a solid black frame B is printed around the image area G on the transfer material P, which not only spoils the appearance of the printed image but also increases the toner consumption amount. There was a problem.

Therefore, in order to solve the above problem, the area of the image frame f of the microfilm F is detected, and the area to be recorded on the transfer material P is controlled based on the area determined based on the image area. As a result, an information recording apparatus has been proposed in which a frameless print is obtained as shown in FIG.

In this apparatus, image reading information at the time of image scanning is binarized by a predetermined threshold value and stored in a memory such as a RAM. This information is, for example, as shown in FIG. 29, where L _X and L _Y in the figure correspond to the horizontal and vertical lengths of the transfer paper P, respectively.

Then, an arithmetic circuit such as a CPU sequentially determines from the bit string of l ₁ of the data in the RAM whether or not one column contains all 0s or contains 1s, and one column contains all 0s.
In this case, this judgment is sequentially repeated with l ₁ , l ₂ , l ₃ ...
When the column l _n containing 1 is first discovered (l _{6 in the} illustrated example), the CPU sets the value L _F of the image recording area to n.

Further, the above operation is similarly performed at the left end and the upper and lower ends of the image area G, and the image recording areas l _x1 , l
Determine _Y and l _Y2 .

[0007]

However, the above-mentioned conventional example has the following drawbacks.

R for storing the image information of the entire image area
Since AM is required, a large amount of RAM is required,
The device becomes expensive and becomes large in size.

Further, since it is necessary to store the image information in the shared memory, it takes a long processing time.

Since only a rectangular frame can be erased, FIG.
If the image is inclined as shown in 0 (A), the frame remains. Further, when there are two or more images in one screen, a frame remains in the portion between them as shown in FIG. 30 (B), which may rather deteriorate the image quality.

After the frame is erased, the size and position of the image portion (or the original document) cannot be clearly understood because the ring spacing of the image portion is unclear as shown in FIG. 30 (c).

[0012]

The present invention has been made in view of the above points, and is based on an input means for inputting an image signal representing an image and its peripheral portion, and an image signal input from the input means. Detecting means for detecting a boundary between the image and the peripheral portion, converting means for converting an image signal outside the boundary detected by the detecting means into a specific signal, and the boundary detected by the detecting means. And a forming means for forming an image signal representing a frame corresponding to the above.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an external view of the present invention applied to a digital film reader for microfilm, and FIG.
Shows a schematic diagram thereof.

In FIGS. 1 and 2, reference numeral 1 is a scanner for projecting or reading a microfilm on a screen for image processing, and 2 is for image processing the image information read by the scanner 1 and then printing it on plain paper. Laser beam printer, 3 is an operation unit for performing various settings and displays, 4 is a roll carrier having a mechanism for sending and rewinding a photographed image of a roll film to a projection position by a knob on the operation unit 3. 5 is a projection zoom lens having a zoom mechanism, 6 is a screen for projecting a microfilm image, 7 is a halogen lamp for illuminating the microfilm, and 8 is for condensing diffused light of the halogen lamp. A condenser lens, 9 is a microfilm sandwiched between pressure plate glasses (not shown) in a roll carrier, 1 Is a reflection mirror for reflecting projection light, 11 is a sliding mirror for selecting screen projection or reading of a projected image, 12 is an axis for rotating the sliding mirror 11, 13 is for reading a projected image The line sensors 14, 15 are sensors for detecting the position of the line sensor.

The movement of image reading in the above configuration will be described.

First, the sliding mirror 11 is usually located at a position indicated by a broken line. At this time, the light irradiated on the microfilm 9 by the halogen lamp 7 and the condenser lens 8 is reflected by the reflection mirror 1.
0, it is projected on the screen 6 through the sliding mirror 11 (the optical path of the broken line).

When the copy button provided on the operation unit 3 is pressed, the sliding mirror 11 first moves to the position of the solid line about the axis 12, and the microfilm projection light follows the optical path of the solid line. At this time, the line sensor 13 departs from the home position sensor 14 and starts moving in the A direction (this direction is hereinafter referred to as a prescan). When the line sensor 13 is moved to the image light end position, the line sensor 13 engages with the start position sensor 15 and starts reversing movement in the B direction (hereinafter, this direction is referred to as a main scan). After that, when the line sensor 13 reaches the home position 14, the movement of the line sensor 13 stops and the sliding mirror 11 returns to the broken line position.

FIG. 3 is a schematic block diagram of an embodiment of the present invention, and FIG. 4 is an image processing circuit 26 and a frame detection circuit 24.
FIG. In the following description, the inversion of the signal is represented by * (for example, the inversion of the signal A is represented by the signal A
*).

In FIG. 3, 21 is a line sensor 1.
An amplifier for amplifying the image signal output 3 and an amplifier A for converting the amplifier output signal into a digital 8-bit signal.
/ D converter, 23 is a shading correction circuit for shading correction of the digitized image signal,
24 is a frame detection circuit for detecting a frame of an image from the shading-corrected image signal; 25 is data setting control for the frame detection circuit;
Alternatively, the CPU 26 for displaying and the like is an image processing circuit for performing various kinds of image processing on the image signal subjected to shading correction.

Next, the image processing circuit 26 and the frame detection circuit 24
Detailed blocks of the above will be described with reference to FIG.

Reference numeral 101 is a binarization circuit for simply binarizing the original image signal VM having an 8-bit gradation, and 102 is a block bit addition circuit for bitwise adding the binarized image signal VMB. Reference numeral 103 denotes a binarization circuit for determining a value obtained by adding block bits, 104 denotes a signal binarized by the binarization circuit 103, and a detection signal for detecting a boundary point between an image portion and a frame portion by SIG. MBI, MBI
It is a detection signal generation circuit for generating T.

Reference numeral 105 is a 13-bit counter which counts by the image block GCLK in synchronization with the main scanning direction synchronizing signal, and 106 is an address correction circuit for correcting the delay (K) in the main scanning direction which occurs during block formation. A 13-bit adder 107 at a certain point is an image section rising address latch circuit that latches an address in the main scanning direction at the rising edge of the detection signal MBIT, and 108 is an image section rising edge that latches an address in the main scanning direction at the rising edge of the detection signal MBI. It is a downstream address latch circuit.

Reference numeral 109 is a synchronization signal HS generated for each T line.
A T line latch circuit that latches the output address signal NB of the rising address latch circuit 107 by the YNT signal and delays it, and a T line latch circuit 110 that similarly latches the output address signal NA of 108 by the HSYNT signal.

Reference numeral 11 is an address / timing conversion circuit A, 1 for generating timing from the address signals of NB and NA.
Reference numeral 12 is an address / timing conversion circuit B for generating timing from the output signals PB and PA of 109 and 110.

Gate circuits 113 to 117 will be described in detail later.

Reference numeral 118 is an edge enhancement circuit for edge enhancing the original image signal VM, and 119 is an error diffusion circuit for performing pseudo halftone processing of the edge enhanced 8-bit grayscale image signal by the error diffusion method. Is an image delay circuit for correcting a delay in the sub-scanning direction that occurs when the block is formed.

FIG. 5 is a schematic circuit diagram showing an example of the block bit addition circuit 102. Reference numeral 121 denotes a signal VMB obtained by binarizing the original image signal VM by the binarization circuit 101 and a GCKW signal as shown in FIG. (1 block in FIG. 16 for every 8 pixels), latch circuits 122 to 129 are cleared for each cycle of the HSYNW signal, 130 is an output signal VMB ′ of the latch circuit 121 and the line memories 122 to 122. An adder circuit A for adding the outputs (a to i) of 129, 131 to 138 is a latch circuit for latching the 4-bit output of the adder circuit A130 with the GCKW signal, 13
9 is the output of the adder circuit A130 and the latch circuits 131 to 13
8 is an adder circuit B for adding the outputs (A to I) of eight.

FIG. 6 is a circuit diagram showing an example of the adder circuit A130. 48, 49, 50, 51 and 52 are 1-bit full adders, and 53 and 54 are 1-bit half adders.

FIG. 7 is a circuit diagram showing an example of the adder circuit B139. 55, 56, 57 and 58 are 4-bit adders and 5
9 and 60 are 5 bit adders, 61 are 6 bit adders, 6
2 is a 7-bit adder.

FIG. 8 is a circuit diagram showing an example of the detection signal generation circuit 104. Reference numeral 41 denotes the judgment 2 by the binarization circuit 103.
An AND gate 42 for ANDing the binarized area signal AREA with the binarized signal SIG.
D latch for connecting to the output of No. 1 and creating an MBI signal which is inverted with the image clock signal GCLK, 43 is an SI
It is a JK flip-flop for creating an MBIT signal which rises at the first rise of the G signal and falls at the next fall of the HSYNC * signal.

FIG. 9 shows the rising address latch circuit 107.
And 44 is a circuit diagram showing an example of the falling address latch circuit 108, in which 44 is a D latch that latches at the rising edge of the MBIT signal, 45 is a D latch that latches that signal at the rising edge of the HSYNT signal, and 46 is a latch at the rising edge of the MBI signal. The D-latch 47 is a D-latch that further latches the signal at the rising edge of the HSYNT signal.

FIG. 10 is a circuit diagram showing an example of the address / timing conversion circuit A111. 63 is a 13-bit adder for calculating the address obtained by subtracting the dot width D of the black frame in the main scanning direction from the address NB, and 64 is the same. Address N
1 to calculate the address with the dot width D added from A
3-bit adder, 65 to 68 is 1 GCLK when the address of each A input and the count address in the main scanning direction match.
13-bit equality comparators, 69 and 70, which output minute pulses, are NL from the pulses from the comparators 65 and 67 and the pulses from the comparators 66 and 68, respectively.
It is a JK flip-flop for producing M and NL signals.

FIG. 11 shows the address / timing conversion circuit B.
In the circuit diagram showing an example of 112, the connection is the same as in FIG.

71 and 72 are 13-bit adders, 73-
76 is a 13-bit equality comparator 77, 78
Is a JK flip-flop.

12 to 14 are schematic circuit diagrams showing an example of a delay circuit. 81 is a serial-parallel conversion circuit for converting the binary image signal VDI into serial-parallel, 82 is a latch for latching at the rising edge of the SPCLK signal, and 83, 84. Is RAM
(1) 3-state gate circuit for selecting output signal to 95 or RAM (2) 96, 85 for inverter, 86 for 8-bit selector for selecting input signal from RAM (1) 95 or RAM (2) 96, 87 is a latch for latching the output of the 8-bit selector at the rising timing of the PSLAT signal, 88 is a parallel-serial conversion circuit for converting the output of the latch 87 to parallel-serial, and 89 is RAM (1) 95, RA
M1RD that controls writing and reading to M (2) 96
*, M1WR *, M2RD *, M2WR * This is a selector that is a signal generation circuit.

Reference numeral 90 is a latch for setting the line count number, 91 is an 8-bit equality comparator which compares with the output of the 8-bit counter 93 and outputs a pulse when they match, 92 is an inverter, and 94 is an 8-bit equality comparator. Is a JK flip-flop for producing an inverted signal MSEL for each output of.

The operation will be described below step by step.

The original image signal VM has passed through a basic correction circuit such as shading correction and γ correction as shown in FIG. 3, and is also subjected to some filtering processing.

This original image signal VM is refl value, (r
efl is interlocked with the photometric value of the prescan), and is converted by the binarizing circuit 101 into a binary signal of 1 or 0. The block for one point X on the image has 9 × 9 sample points as shown in FIG. 22, and each sample point has a GCKW signal interval (here, 8 pixels) in the main scanning direction and a sub scanning direction in the sub scanning direction. The HSYNW signals are separated by an interval (here, 8 pixels). Therefore, the block size is 64 × 64 pixels.

Dust and dust on the microfilm are magnified by the magnification ratio. However, if dust is present in the frame, if the judgment block is small, the magnified dust and dust may cause malfunction. However, the larger the decision block is, the more memory is required. Therefore, the smallest memory is required, and it is an effective method to have such discrete sample points in order to prevent malfunction of dust and dust.

With this size, when a sensor of 400 dpi, for example, is used, no malfunction will occur up to an enlarged dust or dust of about 2 mm width.

Although FIG. 5 shows the block bit addition circuit 102, the image signal VM converted by the binarization circuit 101 is used.
B is marked by the D latch 121 at the rising edge of the GCKW signal, and sequentially stored by the line memories 122 to 129 at intervals of the HSYNW signal.

Then, the signals of 9 lines (a to i) are G
Bits are added at intervals of the CKW signal. For example, in FIG.
When the signals a to i are output as in 7, the adder circuit A13
The 4-bit output of output A of 0 (FIG. 6) is as shown in the figure.

Further, the 4-bit latches 131 to 138 sequentially store in the main scanning direction at intervals of the GCKW signal. Then, the adder circuit B139 calculates the sum of the bit addition signals for 9 lines at the points A to I. At this time, the 4-bit signals A to I are as shown in FIG. 18 when considered along with FIG. Then, the addition circuit B139 (FIG. 7), which is the sum thereof
The output SUM of is the result as shown by SUM in the figure.

The adder circuit A130 is as shown in FIG. 6, for example. The signals a, b and c are added by the 1-bit full adder 48 and converted into a 2-bit signal. Similarly, the d, e, and f signals are added by the 1-bit full adder 49 and converted into a 2-bit signal. Furthermore, the signals of g, h, and i are added by a 1-bit full adder 50 and converted into a 2-bit signal.

The upper 1 bit and the lower 1 bit of each 2-bit converted signal are separately calculated by the 1-bit full adders 51 and 25, and further converted into 4-bit signals by the half adders 53 and 54 (maximum 9).

The adder circuit B139 is, for example, as shown in FIG. 7, in which 4-bit signals of A and B, C and D, E and F, G and H are first added by the 4-bit adders 55 to 58, respectively. ,
It is converted to 5 bits, and this 5-bit signal is added by the 5-bit adders 59 and 60 to be converted to 6 bits.
Then, the 6-bit signal is added by the 6-bit adder 61 to be converted to 7 bits, and finally the 4-bit signal of I is added by the 7-bit adder 62 to obtain the sum SUM of A to I.
Is output.

The SUM thus obtained is the binarization circuit 1
03, a binary signal S of 1 or 0 as compared with ref2.
Convert to IG. Therefore, since this SIG is a signal obtained from the surrounding pixels almost on average, it has the effect of applying a low-pass filter with a large area, and becomes a stable signal against noise and dust. There is.

Next, this signal SIG is limited by the AND gate 41 by the frame elimination area signal AREA in the detection signal generation circuit 104 shown in FIG. 8, and then the D latch 42, JK.
The image fall detection signal MBI is generated by the flip-flop 43.
And the image rise detection signal MBIT. Basically MBI
In order to catch the edge of the image portion which comes first from the main scanning synchronization signal HSYNC, T rises at the first rising point of SIG and falls at the next rising edge of the HSYNC signal. Further, MBI inverts SIG in order to catch the edge of the last image portion when viewed from HSYNC.

The 13-bit counter 105 is a synchronous counter, which is cleared by the HSYNC * signal as shown in FIG. 15 and counts up at the rising edge of GCLK. 13 bits is the number of bits assuming 400 dpi A3 size main scanning, and varies depending on the resolution of the sensor and the image reading width.

By dividing into blocks, a delay occurs in both the main scanning and the sub-scanning, but in the main scanning direction, address correction is performed by the 13-bit adder 106. The correction value is K, but the following timing is K for convenience.
= 0. The address value of the main scanning direction counter thus corrected is set to HAD.

Address latch circuits 107 and 1 shown in FIG.
At 08, when an image exists, the MLAT signal latches the HAD signal once per line and the MBI signal latches the HAD signal at least once by the D latches 44 and 46. Further, for synchronization, the outputs of the D latches 44 and 46 are latched by the D latches 45 and 47 again at the rising edge of the HSYNT signal. The address signal thus latched is N
B and NA. Then, the address signals NB, NA
Further, the address signals PB and PA are latched at the rising edge of the HSYNT signal.

Then, in the address / timing conversion circuit A111 shown in FIG. 10, the 13-bit adder 63 calculates the NB-D address, and the 13-bit adder 64 also calculates the NA + D address. Then, the 13-bit equality comparator 6 is generated at the timing when the address values of NB-D, NB, NA + D, and NA match the address value HAD of the main scanning direction counter.
Pulses are output from 5 to 68. Then, the JK flip-flops 69 and 70 rise at the output of the 13-bit equality comparator 65, rise at the output of the 13-bit equality comparator 67, and rise at the output of the 13-bit equality comparator 66 to give the 13-bit equality comparator. The NL signal falling at the output of the priority comparator 68 is output.

Similarly, from the address signals PB and PA, the PLM and PL signals are output by the address / timing conversion circuit 112 shown in FIG.

19 and 20 are timing charts showing the process of forming a black frame at the edge of the image portion (hereinafter referred to as HS).
YNT is HSYNC (1 line).

The first signal in FIG. 19 is HSYNC *,
A pulse falling at one pulse (two GCLK cycles) is output to one line. The image area is this HSYNC *
It exists between the pulses of the signal, but in relation to the printer,
Normally, one line has a clock timing that is equal to or larger than the image reading width, and there are non-image areas before and after the image area.

FIG. 19 shows the timing when an image appears when there is no image in the sub-scanning direction.
The signal becomes 1. However, the SIG signal may become 0 because the character part of the image part is close to the density of the frame part. At this time, the address signal NB shows the first rising point of the SIG signal, and the address signal NA shows the last falling point of the SIG signal in one line.

Since the MBIT signal becomes 1 at the first rising of the SIG signal and becomes 0 at the next HSYNC * signal, the NB address is latched at the rising of the MBIT signal. Since the MBI signal rises several times in the image part, it is latched several times, but since the last rising address NA is latched in one line, NB is latched at the next HSYNC signal rising. , NA addresses are latched.

Accordingly, the newly created timings NL and NLM are as shown in the figure, and the timings PL and PLM created by the PB and PA addresses latched by HSYNC again are also as shown in the figure.

Then, the EXOR gate 11 shown in FIG.
The output of 3,114

[0061]

[Outer 1] And the OR output

[0062]

[Outside 2] Then, edge enhancement, error diffusion, and AND output of the image signals VD and NLM that have passed through the delay circuit

[0063]

[Outside 3] The waveform of each point is as shown in FIG. Image signal VD
Is indicated by diagonal lines.

As a result, in the line where the image first appears, the entire image area is made a black line, and the line after the next line (H
When SYNCT is not HSYNC and n lines are placed, the next n lines and thereafter) has a black band at the width of the edge of the image part in the main scanning direction set by D (see VDO signal).

Further, as shown in FIG. 20, when the SIG changes, the width of the black band changes like the VDO signal. Due to this change, as a result, the image shown in FIG.
It is converted into an image like 3 (B).

The edge enhancement circuit 118 uses a Laplacian 3 × 3 convolution mask. The mask coefficient is shown in FIG. Further, the error diffusion circuit 119 improves the halftone reproduction characteristic. As is well known, the error diffusion method (ED method) compares a certain pixel of interest with a certain threshold value,
This is a method of diffusing the generated error (the difference value between the density of the pixel of interest and the threshold value) to the density of the next plurality of pixels, which is one of typical pseudo halftone processing.

The delay circuit 120 will be described in detail with reference to FIGS.
It is configured like.

In FIG. 13, first, by the CPU (not shown), D
The number of delay lines is set in the latch 90 at the register write timing. The 8-bit counter 93 is cleared by the sub-scanning synchronizing signal VSYNC *, and the main-scanning synchronizing signal HSYNC.
Count up at the rising edge of NC. This counter 93
The output count signal of is input to the 8-bit equality comparator 91, compared with the number of delay lines described above, and when they match, a positive pulse for one line period is output.

The positive pulse becomes a negative pulse by the inverter 92, and the 8-bit counter 93 is reset. At the same time, the previous match signal is input to the JK flip-flop 94, and the toggled signal MS is output each time the match signal is output.
Output EL.

The output count signal of the 8-bit counter 93 is connected to the address buses MA10 to MA17 of the RAM (1) 95 and the RAM (2) 96. RA
Address bus MA9 of M (1) 95 and RAM (2) 96
To MA0 are address signals HAD12 to HAD obtained by adding a correction value to the count signal of the 13-bit counter 5 in the main scanning direction.
AD3 is connected. The lower 3 bits are not used because the data is converted from serial to parallel.

The output signal VD of the error diffusion circuit 19 in FIG.
I is an 8-bit serial-parallel converter 81 for serial-parallel signal conversion.

The SPCLK signal is GC as shown in FIG.
The signal of ⅛ cycle of the LK signal, the signal of serial-parallel conversion is latched by the D latch 82 by this SPCLK signal,
As a result, the serial signal carved with GCLK is GCLK /
It is converted into an 8-bit parallel signal that is divided by 8. This signal is a 3-state gate 8 when the previous MSEL signal is high.
Data is output from the RAM 3 to the RAM (2) 96, the 3-state gate 84 becomes high impedance, and when the MSEL signal is low, the 3-state gate 84 outputs the RAM.
(1) The data is output to 95 and the 3-state gate 83
Becomes high impedance.

At the same time, when the MSEL signal is High, the signal from the RAM (1) 95 is output to the output S of the 8-bit selector 86, and when the MSEL signal is Low, the output S of the 8-bit selector 86 is output to the RAM ( 2) The signal from 96 is output. This signal is latched by the D latch 8F at the rising edge of the PSLAT signal.

The PSLAT signal is GCLK as shown in FIG.
It is a signal of 1/8 cycle of the signal, and its rising point is SPCLK.
This is a half point of the signal rising period. Then, the output signal of the D latch 8F is input to the parallel-serial converter 88, and P
Data is loaded by the SLOAD * signal, and serial image data V is loaded at the clock rising timing of the GCLK signal.
Output D.

The MSEL signal also serves as a select signal for the 4-bit selector 89, and M1RD *, M1
The WR *, M2RD *, and M2WR * are input to the RAM (1) 95 and the RAM (2) 96 at the timings shown in FIG. As a result, the read (RD) and write (WR) timings of the RAM (1) and RAM (2) are as shown in FIG. The memory write signal MWR * used for M1WR * and M2WR * is output at the timing shown in FIG.

By the above control, the serial image signal VDI is output as the serial image signal VD delayed by the set number of delay lines. The serial-to-parallel conversion is performed here in order to control a high-speed image signal with a low-speed (long access time) inexpensive RAM.

As described above, since image processing is performed by pipeline processing and automatic frame erasing is performed, only a few lines are required as an image memory, and an inexpensive and compact device can be provided. Further, since it is uneasy to carry out processing such as storing image information in the entire image area, the processing can be performed at high speed.

Further, since the frame erasing is not performed in a rectangular shape but can be performed in almost any shape, unnecessary frame portions can be erased with high precision, toner consumption can be reached, and a copy with good image quality can be obtained. Can be obtained.

Further, by edging the periphery of the image portion (inner portion of the frame), the ring gap of the image portion is raised,
The size and position of the image part can be clarified.

(Other Embodiments) The line memories 1 (22) to 7 (28) shown in FIG. 5 use 1-bit line memories, but the cycle of HSYNW * is 8 lines. Since the static line memory must be used, the cost becomes high. Therefore, the line memory of FIG.
FIG. 2 shows an example of configuration using D42505V (manufactured by NEC).
5 shows.

Read clock RC of line memory 79
The GCLKW signal is supplied to the K and write clock WCK terminals, and the HSYNC signal is supplied to the read reset RSTR * and write reset RSTW * terminals. Therefore, although the line memory contents are rewritten for each line, the SEL terminal of the 8-bit selector 80 is
Since the HSYNW signal is connected, HSYNW is n
In the case of the line cycle, the (n-1) line refreshes and rewrites the contents once written in the memory.

Therefore, a new VMB 'is written in the 0th bit line memory on the nth line, and thereafter, the 0th bit line memory content is the 1st bit and the 1st bit line memory content is the 2nd bit. One bit is written to each eye. As a result, a line memory of 8 lines can be performed every n lines.

In the above description, the original is a microfilm image, but the original is not particularly limited and may be applied to, for example, a digital copying machine or a paper scanner. In such a device, since the same size copying is mainly performed, the influence of dust and dust is small as it is not enlarged like microfilm, and the block bit addition circuit 102 may be a simplified one, and may be omitted in some cases. It is possible.

Since the edging width can be changed separately in the main and sub-scanning directions, edging as shown in FIGS. 26A and 26B is possible. However, the edging width is changed simultaneously in the main and sub-scanning directions. Can be easily achieved.

Further, the edge enhancement circuit 118 and the error diffusion circuit 119 are not particularly required constituent elements, and any image processing may be performed. Also, as shown in FIG. 27, if it is permissible for a part of the frame to be copied at the rear end, the delay circuit 120
Is also unnecessary.

Further, although the NLM signal is used on one side of the input of the AND gate 116, the frame can be erased equivalently by any of NL, PL and PLM. However, for each signal, there is a slight shift in the frame position and a difference in the frame disappearance width when the edging function is turned off.

As described above, at the time of image reading, the evaluation signals indicating the image portion or the frame portion corresponding to the read signals of the two lines in the main scanning direction which are separated from each other in the sub-scanning direction by a constant section are taken out and further evaluated. A signal with the border width added to both ends of the image part of the signal is taken out, and the non-rectangular frame is automatically erased from these signals. By making it, while improving the image quality of the output image,
The image area can be emphasized to clarify the size and position of the image.

Also, this system requires only a few line memories as an image memory, and since the processing can be performed almost in real time by pipeline processing, the system can be constructed inexpensively and at high speed. Image processing can be performed.

[0089]

As described above, according to the present invention, the boundary between the image and the peripheral portion is detected based on the image signal representing the image and the peripheral portion thereof, and the image signal outside the detected boundary is specified. Since a picture signal representing a frame is formed corresponding to the detected boundary while being converted into a signal, automatic non-rectangular frame erasure is performed, and at the same time a frame is created by drawing a boundary line between the image part and the frame part. By doing so, the image quality of the output image can be improved and the image area can be emphasized to clarify the size and position of the image.

[Brief description of drawings]

FIG. 1 is an external view of a digital reader printer.

FIG. 2 is a mechanism diagram of a digital reader printer.

FIG. 3 is a circuit block diagram of a digital reader printer.

FIG. 4 is a block diagram of an image processing circuit and a frame detection circuit.

FIG. 5 is a block diagram of a block bit addition circuit.

FIG. 6 is a block diagram of an adder circuit A.

FIG. 7 is a block diagram of an adder circuit B.

FIG. 8 is a block diagram of a detection signal generation circuit.

FIG. 9 is a block diagram of a rising / falling address latch circuit.

FIG. 10 is a block diagram of an address / timing conversion circuit A.

FIG. 11 is a block diagram of an address / timing conversion circuit B.

FIG. 12 is a block diagram of a delay circuit.

[13] A block diagram of a delay circuit.

FIG. 14 is a block diagram of a delay circuit.

FIG. 15 is a timing chart diagram.

FIG. 16 is a timing chart diagram.

FIG. 17 is a timing chart diagram.

FIG. 18 is a timing chart diagram.

FIG. 19 is a timing chart diagram.

FIG. 20 is a timing chart.

FIG. 21 is a timing chart diagram.

FIG. 22 is a diagram showing sample points.

FIG. 23 is a diagram showing an output example of an image.

FIG. 24 is a diagram showing filter coefficients.

FIG. 25 is a diagram showing another configuration of the line memory.

FIG. 26 is a diagram showing an output example of an image.

FIG. 27 is a diagram showing an output example of an image.

FIG. 28 is a diagram showing a conventional image output example.

FIG. 29 is a diagram showing the contents of a memory RAM.

FIG. 30 is a diagram showing a conventional image output example.

[Explanation of symbols]

 13 line sensor 24 frame detection circuit 26 image processing circuit 102 block bit addition circuit 104 detection signal generation circuit 107 rising address latch circuit 108 falling address latch circuit 111 address / timing conversion circuit A 112 address / timing conversion circuit B 120 delay circuit

Claims (1)

[Claims] 1. Input means for inputting an image signal representing an image and a peripheral portion thereof; detection means for detecting a boundary between the image and the peripheral portion based on the image signal input from the input means; The image forming apparatus includes: a converting unit that converts an image signal outside the boundary detected by the detecting unit into a specific signal; and a forming unit that forms an image signal representing a frame corresponding to the boundary detected by the detecting unit. An image processing device characterized by.