JPH05183448A - Error correction encoding and decoding device - Google Patents

Abstract

(57) [Summary] (Modified) [Objective] To improve the error correction capability of a convolutional code in an error correction coding / decoding apparatus including a systematic encoder with feedback as a coding circuit. [Structure] Bit inserting means 21 for inserting one or more bits into an information signal sequence input to an encoder 3 on the encoding side.
And an insertion bit calculating means 4 for calculating the value of this bit so that the value of the shift register of the encoder becomes a fixed value when this bit is input to the encoder. Insertion bit position storage means 41 for storing the insertion position in the signal sequence, and convolutional error correction for performing maximum likelihood decoding of the received signal by limiting the state transition corresponding to the bit using the information of the insertion position. Decoding means 5
And are provided. When the bit inserted in the information signal sequence is input to the encoder, the value of the shift register of the encoder becomes a fixed value, and the convolutional error correction decoding means 5 corresponds to the inserted bit in the path of the trellis diagram. You can narrow down the branch you want to do.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding / decoding device used in a digital communication device such as a digital car phone or a mobile phone, and more particularly, to an error correction capability of an information signal.

[0002]

2. Description of the Related Art Conventionally, in a digital radio communication system such as a digital car telephone, strong error correction coding is performed in order to maintain the transmission quality of information data above a certain level even with poor transmission line quality. As one of the error correction codings, "convolutional coding" is known in which information signals before and after sequentially input information signal sequences are combined and coded, and a decoding method of the convolutional code is known. As known as "Viterbi decoding", a maximum likelihood decoding using a trellis diagram is known.

In the error correction code decoding apparatus using the convolutional code, if the line bit error rate is too high and exceeds the correction capability of the convolutional code, the correct information signal cannot be reproduced in the error correction decoding. In addition, there was a problem that bit errors remained.

Therefore, in the conventional error correction, in order to reduce the bit error residual rate, a fixed value (0 or 1) of 1 bit or a plurality of bits is inserted into the information signal sequence to be error correction coded, and then the error correction is performed. Encoding is in progress.

In this way, at the time of error correction decoding, the state transition corresponding to the position of the bit (fixed bit) in which the fixed value is inserted can be limited to one value determined by the fixed bit value (0 or 1). Therefore, in the middle of the path of the trellis diagram, the branch can be narrowed down to one correct branch by the number of inserted bits, and the correction capability of the convolutional code, especially before and after the bit position where the fixed bit is inserted, can be obtained. The error correction capability for information signals can be improved.

This conventional error correction code decoding apparatus is shown in FIG.
As shown in FIG. 2, on the encoding side (a), a voice encoding circuit 1 for encoding a voice signal into, for example, a high-efficiency encoded digital voice signal, and one bit or a plurality of bits for all or some of the information signals. A fixed bit insertion unit 2 for inserting a fixed value of bits (0 or 1) and a convolutional error correction coding circuit 3 for error correction coding of a digital audio signal with fixed bits inserted are provided. The voice signal is converted into a high-efficiency coded digital voice signal which is error correction coded.

On the other hand, on the decoding side (b), a fixed bit insertion position storage circuit 42 for storing fixed bit insertion position information.
And a convolutional error correction decoding circuit 5 for decoding the input signal into a high-efficiency coded digital audio signal with transmission errors removed by using the fixed bit insertion position information stored in the storage circuit 42, and this circuit. A voice decoding circuit 6 that decodes the digital signal output by 5 into a voice signal is provided, and the received error-correction-coded high-efficiency coded digital voice signal is converted into a voice signal.

As the convolutional error correction coding circuit 3 of this error correction coding / decoding device, a coding circuit called a non-systematic encoder is used. This circuit has a coding rate R = 1 /
2. In the case of the number of shift registers ν = 2, as shown in FIG. 4A, the shift register R ₀ 31 and the shift register R ₀ 31 to which the information signals x ₀ , x ₁ , x ₂ ... Are sequentially input. and a shift register R ₁ 32 where the output signal of inputs, one transmission signal with exclusive OR operation 35 and the output signal of the shift register R ₁ 32 and the information signal is formed, also, the shift register R ₀ The value of the shift register R ₁ 32 is further subjected to exclusive OR operation 37 to the exclusive OR 36 of 31 and the information signal to form the other transmission signal, and these transmission signals are parallel-serial converted and output. ..

When a fixed bit (for example, x ₄ = 0) is inserted in the information signal, when the fixed bit (x ₄ ) is input to the encoding circuit, the shift register has one fixed value. Depends on the value of. Therefore, on the decoding side, it becomes possible to specify the option of the state transition corresponding to the information signal x ₄ of the trellis diagram, and the path for erroneously decoding x ₄ is selected as the finally selected path. The probability that the

In the convolutional code, there is a characteristic that a decoded bit error propagates. By thus inserting the fixed bit x ₄ and performing convolutional coding, the error correction probability of the information signal in the vicinity of x ₄ is obtained. Can be improved.

[0011]

However, the convolutional error correction coding circuit 3 includes a coding circuit called a systematic coder with feedback, in addition to the non-systematic coder.
This circuit has a coding rate R = 1/2 and the number of shift registers ν
= 2, as shown in FIG. 4B, the shift register R ₀ 33 and the shift register R ₁ 34 are provided, and the output signal of the shift register R ₁ 34 is changed to the shift register R ₀ 33. Is input to the shift register R ₀ 33 and the exclusive OR of the output signal of the shift register R ₀ 33 and the information signal (x ₀ , x ₁ , x ₂ ...).
8 is input to the shift register R ₁ 34. Further, the information signal and the output signal of the shift register R ₁ 34 are taken out as a transmission signal, parallel-serial converted and transmitted.

In this systematic encoder with feedback,
Even if the fixed bit (x ₄ = 0) is inserted into the information signal, the value of the shift register R ₀ 33 or R ₁ 34 is not determined only by the value of the fixed bit x ₄ . Therefore, on the decoding side, the state transition of the shift register cannot be narrowed down corresponding to the information signal x ₄ , and improvement of the error correction capability as in the non-systematic encoder cannot be desired.

The present invention solves such a conventional problem, and even when a systematic encoder with feedback is provided as an encoding circuit, a convolutional code is generated in the same manner as a non-systematic encoder. It is an object of the present invention to provide an error correction coding / decoding device capable of enhancing the correction capability of the.

[0014]

Therefore, in the present invention, in an error correction coding / decoding device having a systematic encoder with feedback as convolutional error correction coding means, the coding side inputs to the above-mentioned encoder. Bit inserting means for inserting one or more bits in the information signal sequence, and an insert bit operation for calculating the value of this bit so that the value of the shift register of the encoder becomes a fixed value when this bit is input to the encoder. Means for storing the insertion position of the bit in the information signal sequence on the decoding side, and limiting the state transition corresponding to the bit using the information of the insertion position. And a convolutional error correction decoding means for performing maximum likelihood decoding of the received signal.

Further, among the information signals coded by the systematic encoder with feedback, a significant bit having a high error sensitivity is arranged at the beginning or the end of the information signal sequence or near the insertion position of the bit to be inserted. Is provided.

Further, the convolutional error correction coding means has a built-in punctured coding means capable of changing the coding rate.

[0017]

In the error correction coding / decoding apparatus of the present invention, when the bits inserted in the information signal sequence are input to the systematic encoder with feedback, the value of the shift register of this encoder becomes a fixed value, and therefore the convolution In the error correction decoding means, the branch corresponding to the inserted bit can be narrowed down to a specific branch in the middle of the path of the trellis diagram, and the error correction capability can be improved.

Further, the bit arranging means arranges the important bit having a high error sensitivity in a position having a high error correction capability, that is, in the vicinity of the first, last or inserted bit position of the signal sequence.

Further, by changing the number of the inserted bits, the error correction capability also changes, but the coding rate of the punctured coding can be changed in association with it to improve the data transmission efficiency. There is.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the error correction code decoding apparatus of the present invention is
As shown in FIG. 1, on the encoding side (a), a voice encoding circuit 1 for encoding a voice signal into a high-efficiency encoded digital voice signal and all or part of error correction encoding should be performed. A bit insertion unit 21 that inserts a bit value into an information signal, an insertion bit value operation unit 4 that operates a bit value to be inserted, and a convolutional error correction that performs error correction coding on a signal sequence in which a bit value is inserted. And an encoding circuit 3,
The input voice signal is converted into an error-correction-coded high-efficiency coded digital voice signal.

On the other hand, on the decoding side (b), the bit insertion position storage circuit 41 for storing the bit insertion position information.
And a convolutional error correction decoding circuit 5 for decoding the convolutional error correction of the received digital voice signal using the bit insertion position information stored in the storage circuit 41, and the digital signal output by this circuit. A voice decoding circuit 6 for decoding into a voice signal is provided, and the received error correction coded high-efficiency coded digital voice signal is converted into a voice signal.

Further, the convolutional error correction coding circuit 3 in this error correction coding / decoding device is the systematic encoder with feedback described above, and the coding rate R = 1/2 and the number of shift registers ν = 2. In the case of, as shown in FIG.
A shift register R ₀ 33, and a shift register R ₁ 34, the output signal of the shift register R ₁ 34 inputs fed back to the shift register R ₀ 33, the shift register R ₀
An exclusive OR 38 of the output signal of 33 and the information signal (x ₀ , x ₁ , x ₂ ...) Is input to the shift register R ₁ 34, and the information signal and the output signal of the shift register R ₁ 34 are used as a transmission signal. It is taken out, converted into parallel to serial and sent out.

Next, the operation of the apparatus of this embodiment will be described.

From the convolutional error correction coding circuit 3, the values of the shift registers 33 and 34 of the systematic encoder with feedback are sent to the insertion bit value calculation unit 4, which in turn inserts the values. Based on the value, the bit value of the insertion bit that can set the value of the shift register of the encoder to a fixed value (for example, 0) is calculated. The calculated insertion bit value is sent to the bit inserting unit 21, and the bit inserting unit 21 inserts the value into the information series of the information signal to be error correction coded. The bit-inserted information signal sequence is error-correction coded by the convolutional error-correction coding circuit 3 and then transmitted.

On the other hand, on the decoding side, in the convolutional error correction decoding circuit 5, the bit insertion position information stored in the bit insertion position storage circuit 41 is used to change the state transition corresponding to the bit insertion position to the insertion bit. Viterbi decoding is performed while limiting to the branch specified by. Next, the decoded digital signal is converted into a voice signal in the voice decoding circuit 6.

Now, the value of the insertion bit for setting the value of the shift registers 33 and 34 to a fixed value of 0 will be described.

Information signals x ₀ , x ₁ , x ₂ , x ₃ , x ₄ ... Are sequentially input to the systematic encoder with feedback.
Of these, it is assumed that x ₄ is the inserted bit.

In the systematic encoder with feedback shown in FIG. 2, the following relational expression holds between the values of the shift registers R ₀ 33 and R ₁ 34 and the information signal which is the input value.

R ₀ (i + 1) = R ₁ (i) R ₁ (i + 1) = R ₀ (i) + x _{(i + 1)} or R ₀ (i + 2) = R ₀ (i) + x _{(i + 1)} R ₁ (i + 2) = R ₁ (i) + x _{(i + 2)} where i is an integer of i ≧ 0 and indicates the order of the information signals input to the systematic encoder with feedback, and + is an exclusive logic Indicates the sum.

Then, since there is a relation of R ₁ (4) = R ₀ (3) + x ₄ , if the bit insertion value is set to x ₄ = R ₀ (3), the exclusive OR of the same values is 0. Therefore, R ₁ (4) is always 0.

Therefore, since the shift registers R ₀ 33 and R ₁ 34 can originally take the values of ₀ and ₁ , four states are possible with the combination of R ₀ and R ₁ , but R ₁ Since the value of is determined in one way, the possible states of the combination of R ₀ and R ₁ are limited to two states. for that reason,
On the decoding side, the state transition of the shift register corresponding to the information signal x ₄ can be narrowed down to 2 out of the 4 options.

Furthermore, with x _4, when the _{x 5 x 5 = R 1 (} 3) performing bit insertion as, from the relationship of _{R 1 (5) = R 1} (3) + x 5, R 1 (5) is Must be 0.

From the relationship of R ₀ (5) = R ₁ (4), R ₀ (5) is always 0.

Therefore, in this case, since R ₀ (5) and R ₁ (5) both become 0 when i = 5, the state of the combination of R ₀ and R ₁ is fixed to one, and decoding is performed. On the conversion side, the state transition of the corresponding shift register can be narrowed down to one.

[0035] Thus, x ₄ with the value of the information signal sequence or by the x ₄ and x ₅ bits inserted,
The value of the shift register can be set to a fixed value, and accordingly, the decoding side can narrow down the state transition of the shift register corresponding to the bit insertion position in the Viterbi decoding of the error correction decoding. .. Therefore, the probability that a path that erroneously decodes x ₄ or x ₅ is selected as the finally selected path can be set to 0, and the error correction capability for the information signal can be improved.

Of the information signals to be error-corrected and decoded, important bits with high error sensitivity need to be transmitted without error. Therefore, the bits of such an information signal are placed at the beginning and the end of the encoding where the error correction capability of the convolutional code is originally high because the value of the shift register is 0, or in the vicinity of the inserted bit. By arranging them, high quality data transmission becomes possible.

In order to perform such data transmission,
A bit arranging unit that defines the arrangement order of the information signals in the information signal sequence is provided between the voice encoding circuit 1 and the bit inserting unit 21 of the encoding side circuit shown in FIG. The position at which important bits with high error sensitivity are rearranged to the first or last position of encoding, or the position at which bits are inserted by the bit insertion unit 21, based on the error sensitivity and importance of the information signal examined in 1. The sorting operation is performed in the vicinity of.

In the convolutional error correction coding circuit 3,
Encoding called punctured encoding has been performed to improve the transmission efficiency of data transmission. This is because, in the encoding circuit shown in FIG. 2, two signals are output each time one information signal is input, so, for example, if five information signals are input, ten signals are transmitted, In the punctured coding, if no problem occurs in the decoding on the decoding side, one of the output signals is periodically omitted, and 9 signals are input for 5 information signals. The transmission efficiency is improved by transmitting the output signal.

In this case, the ratio of signals to be omitted, or in other words, the coding rate, is related to whether or not decoding can be performed on the decoding side to the same extent as when the signals are omitted. There is.

In the error correction code decoding apparatus of the present invention, the error correction capability can be adjusted by increasing or decreasing the number of bits to be inserted in the information signal sequence. It is possible to flexibly change the coding rate of Chad coding. Therefore, it is possible to improve the efficiency of data transmission by incorporating punctured coding means capable of changing the coding rate in the convolutional error correction coding circuit and associating the number of inserted bits with the coding rate.

[0041]

As is apparent from the above description of the embodiments, the error correction coding / decoding apparatus of the present invention includes a systematic encoder with feedback as an encoding circuit, and is similar to the case of the non-systematic encoder. In addition, it is possible to enhance the error correction capability for the information signal before and after the insertion position of the insertion bit.

Further, according to the present invention, by appropriately setting the number of bits to be inserted, the punctured code rate of the convolutional code by the systematic encoder with feedback is made flexible, and thereby the data transmission can be performed. It is possible to improve efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram of an encoding side (a) and a decoding side (b) of an embodiment of an error correction code decoding apparatus of the present invention,

FIG. 2 is a block diagram of a systematic encoder with feedback used in the apparatus of the above embodiment,

FIG. 3 is an encoding side of an example of a conventional error correction code decoding apparatus.
Block diagrams of (a) and the decoding side (b),

FIG. 4 is a non-systematic encoder (a) used in a conventional device.
FIG. 3 is a block diagram of a systematic encoder with feedback (b).

[Explanation of symbols]

 1 voice coding circuit 2 fixed bit insertion unit 21 bit insertion unit 3 convolutional error correction coding circuit 31, 32, 33, 34 shift register 35, 36, 37, 38 exclusive OR 4 insertion bit value operation unit 41 bits Insertion position storage circuit 42 Fixed bit insertion position storage circuit 5 Convolutional error correction decoding circuit 6 Speech decoding circuit

Claims (3)

[Claims] 1. An error correction coding / decoding device comprising a systematic encoder with feedback as convolutional error correction coding means, wherein one or more bits are added to an information signal sequence input to the encoder on the coding side. A bit inserting means for inserting, and an insert bit calculating means for calculating the value of the bit so that the value of the shift register of the encoder becomes a fixed value when the bit is input to the encoder, On the side, insertion bit position storage means for storing the insertion position of the bit in the information signal sequence, and maximum likelihood decoding of the received signal by limiting the state transition corresponding to the bit using the information of the insertion position. And a convolutional error correction decoding means for performing the above. 2. Among the information signals encoded by the systematic encoder with feedback, important bits with high error sensitivity are arranged at the beginning or the end of the information signal sequence or near the bit insertion position by the bit insertion means. The error correction code decoding apparatus according to claim 1, further comprising a bit arranging unit. 3. The error correction code decoding according to claim 1 or 2, wherein the convolutional error correction coding means comprises punctured coding means capable of changing a coding rate. apparatus.