JPH05189837A - Electronic equipment - Google Patents

Abstract

(57) [Summary] [Purpose] To prevent the adverse effects of changes in the data in the nonvolatile memory. In the tape recorder, the system control circuit 7 writes and saves data from the buffer RAM 15 to the non-volatile memory 16 when the power is turned off, and transfers the data to the read buffer RAM 15 when the power is turned on for use. The non-volatile memory 16 has a front area 16A and a back area 16B, and double writing of the same data reduces the occurrence of data errors. [Effect] The destruction of the data in the nonvolatile memory 16 is reduced by the double writing of the data, and the adverse effect on the device due to the data destruction is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic equipment device,
In particular, the present invention relates to an electronic device that stores information in a non-volatile memory when power is turned off.

[0002]

2. Description of the Related Art A so-called non-volatile memory (NVRAM) is sometimes used to retain some data such as status information of electronic equipment even when the power is turned off. Since this non-volatile memory does not require power backup, it has an advantage that there is no risk of data loss due to battery exhaustion. However, the number of times data can be read and written is limited to, for example, about 10,000 to 100,000, and the time required for writing is a normal RAM (random access memory).
Is relatively long (slow in speed) and relatively large in write current. Therefore, if the data is written every time the data to be held changes, the life of the memory itself, response speed, power consumption, etc. Since it is disadvantageous in writing, the writing is performed when the electronic device is powered off.

For example, when a small rotary head type digital tape recorder (DAT) is assumed as an electronic device, an electronic tape counter, an electronic volume or the like is often used from the viewpoint of improving operability and downsizing, and a power source. It is necessary to hold these tape counter values and electronic volume values even when the power is off. The nonvolatile memory is used to hold these data.
In such a DAT, depending on the power off operation,
After writing the required data in the non-volatile memory, the circuit power supply is actually turned off.

[0004]

However, when the power is turned off during the data writing operation, for example, when the battery serving as the power source is removed or an accident such as a defective contact of the battery occurs, the above nonvolatile memory is used. Power is turned off while the latest data is not written to the static memory or during writing. In particular, if the power is turned off during writing, some of the written data may become an error, which may adversely affect the operation when the power is turned on next time. ..

Here, as a case where the power is turned off while writing data in the non-volatile memory, it is considered that the battery is taken out immediately after the stop operation is performed. This is a series of controls in which a control unit such as a microcomputer writes necessary data in a non-volatile memory and turns off the power after a predetermined time (for example, about 5 seconds) has elapsed since the stop operation was performed. Moreover, since the data writing speed to the non-volatile memory is slow, the battery may be removed during the writing operation of all data. In particular, in a small DAT or the like, a small memory chip of about 8 pins is often used in order to reduce the size and cost, and since data transfer is performed serially, a data writing time of 10 to 20 msec per word is required. In other words, it may take about 0.5 seconds to 1 second, or more, to write all the data, and the probability of removing the battery coincides with the operation of writing all the data.

In addition, the data written in the non-volatile memory may be changed or destroyed by, for example, electrostatic pulse or external noise. When such change or destruction of data occurs, Next, it may cause a failure when the power is turned on.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electronic apparatus capable of preventing adverse effects due to a change or destruction of data written in a nonvolatile memory. ..

[0008]

An electronic equipment device according to the present invention is an electronic equipment device having a non-volatile memory for writing and holding required data when the power is turned off. The above problem is solved by adding a parity to each block and writing all the blocks of the required data in the nonvolatile memory in a multiplexed manner (for example, double writing).

Further, in the electronic equipment device according to the present invention, in the electronic equipment device having the above configuration, when the data is read from the nonvolatile memory, the multiple written data are compared in the same corresponding block unit. The above-mentioned problem is solved by.

Here, by multiple-writing in the above-mentioned non-volatile memory, even if any one of the corresponding corresponding blocks has an error, the data can be corrected by the block that does not cause the error, and When the data does not match even though there is no error in any of the blocks, the data of any one block can be preferentially used to correct the data.

For example, double writing for all blocks,
Even if one block has an error, the other block corrects the data. In addition, matching between blocks is detected, and the data of the priority block is copied to the other block for correction. Then, after the transfer is completed, all data may be read out and reconfirmed.

[0012]

Since data is written in multiplex into the non-volatile memory, correct data will remain even if the power is turned off during data writing, or data failure or data destruction occurs due to electrostatic pulse, external noise, etc. Can be increased, and adverse effects can be prevented.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of an electronic device according to the present invention, in which the applicant of the present invention first applied for a patent application 0
3 shows a schematic block circuit configuration in which the present invention is applied to a small rotary head type digital audio tape recorder (DAT) proposed in the specification and drawings of No. 3-50518.

In FIG. 1, a mode changeover switch group 3, a volume switch group 4, and a power supply switch 5 for changing over and controlling the operation mode of the DAT are connected to an input control circuit 6, respectively. The mode changeover switch group 3 is, for example, the reproduction switch 3 for controlling the reproduction mode.
A, a recording switch 3B for controlling the recording mode, a fast-forward switch 3C for controlling the fast-forward mode, and a rewind switch 3D for controlling the rewind mode. The volume switch group 4 has, for example, a plus volume 4A for increasing the reproduction or recording volume and a minus volume 4B for decreasing the reproduction or recording volume.

When the operation switches are operated, the input control circuit 6 sends a control signal S _CT in response to the operation switches to the system control circuit 7 which uses, for example, a so-called microcomputer. The system control circuit 7 controls, for example, the volume display unit 11, the signal processing unit 12, and the tape drive unit 13 according to the control signal S _CT .

That is, when any one of the switches 3A to 3D of the mode changeover switch group 3 is turned on, the system control circuit 7 outputs the signal processing section control signal S _SP and the tape drive section control signal S _TP in response to this. Signal processing unit 12
And the tape drive unit 13 to output the signal processing unit 12 and the tape drive unit 1 according to the operated switch.
3 is controlled to switch to a predetermined mode.

When the positive volume switch 4A or the negative volume switch 4B of the volume switch group 4 is turned on, the system control circuit 7 outputs the volume display control signal S _VL and the signal processing unit control signal S _SP in response to this. By sending them to the volume display unit 11 and the signal processing unit 12, respectively, the playback or recording volume value of the DAT is controlled to a value according to the user's operation, and at the same time, the set volume value is set.
It is designed to be displayed.

A buffer RAM (random access memory) 15 is connected to the system control circuit 7 by a control bus BC, a data bus BD, and an address bus BA. For example, various data such as a volume value or a tape count value. Is written and the relevant data is D
It is rewritten each time it changes according to the operating state of the AT.

Further, a non-volatile memory (NVRAM) 16 is connected to the system control circuit 7, and is connected to the buffer RAM 15 by the chip select signal S _CS and the serial clock signal S _CK from the system control circuit 7. Then, various data such as the volume value and the tape count value, especially the data that needs to be held when the power is turned off are transferred as the data signal S _D. Specifically, for example, when the power switch 5 of the DAT is turned off, the holding data such as the volume value and the tape count value is transferred from the buffer RAM 15 to the NVRA.
It is transferred to M16 and written. In the case of a DAT with a so-called auto-off function, other than turning off the power switch 5, or even if the power switch 5 is not provided, after operating the mode changeover switch group 3 to set the stop mode, The power is automatically turned off when no input operation is performed for a certain time (for example, several seconds), and at the time of this off operation, data transfer from the buffer RAM 15 to the NVRAM 16 is performed.

Here, as shown in FIG. 2, the data structure in the NVRAM 16 is divided into blocks of a predetermined number of words (for example, every 8 words), and a parity word is added to each block. .. Further, the data of each block is written in multiples (for example, double writing).

Specifically, as the NVRAM 16, 16
(Bit) x 128 (word), that is, 2K
2K with a memory capacity of (2048) bits
1K of each bit is the front area 16A and the back area 16
B (or the first page 16A and the second page 16B), and the areas 16A and 16B are divided into eight blocks BLa to BLh and BLaa to BLhh, respectively. The addresses of these areas 16A and 16B are fixed and have a one-to-one correspondence.

As a concrete example of each data written in such eight blocks, a. Rewriting data, b. Manufacturing time constant first data, c. Manufacturing time constant second data, d.
Service data, e. Design constant first data, f. Design constant second data, g. Design constant third data, h. Design constant 4th data, etc. are mentioned. Above a. For example, as shown in FIG. 2, the rewrite data includes a tape count value, a reproduction volume value, a recording volume value, adjustment data, and the like in 7 words, and the parity of the data in the block in the 8th word, for example, from odd parity. Consists of
First block BLa and area 18 in area 16A
It is double-written in the first block BLaa in B. Similarly, each data b. ~ H. Is double-written in the second to eighth blocks BLb to BLh in the area 16A and the second to eighth blocks BLbb to BLhh in the area 16B, respectively, and is the last address in each block. Is added with the parity of the data in the block.

In contrast to the internal structure (memory map) of the NVRAM 16 as described above, the memory map of the buffer RAM 15 is as shown in FIG. 3, for example. In FIG. 3, for example, a storage area of 64 words at addresses 0 to 63 is divided into eight block storage areas 15a to 15h for every 8 words (one block). In each of these block storage areas 15a to 15h, the above N
Each block BLa to B in the area 16A of the VRAM 16
Each data of Lh is written respectively. In addition, the areas 15a to 1 in the buffer RAM 15
8 words block storage area 15 _NN other than 5h
As a so-called temporary block buffer area, the blocks BLaa to BLhh in the area 16B of the NVRAM 16 are sequentially written one by one. Here, the block storage area 15 _NN of FIG.
The block BL _NN of 8 indicates any one of the eight blocks BLaa to BLhh in the area 16B.

Next, the operation of writing data to the NVRAM 16 when the power is off will be described. As shown in the flowchart of FIG.
Data is transferred from the AM 15 to the NVRAM 16 and written. At this time, the two areas 16 of the NVRAM 16
Of A and 16B, first, area 16A of the table (first page)
Write first. After the data transfer of each block, the data of each block is read out from the NVRAM 16 and the data is verified (verified). After the data writing operation in the area 16A of the table (first page) including the read verify processing is completed for all eight blocks, the area 16B of the back (second page) similarly writes and reads the data of each block. The verification is carried out sequentially. Area 1 behind this (2nd page)
After the data write operation of all 8 blocks of 6B is completed, the front and back areas (first and second pages) areas 16A and 16B
Read all the data in, reconfirm and finish.

The above operation will be described in detail with reference to the flowchart of FIG. In the following description, block numbers 0 to 7 are sequentially assigned to the eight blocks BLa to BLh in the area 16A of the table (first page) of the NVRAM 16 so that any block number N _BL (= 0 to 7). )
_Let BL _N be the block. Also, eight blocks BL in the area 16B on the back side (second page) of the NVRAM 16
Block numbers 8 to 15 are sequentially assigned to aa to BLhh, and a block with an arbitrary block number N _BL (= 8 to 15) is BL.
_NN .

In the first step S1 of FIG. 4, a block counter for counting the block number N _BL is initialized, that is, N _BL is set to 0. In the next step S2, the start address of the corresponding block in the buffer RAM 15 is obtained based on the value (block number) N _BL of this block counter. In the next step S3, NVRA is calculated based on the block number N _BL.
The start address of the corresponding block BL _N in the area 16A of the table (first page) of M16 is obtained. In the next step S4, the block number N in the buffer RAM 15
Calculates the parity of the data in the block specified by _BL . Then, in the next step S5, the data of the block of the buffer RAM 15 is transferred (block transferred) to the corresponding block BL _N in the area 16A of the table (first page) of the NVRAM 16 and written. In the next step S6, the data written in the NVRAM 16 in the immediately preceding step S5 is read and confirmed (data collation and verification).
To do. In the next step S7, the count value of the block counter, namely (a N _BL +1 substituting N _BL) and the block number N _BL increment, whether the value N _BL reaches 8 at the next step S8 Determine. If NO (less than 8), the process returns to step S3, and the above-described data write operation (including read verify) is performed on the incremented block number N _BL . YES in step S8, that is, N _BL
When it is determined that = 8, the process proceeds to the next step S9.

From step S9 to step S15,
The operation corresponds to the data write (including read verify) operation for each block in the area 16B on the back side (second page) of the NVRAM 16, and the same operations as those in steps S2 to S8 described above are performed. That is, steps S9, S10, S12, S13, S14, and S
15 is each of the above-mentioned steps S2, S3, S5, S6,
These correspond to S7 and S8, respectively. However, the block number N _BL becomes 8 to 15, and NVRAM
Any one block BL _NN among the 8 blocks BLaa to BLhh in the area 16B on the back side (second page) of 16 is designated, and in the buffer RAM 15, N _BL −
The block of number 8 (0 to 7) will be designated.
As a result, the address 0 in the buffer RAM 15
Data of 8 blocks 64 words of ~ 63 is NVRAM
16 front and back areas (first and second pages) 16A, 16
It will be double-written on B. Note that the above step S
The step corresponding to the parity calculation processing for each block of 4 may be inserted between step S10 and step S11, but if the parity data calculated in step S4 is stored in the buffer RAM 15, Since this may be used as it is, this parity calculation process is omitted when writing data to the back area 16B. In step S15, it is determined whether or not the count value N _BL has reached 16. If NO, the process returns to step S9, and if YES, the process proceeds to the next step S16.

In step S16, NVRAM1
Areas 16A and 16B on the front and back of page 6 (first and second pages)
The data of all the blocks (16 blocks) written in is read and verified again. Then, in the next step S17, it is determined whether or not this verification is OK. If YES, the process proceeds to step S18 to perform a power down (power down) process, and if NO, the process proceeds to step S19 to NVRA.
An error display process for displaying the writing error of M16 is performed.

The above is an example of the double writing operation of data to the NVRAM 16 when the power is off. As a result, for example, when the battery is pulled out during the process of step S9 and thereafter, valid data is already written in the area 16A of the table (first page) of the NVRAM 16,
This can be used. Also, from step S2 to step S
If the battery is pulled out in the middle of the process up to 8, the parity correct data can be used for each block in the area 16A of the table (first page), and even if the data in the area 16A is destroyed. , The back of NVRAM 16 (second
Since the valid data of the previous time is written in the area 16B of (page), by using this, it is possible to prevent an adverse effect such as an accident.

Next, the NVRAM 1 when the power of the DAT is turned on
The data transfer operation from 6 to the buffer RAM 15 will be described with reference to the flowcharts of FIGS. When the power is turned on, after performing top priority initialization processing, N
The reading process of the VRAM 16 is performed. This is because one block of 8 words in the table (first page) area 16A is (in the area 15a of the buffer RAM 15) in order from the first block.
Read in the corresponding area of 15h), then back (2nd
Page) 8 words of the corresponding block of the area 16B are read into the temporary area (area 15 _NN ) of the buffer RAM 15 and the parity check (error detection, error detection,
(Correction) and after doing this for each 8 blocks,
After the initialization is completed, the process is moving to the main process.

That is, FIG. 5 shows a schematic operation of the whole reading of the NVRAM 16. First, at step S21.
Then, the block counter for counting the block number N _BL as described above is initialized (N _BL ← 0). In the next step S22, the data of the corresponding blocks in the front and back (first and second pages) areas 16A and 16B of the NVRAM 16 are transferred to the buffer RAM 15 based on the block number N _BL . Specifically, the block BL _N having a block number N _BL among the eight blocks BLa to BLh in the table area 16A of the NVRAM 16 is set to the buffer RAM 1
5 in the corresponding area of the block storage areas 15a to 15h, and the back area 16B of the NVRAM 16
8 blocks BLaa to BLhh, the block BL _NN having a block number of N _BL +8 is written in the temporary area 15 _NN of the buffer RAM 15. Next, the error detection and correction processing of step S23 is performed. This process will be described later with reference to FIG. Next, in step S24, it is determined whether or not 8 blocks have been completed. If NO, then in the next step S25, N _BL is incremented (N _BL ← N _BL +1) and the above step S2 is performed.
Returning to step 2, if YES, the process proceeds to step S26, and after the initialization is completed, the process proceeds to the main process.

Next, FIG. 6 shows a specific example of the error detection and correction processing in step S23. This Figure 6
In step S41, which will be described later,
In step 31, the parity check (error detection) is performed on the data in the block BL _N of the number N _BL of the table area 16A, and it is determined whether or not there is an error (OK). If YES (no error), the next step S32
Then, the parity check is performed for the data in the block BL _{NN with} the number N _BL +8 in the back area 16B,
It is determined whether there is no error (OK). Step S31
If it is determined to be NO (there is an error) in step S, step S
In step 35, the parity of the block BL _{NN in} the back area 16B is checked. If YES is determined in the above step S32, it means that both blocks BL _N and BL _NN of the front and back areas 16A and 16B have no error.
Proceed to the next step S33, and execute these blocks B
It is determined whether or not the L _N and BL _NN data match each other. If YES (coincidence), the process proceeds to step S24 in FIG.

In step S32, NO (block BL
_If it is determined that there is an error in only _NN ) or if it is determined as NO (mismatch) in step S33, the process proceeds to step S36, and the data in the block BL _N of the number N _BL of the front area 16A is stored in the back area 16B. Block BL _NN
Transfer to and copy. This can be done by transferring the data of the corresponding block BL _N in the areas 15a to 15h of the buffer RAM 15 to the corresponding block of the back area 16B of the NVRAM 16 and writing it. Then, the process returns to step S22 of FIG. At this time, the block number N _BL
Is not incremented, so in step S22 N
Data is transferred to the buffer RAM 15 from the blocks BL _N and BL _NN in the VRAM 16 corresponding to the same number N _BL as the previous time. However, the data of the block BL _{NN in} the back area 16B of the NVRAM 16 is the same as the above step S
The block BL _{N in the} table area 16A is rewritten by 36.
Since it is the same as the data of step S3, step S3
5 is determined as YES in all of S1, S32, and S33.
Can proceed to the next step S24.

If YES in step S35, there is an error in block BL _N , but block B _N
Since there is no error in L _NN , the process proceeds to step S37,
The data in the block BL _NN of the back area 16B is transferred to the block BL _N of the number N _BL of the front area 16A and copied. This may be achieved by transferring the data of the block BL _NN written in the temporary area 15 _NN of the buffer RAM 15 to the corresponding block BL _N of the table area 16A of the NVRAM 16 and writing it. Then, the process returns to step S22 of FIG. Also at this time, the block number N _BL
Is not incremented, and NVRA is calculated in step S22.
Data will be transferred to the buffer RAM 15 from the same block BL _N , BL _{NN of} M16.
The data of the block BL _N of 6A is obtained in the above step S36.
The data of the block BL _{NN in} the back area 16B has been rewritten in step S31, S3.
If YES is determined in 2 and S33, the process proceeds to the next step S24 in FIG.

In the step S36, the NVRAM1
After modifying the data of step S6, step S24 of FIG.
To the NVRAM16 in step S37.
Data of the corresponding block BL _N of the buffer RAM 15 are corrected at the same time, the process proceeds to step S24, and step S2 for the same block number is performed.
The second data transfer operation may be omitted.

If NO in step S35, it means that there is an error in both the blocks BL _N and BL _NN , and it cannot be corrected. Therefore, if necessary, retry again, and if that is not enough, step S3
Proceed to step 8 to display an error. Specifically, if NO in step S35, the process proceeds to step S42 to determine whether or not the number of times is the second time (whether or not the variable m is 2), and YES.
If so, the process proceeds to step S38. At the first time, it is determined as NO in Step S42, and Step S43
Then, the variable m is incremented, and the process is returned to the retry process, for example, the process after step S31. Prior to this step S31, the variable m is initialized (m
← 1) Insert step S41 to perform this step 41
It is arranged to be returned to the position immediately before step S31. If it is desired to perform this retry including the data transfer from the NVRAM 16 to the buffer RAM 15, the process is returned to immediately before step S22 in FIG. 5, and the initialization step of the variable m is performed before that. It should be inserted. The initialization value and step S42
The number of retries can be increased or decreased by changing the discriminant value in step S4, and if such a retry is not performed, steps S41, S42 and S4 shown by broken lines in FIG.
3 may be omitted.

As is apparent from the above description, for example, the buffer RAM 15 to the NVRAM 16 when the power is off.
If the user removes the battery while writing data to the NVRAM, or if some of the data in the NVRAM 16 is changed or destroyed due to computer runaway, electrostatic pulse, external noise, etc., the data will be blocked. It is possible to perform parity check for each block and to write each block twice, so that valid data can be read out while avoiding defective data or destroyed data, which adversely affects the operation after power is turned on. The risk of exerting it is drastically reduced, and the equipment failure rate can be reduced.

The present invention is not limited to the above-mentioned embodiments, and for example, the applicable device is not limited to the small rotary head type DAT, but can be applied to various electronic equipment devices.
In particular, it is preferable when applied to a battery-driven type small electronic device such as a small disc reproducing device or a small tape recorder.

[0039]

As is apparent from the above description, according to the electronic equipment device of the present invention, in the electronic equipment device having the non-volatile memory for writing and holding the required data when the power is turned off, the required data can be stored. It is divided into blocks for each predetermined number of words, parity is added to each block, and all blocks of the required data are multiple-written in the nonvolatile memory, so the power is turned off during data writing,
Even if data failure or data destruction occurs due to electrostatic pulse, external noise, etc., correct data will often remain,
In addition, a parity check is performed for each block to read valid data, so that the bad influence of defective data can be prevented.

Further, according to the electronic equipment device of the present invention, in the electronic equipment device having the above-mentioned configuration, when the data is read from the nonvolatile memory, the multiple written data are compared in the same corresponding block unit. Therefore, when data does not match in spite of no error in any block, data in any one block can be preferentially used for data correction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a small rotary head type digital audio tape recorder (DAT) as an embodiment of an electronic device apparatus according to the present invention.

FIG. 2 is a nonvolatile memory (NV used in the above embodiment
It is a figure which shows the specific example of the memory map of RAM.

FIG. 3 is a diagram showing a specific example of a memory map of a buffer RAM used in the above embodiment.

FIG. 4 is a flowchart for explaining an operation when the power is off in the above embodiment.

FIG. 5 is a flow chart for explaining the operation of the above embodiment when the power is turned on.

FIG. 6 is a flowchart for explaining error detection and correction processing by parity check in the above embodiment.

[Explanation of symbols]

 3 ... Mode changeover switch group 4 ... Volume switch group 6 ... Input control circuit 7 ... System control circuit 15 ... Buffer RAM 16 ...・ NVRAM (non-volatile memory) 16A: front (first page) area 16B: back (second page) area

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location G11B 27/00 A 8224-5D // G11B 33/00 Z 7177-5D

Claims (2)

[Claims] 1. An electronic device having a non-volatile memory for writing and holding required data when the power is turned off, the required data is divided into blocks for each predetermined number of words, and a parity is added to each block to obtain the required data. An electronic device apparatus, wherein all blocks are written in multiplex into the nonvolatile memory. 2. The electronic device apparatus according to claim 1, wherein when the data is read from the non-volatile memory, the multiple-written data are compared in the same corresponding block unit.